Merge branch 'turbostat' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

Pull turbostat update from Len Brown:
 "Updates to the turbostat utility.

  Just one kernel dependency in this batch -- added a #define to
  msr-index.h"

* 'turbostat' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux:
  tools/power turbostat: correct dumped pkg-cstate-limit value
  tools/power turbostat: calculate TSC frequency from CPUID(0x15) on SKL
  tools/power turbostat: correct DRAM RAPL units on recent Xeon processors
  tools/power turbostat: Initial Skylake support
  tools/power turbostat: Use $(CURDIR) instead of $(PWD) and add support for O= option in Makefile
  tools/power turbostat: modprobe msr, if needed
  tools/power turbostat: dump MSR_TURBO_RATIO_LIMIT2
  tools/power turbostat: use new MSR_TURBO_RATIO_LIMIT names
  x86 msr-index: define MSR_TURBO_RATIO_LIMIT,1,2
  tools/power turbostat: label base frequency
  tools/power turbostat: update PERF_LIMIT_REASONS decoding
  tools/power turbostat: simplify default output

diff --combined arch/x86/include/uapi/asm/msr-index.h
index 1a4eae695ca8ace1c93b317e0f1d054875b0b03d,fe01b0a784e7ea951e2dce7abbf39092599b7081..c469490db4a8d4a0c7ac7e71b17053fbd62b12e4
--- 1/arch/x86/include/uapi/asm/msr-index.h
--- 2/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@@ -61,6 -61,9 +61,9 @@@
  #define MSR_OFFCORE_RSP_1             0x000001a7
  #define MSR_NHM_TURBO_RATIO_LIMIT     0x000001ad
  #define MSR_IVT_TURBO_RATIO_LIMIT     0x000001ae
+ #define MSR_TURBO_RATIO_LIMIT         0x000001ad
+ #define MSR_TURBO_RATIO_LIMIT1                0x000001ae
+ #define MSR_TURBO_RATIO_LIMIT2                0x000001af
  
  #define MSR_LBR_SELECT                        0x000001c8
  #define MSR_LBR_TOS                   0x000001c9
@@@ -74,24 -77,6 +77,24 @@@
  #define MSR_IA32_PERF_CAPABILITIES    0x00000345
  #define MSR_PEBS_LD_LAT_THRESHOLD     0x000003f6
  
 +#define MSR_IA32_RTIT_CTL             0x00000570
 +#define RTIT_CTL_TRACEEN              BIT(0)
 +#define RTIT_CTL_OS                   BIT(2)
 +#define RTIT_CTL_USR                  BIT(3)
 +#define RTIT_CTL_CR3EN                        BIT(7)
 +#define RTIT_CTL_TOPA                 BIT(8)
 +#define RTIT_CTL_TSC_EN                       BIT(10)
 +#define RTIT_CTL_DISRETC              BIT(11)
 +#define RTIT_CTL_BRANCH_EN            BIT(13)
 +#define MSR_IA32_RTIT_STATUS          0x00000571
 +#define RTIT_STATUS_CONTEXTEN         BIT(1)
 +#define RTIT_STATUS_TRIGGEREN         BIT(2)
 +#define RTIT_STATUS_ERROR             BIT(4)
 +#define RTIT_STATUS_STOPPED           BIT(5)
 +#define MSR_IA32_RTIT_CR3_MATCH               0x00000572
 +#define MSR_IA32_RTIT_OUTPUT_BASE     0x00000560
 +#define MSR_IA32_RTIT_OUTPUT_MASK     0x00000561
 +
  #define MSR_MTRRfix64K_00000          0x00000250
  #define MSR_MTRRfix16K_80000          0x00000258
  #define MSR_MTRRfix16K_A0000          0x00000259
@@@ -165,6 -150,11 +168,11 @@@
  #define MSR_PP1_ENERGY_STATUS         0x00000641
  #define MSR_PP1_POLICY                        0x00000642
  
+ #define MSR_PKG_WEIGHTED_CORE_C0_RES  0x00000658
+ #define MSR_PKG_ANY_CORE_C0_RES               0x00000659
+ #define MSR_PKG_ANY_GFXE_C0_RES               0x0000065A
+ #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
+ 
  #define MSR_CORE_C1_RES                       0x00000660
  
  #define MSR_CC6_DEMOTION_POLICY_CONFIG        0x00000668