Merge branch 'master' of git://git.denx.de/u-boot-coldfire

diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 8e9251d4aa51f839a83e5365acdb52575a9eb0b4..b2d6f8479a7aa1e971fb31f134cfbb77ca20e959 100644 (file)
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -283,6 +283,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 #if defined(CONFIG_SYS_MBAR)
        print_num ("mbar",              bd->bi_mbar_base);
 #endif
+       print_str ("cpufreq",           strmhz(buf, bd->bi_intfreq));
        print_str ("busfreq",           strmhz(buf, bd->bi_busfreq));
 #ifdef CONFIG_PCI
        print_str ("pcifreq",           strmhz(buf, bd->bi_pcifreq));
@@ -322,7 +323,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
        puts ("\nip_addr     = ");
        print_IPaddr (bd->bi_ip_addr);
 #endif
-       printf ("\nbaudrate    = %d bps\n", bd->bi_baudrate);
+       printf ("\nbaudrate    = %ld bps\n", bd->bi_baudrate);
 
        return 0;
 }

diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 66f9164d562971bb17a398d43985402b85d2148a..11f70b0dbf21bbf0896e406eeaa60f4b490fc987 100644 (file)
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -181,9 +181,14 @@ void cpu_init_f(void)
        /* FlexBus Chipselect */
        init_fbcs();
 
+#ifdef CONFIG_SYS_MCF_SYNCR
+       /* Set clockspeed according to board header file */
+       mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
+#else
        /* Set clockspeed to 100MHz */
-       mbar_writeShort(MCF_FMPLL_SYNCR,
+       mbar_writeLong(MCF_FMPLL_SYNCR,
                        MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
+#endif
        while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
 }
 
@@ -219,7 +224,8 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 {
        if (setclear) {
                /* Enable Ethernet pins */
-               mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
+               mbar_writeByte(MCF_GPIO_PAR_FECI2C,
+                              (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
        } else {
        }
 

diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c
index fe51fb480352751db237547a782a8efa2182f19a..c93a5180eb5702f3e84928dc7ad07a6d60eca056 100644 (file)
--- a/cpu/mcf52x2/speed.c
+++ b/cpu/mcf52x2/speed.c
@@ -77,7 +77,8 @@ int get_clocks (void)
 #endif
 
        gd->cpu_clk = CONFIG_SYS_CLK;
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5275)
+#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || \
+    defined(CONFIG_M5271) || defined(CONFIG_M5275)
        gd->bus_clk = gd->cpu_clk / 2;
 #else
        gd->bus_clk = gd->cpu_clk;

diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c
index 2b733c66e306b0d9d635bb7afe19e37c47eab2b1..4f1c0a0127b174971977be98b31dd6dc37f60a6d 100644 (file)
--- a/drivers/net/mcfmii.c
+++ b/drivers/net/mcfmii.c
@@ -226,7 +226,8 @@ void __mii_init(void)
        volatile FEC_T *fecp;
        struct eth_device *dev;
        int miispd = 0, i = 0;
-       u16 autoneg = 0;
+       u16 status = 0;
+       u16 linkgood = 0;
 
        /* retrieve from register structure */
        dev = eth_get_dev();
@@ -250,22 +251,32 @@ void __mii_init(void)
 
        info->phy_addr = mii_discover_phy(dev);
 
-#define AUTONEGLINK            (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS)
        while (i < MCFFEC_TOUT_LOOP) {
-               autoneg = 0;
-               miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg);
+               status = 0;
                i++;
-
-               if ((autoneg & AUTONEGLINK) == AUTONEGLINK)
+               /* Read PHY control register */
+               miiphy_read(dev->name, info->phy_addr, PHY_BMCR, &status);
+
+               /* If phy set to autonegotiate, wait for autonegotiation done,
+                * if phy is not autonegotiating, just wait for link up.
+                */
+               if ((status & PHY_BMCR_AUTON) == PHY_BMCR_AUTON) {
+                       linkgood = (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS);
+               } else {
+                       linkgood = PHY_BMSR_LS;
+               }
+               /* Read PHY status register */
+               miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &status);
+               if ((status & linkgood) == linkgood)
                        break;
 
                udelay(500);
        }
        if (i >= MCFFEC_TOUT_LOOP) {
-               printf("Auto Negotiation not complete\n");
+               printf("Link UP timeout\n");
        }
 
-       /* adapt to the half/full speed settings */
+       /* adapt to the duplex and speed settings of the phy */
        info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16;
        info->dup_spd |= miiphy_speed(dev->name, info->phy_addr);
 }

diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index e04fc298d960d8d338140db468a1022b6342753d..0b531402e4be44790f172fb1cf15c39e610a72e1 100644 (file)
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -115,8 +115,9 @@ void serial_setbrg(void)
        volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
        u32 counter;
 
-       counter = ((gd->bus_clk / gd->baudrate)) >> 5;
-       counter++;
+       /* Setting up BaudRate */
+       counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
+       counter = counter / gd->baudrate;
 
        /* write to CTUR: divide counter upper byte */
        uart->ubg1 = ((counter & 0xff00) >> 8);

diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h
index 787761689428e78d6f66514690231894513f8ef7..d25261bcd1b12e128469aa7ef39a0113dbca8351 100644 (file)
--- a/include/asm-m68k/m5271.h
+++ b/include/asm-m68k/m5271.h
@@ -37,8 +37,27 @@
 
 #define MCF_FMPLL_SYNCR                                0x120000
 #define MCF_FMPLL_SYNSR                                0x120004
+
 #define MCF_FMPLL_SYNCR_MFD(x)                 ((x&0x7)<<24)
+#define MCF_SYNCR_MFD_4X               0x00000000
+#define MCF_SYNCR_MFD_6X               0x01000000
+#define MCF_SYNCR_MFD_8X               0x02000000
+#define MCF_SYNCR_MFD_10X              0x03000000
+#define MCF_SYNCR_MFD_12X              0x04000000
+#define MCF_SYNCR_MFD_14X              0x05000000
+#define MCF_SYNCR_MFD_16X              0x06000000
+#define MCF_SYNCR_MFD_18X              0x07000000
+
 #define MCF_FMPLL_SYNCR_RFD(x)                 ((x&0x7)<<19)
+#define MCF_SYNCR_RFD_DIV1             0x00000000
+#define MCF_SYNCR_RFD_DIV2             0x00080000
+#define MCF_SYNCR_RFD_DIV4             0x00100000
+#define MCF_SYNCR_RFD_DIV8             0x00180000
+#define MCF_SYNCR_RFD_DIV16            0x00200000
+#define MCF_SYNCR_RFD_DIV32            0x00280000
+#define MCF_SYNCR_RFD_DIV64            0x00300000
+#define MCF_SYNCR_RFD_DIV128           0x00380000
+
 #define MCF_FMPLL_SYNSR_LOCK                   0x8
 
 #define MCF_WTM_WCR                            0x140000
@@ -50,17 +69,79 @@
 #define MCF_RCM_RCR_FRCRSTOUT                  0x40
 #define MCF_RCM_RCR_SOFTRST                    0x80
 
+#define MCF_GPIO_PODR_ADDR                     0x100000
+#define MCF_GPIO_PODR_DATAH                    0x100001
+#define MCF_GPIO_PODR_DATAL                    0x100002
+#define MCF_GPIO_PODR_BUSCTL                   0x100003
+#define MCF_GPIO_PODR_BS                       0x100004
+#define MCF_GPIO_PODR_CS                       0x100005
+#define MCF_GPIO_PODR_SDRAM                    0x100006
+#define MCF_GPIO_PODR_FECI2C                   0x100007
+#define MCF_GPIO_PODR_UARTH                    0x100008
+#define MCF_GPIO_PODR_UARTL                    0x100009
+#define MCF_GPIO_PODR_QSPI                     0x10000A
+#define MCF_GPIO_PODR_TIMER                    0x10000B
+
+#define MCF_GPIO_PDDR_ADDR                     0x100010
+#define MCF_GPIO_PDDR_DATAH                    0x100011
+#define MCF_GPIO_PDDR_DATAL                    0x100012
+#define MCF_GPIO_PDDR_BUSCTL                   0x100013
+#define MCF_GPIO_PDDR_BS                       0x100014
+#define MCF_GPIO_PDDR_CS                       0x100015
+#define MCF_GPIO_PDDR_SDRAM                    0x100016
+#define MCF_GPIO_PDDR_FECI2C                   0x100017
+#define MCF_GPIO_PDDR_UARTH                    0x100018
+#define MCF_GPIO_PDDR_UARTL                    0x100019
+#define MCF_GPIO_PDDR_QSPI                     0x10001A
+#define MCF_GPIO_PDDR_TIMER                    0x10001B
+
+#define MCF_GPIO_PPDSDR_ADDR                   0x100020
+#define MCF_GPIO_PPDSDR_DATAH                  0x100021
+#define MCF_GPIO_PPDSDR_DATAL                  0x100022
+#define MCF_GPIO_PPDSDR_BUSCTL                 0x100023
+#define MCF_GPIO_PPDSDR_BS                     0x100024
+#define MCF_GPIO_PPDSDR_CS                     0x100025
+#define MCF_GPIO_PPDSDR_SDRAM                  0x100026
+#define MCF_GPIO_PPDSDR_FECI2C                 0x100027
+#define MCF_GPIO_PPDSDR_UARTH                  0x100028
+#define MCF_GPIO_PPDSDR_UARTL                  0x100029
+#define MCF_GPIO_PPDSDR_QSPI                   0x10002A
+#define MCF_GPIO_PPDSDR_TIMER                  0x10002B
+
+#define MCF_GPIO_PCLRR_ADDR                    0x100030
+#define MCF_GPIO_PCLRR_DATAH                   0x100031
+#define MCF_GPIO_PCLRR_DATAL                   0x100032
+#define MCF_GPIO_PCLRR_BUSCTL                  0x100033
+#define MCF_GPIO_PCLRR_BS                      0x100034
+#define MCF_GPIO_PCLRR_CS                      0x100035
+#define MCF_GPIO_PCLRR_SDRAM                   0x100036
+#define MCF_GPIO_PCLRR_FECI2C                  0x100037
+#define MCF_GPIO_PCLRR_UARTH                   0x100038
+#define MCF_GPIO_PCLRR_UARTL                   0x100039
+#define MCF_GPIO_PCLRR_QSPI                    0x10003A
+#define MCF_GPIO_PCLRR_TIMER                   0x10003B
+
 #define MCF_GPIO_PAR_AD                                0x100040
+#define MCF_GPIO_PAR_BUSCTL                    0x100042
+#define MCF_GPIO_PAR_BS                                0x100044
 #define MCF_GPIO_PAR_CS                                0x100045
 #define MCF_GPIO_PAR_SDRAM                     0x100046
 #define MCF_GPIO_PAR_FECI2C                    0x100047
 #define MCF_GPIO_PAR_UART                      0x100048
+#define MCF_GPIO_PAR_QSPI                      0x10004A
+#define MCF_GPIO_PAR_TIMER                     0x10004C
+
+#define MCF_DSCR_EIM                           0x100050
+#define MCF_DCSR_FEC12C                        0x100052
+#define MCF_DCSR_UART                          0x100053
+#define MCF_DCSR_QSPI                          0x100054
+#define MCF_DCSR_TIMER                         0x100055
 
 #define MCF_CCM_CIR                            0x11000A
 #define MCF_CCM_CIR_PRN_MASK                   0x3F
 #define MCF_CCM_CIR_PIN_LEN                    6
-#define MCF_CCM_CIR_PIN_MCF5270                        0x2e
-#define MCF_CCM_CIR_PIN_MCF5271                        0x80
+#define MCF_CCM_CIR_PIN_MCF5270                        0x002e
+#define MCF_CCM_CIR_PIN_MCF5271                        0x0032
 
 #define MCF_GPIO_AD_ADDR23                     0x80
 #define MCF_GPIO_AD_ADDR22                     0x40

diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 7ddeb550b617357a797bd2825ff039b8a8a4f8ae..50b3ab2808494b90b8e6aca5cb0eb6600fe0c5b0 100644 (file)
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -82,7 +82,10 @@
 #define CONFIG_CMD_MISC
 
 #undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
@@ -116,7 +119,7 @@
 #define CONFIG_SYS_I2C_OFFSET          0x00000300
 #define CONFIG_SYS_IMMR                CONFIG_SYS_MBAR
 
-#define CONFIG_BOOTDELAY       1       /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY       1       /* autoboot after 1 seconds */
 #define CONFIG_BOOTFILE                "u-boot.bin"
 #ifdef CONFIG_MCFFEC
 #      define CONFIG_NET_RETRY_COUNT   5
@@ -128,16 +131,16 @@
 #      define CONFIG_OVERWRITE_ETHADDR_ONCE
 #endif                         /* FEC_ENET */
 
-#define CONFIG_HOSTNAME                M5235EVB
+#define CONFIG_HOSTNAME                M5271EVB
 #define CONFIG_EXTRA_ENV_SETTINGS              \
        "netdev=eth0\0"                         \
        "loadaddr=10000\0"                      \
-       "u-boot=u-boot.bin\0"                   \
-       "load=tftp ${loadaddr) ${u-boot}\0"     \
+       "uboot=u-boot.bin\0"            \
+       "load=tftp $loadaddr $uboot\0"  \
        "upd=run load; run prog\0"              \
-       "prog=prot off ffe00000 ffe2ffff;"              \
-       "era ffe00000 ffe2ffff;"                                \
-       "cp.b ${loadaddr} 0 ${filesize};"       \
+       "prog=prot off ffe00000 ffe3ffff;"      \
+       "era ffe00000 ffe3ffff;"                \
+       "cp.b $loadaddr ffe00000 $filesize;"    \
        "save\0"                                \
        ""
 
@@ -159,7 +162,17 @@
 #define CONFIG_SYS_MEMTEST_END         0x380000
 
 #define CONFIG_SYS_HZ                  1000000
+
+/* Clock configuration
+ * The external oscillator is a 25.000 MHz
+ * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk)
+ * bus_clk = (cpu_clk/2) (fixed ratio)
+ *
+ * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to
+ * match the new clock speed. Max cpu_clk is 150 MHz.
+ */
 #define CONFIG_SYS_CLK                 100000000
+#define CONFIG_SYS_MCF_SYNCR   (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1)
 
 /*
  * Low Level Configuration Settings
@@ -216,7 +229,14 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
-/* Port configuration */
-#define CONFIG_SYS_FECI2C              0xF0
+/* Chip Select 0  : Boot Flash */
+#define CONFIG_SYS_CS0_BASE    0xFFE00000
+#define CONFIG_SYS_CS0_MASK    0x001F0001
+#define CONFIG_SYS_CS0_CTRL    0x00001980
+
+/* Chip Select 1 : External SRAM */
+#define CONFIG_SYS_CS1_BASE    0x30000000
+#define CONFIG_SYS_CS1_MASK    0x00070001
+#define CONFIG_SYS_CS1_CTRL    0x00001900
 
 #endif                         /* _M5271EVB_H */