Merge branch 'fixes-non-critical' into for-next

* fixes-non-critical:
  ARM: dts: fix PL330 MDMA1 address in DT for Universal C210 board
  ARM: dts: Work around lack of cpufreq regulator lookup for exynos4210-origen and trats boards
  ARM: dts: Fix typo earlyprintk in exynos5440-sd5v1 and ssdk5440 boards
  ARM: dts: Correct typo in use of samsung,pin-drv for exynos5250
  ARM: rockchip: remove obsolete rockchip,config properties
  ARM: rockchip: fix wrong use of non-existent CONFIG_LOCAL_TIMERS
  ARM: mach-omap1: Fix omap1510_fpga_init_irq() implicit declarations.
  ARM: OMAP1: fix incorrect placement of __initdata tag
  ARM: OMAP: remove deprecated IRQF_DISABLED
  ARM: OMAP2+: throw the die id into the entropy pool

diff --combined arch/arm/boot/dts/rk3066a.dtsi
index 2218c64410de6c27c93d3acb15bd748be633dca2,98f3597a6a3570c7dd19adbbef1febf93b0db8ea..be5d2b09a363d15c66c648ab5079c9d1312226ce
--- 1/arch/arm/boot/dts/rk3066a.dtsi
--- 2/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@@ -14,12 -14,15 +14,12 @@@
   */
  
  #include <dt-bindings/gpio/gpio.h>
 -#include <dt-bindings/interrupt-controller/irq.h>
 -#include <dt-bindings/interrupt-controller/arm-gic.h>
  #include <dt-bindings/pinctrl/rockchip.h>
 -#include "skeleton.dtsi"
 +#include "rk3xxx.dtsi"
  #include "rk3066a-clocks.dtsi"
  
  / {
        compatible = "rockchip,rk3066a";
 -      interrupt-parent = <&gic>;
  
        cpus {
                #address-cells = <1>;
@@@ -40,6 -43,33 +40,6 @@@
        };
  
        soc {
 -              #address-cells = <1>;
 -              #size-cells = <1>;
 -              compatible = "simple-bus";
 -              ranges;
 -
 -              gic: interrupt-controller@1013d000 {
 -                      compatible = "arm,cortex-a9-gic";
 -                      interrupt-controller;
 -                      #interrupt-cells = <3>;
 -                      reg = <0x1013d000 0x1000>,
 -                            <0x1013c100 0x0100>;
 -              };
 -
 -              L2: l2-cache-controller@10138000 {
 -                      compatible = "arm,pl310-cache";
 -                      reg = <0x10138000 0x1000>;
 -                      cache-unified;
 -                      cache-level = <2>;
 -              };
 -
 -              local-timer@1013c600 {
 -                      compatible = "arm,cortex-a9-twd-timer";
 -                      reg = <0x1013c600 0x20>;
 -                      interrupts = <GIC_PPI 13 0x304>;
 -                      clocks = <&dummy150m>;
 -              };
 -
                timer@20038000 {
                        compatible = "snps,dw-apb-timer-osc";
                        reg = <0x20038000 0x100>;
@@@ -161,17 -191,14 +161,14 @@@
                                uart0_xfer: uart0-xfer {
                                        rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
                                                        <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                uart0_cts: uart0-cts {
                                        rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                uart0_rts: uart0-rts {
                                        rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
                        };
  
@@@ -179,17 -206,14 +176,14 @@@
                                uart1_xfer: uart1-xfer {
                                        rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
                                                        <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                uart1_cts: uart1-cts {
                                        rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                uart1_rts: uart1-rts {
                                        rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
                        };
  
@@@ -197,7 -221,6 +191,6 @@@
                                uart2_xfer: uart2-xfer {
                                        rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
                                                        <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
                                /* no rts / cts for uart2 */
                        };
@@@ -206,44 -229,36 +199,36 @@@
                                uart3_xfer: uart3-xfer {
                                        rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
                                                        <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                uart3_cts: uart3-cts {
                                        rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                uart3_rts: uart3-rts {
                                        rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
                        };
  
                        sd0 {
                                sd0_clk: sd0-clk {
                                        rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd0_cmd: sd0-cmd {
                                        rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd0_cd: sd0-cd {
                                        rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd0_wp: sd0-wp {
                                        rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd0_bus1: sd0-bus-width1 {
                                        rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd0_bus4: sd0-bus-width4 {
@@@ -251,34 -266,28 +236,28 @@@
                                                        <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
                                                        <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
                                                        <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
                        };
  
                        sd1 {
                                sd1_clk: sd1-clk {
                                        rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd1_cmd: sd1-cmd {
                                        rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd1_cd: sd1-cd {
                                        rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd1_wp: sd1-wp {
                                        rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd1_bus1: sd1-bus-width1 {
                                        rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
  
                                sd1_bus4: sd1-bus-width4 {
@@@ -286,9 -295,74 +265,8 @@@
                                                        <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
                                                        <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
                                                        <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
-                                       rockchip,config = <&pcfg_pull_default>;
                                };
                        };
                };
 -
 -              uart0: serial@10124000 {
 -                      compatible = "snps,dw-apb-uart";
 -                      reg = <0x10124000 0x400>;
 -                      interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 -                      reg-shift = <2>;
 -                      reg-io-width = <1>;
 -                      clocks = <&clk_gates1 8>;
 -                      status = "disabled";
 -              };
 -
 -              uart1: serial@10126000 {
 -                      compatible = "snps,dw-apb-uart";
 -                      reg = <0x10126000 0x400>;
 -                      interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 -                      reg-shift = <2>;
 -                      reg-io-width = <1>;
 -                      clocks = <&clk_gates1 10>;
 -                      status = "disabled";
 -              };
 -
 -              uart2: serial@20064000 {
 -                      compatible = "snps,dw-apb-uart";
 -                      reg = <0x20064000 0x400>;
 -                      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 -                      reg-shift = <2>;
 -                      reg-io-width = <1>;
 -                      clocks = <&clk_gates1 12>;
 -                      status = "disabled";
 -              };
 -
 -              uart3: serial@20068000 {
 -                      compatible = "snps,dw-apb-uart";
 -                      reg = <0x20068000 0x400>;
 -                      interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 -                      reg-shift = <2>;
 -                      reg-io-width = <1>;
 -                      clocks = <&clk_gates1 14>;
 -                      status = "disabled";
 -              };
 -
 -              dwmmc@10214000 {
 -                      compatible = "rockchip,rk2928-dw-mshc";
 -                      reg = <0x10214000 0x1000>;
 -                      interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -
 -                      clocks = <&clk_gates5 10>, <&clk_gates2 11>;
 -                      clock-names = "biu", "ciu";
 -
 -                      status = "disabled";
 -              };
 -
 -              dwmmc@10218000 {
 -                      compatible = "rockchip,rk2928-dw-mshc";
 -                      reg = <0x10218000 0x1000>;
 -                      interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 -                      #address-cells = <1>;
 -                      #size-cells = <0>;
 -
 -                      clocks = <&clk_gates5 11>, <&clk_gates2 13>;
 -                      clock-names = "biu", "ciu";
 -
 -                      status = "disabled";
 -              };
        };
  };

diff --combined arch/arm/mach-omap2/id.c
index 4f8f1cb3f5f76be68af9134147551a936451b81d,ef32d11c4bca6f5e08ead35d70f2177a85c68b8d..9428c5f9d4f2faa47e91a2caa193ecf39bba39fb
--- 1/arch/arm/mach-omap2/id.c
--- 2/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@@ -18,6 -18,7 +18,7 @@@
  #include <linux/kernel.h>
  #include <linux/init.h>
  #include <linux/io.h>
+ #include <linux/random.h>
  #include <linux/slab.h>
  
  #ifdef CONFIG_SOC_BUS
@@@ -130,6 -131,17 +131,17 @@@ void omap_get_die_id(struct omap_die_i
        odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
  }
  
+ static int __init omap_feed_randpool(void)
+ {
+       struct omap_die_id odi;
+ 
+       /* Throw the die ID into the entropy pool at boot */
+       omap_get_die_id(&odi);
+       add_device_randomness(&odi, sizeof(odi));
+       return 0;
+ }
+ omap_device_initcall(omap_feed_randpool);
+ 
  void __init omap2xxx_check_revision(void)
  {
        int i, j;
@@@ -576,8 -588,8 +588,8 @@@ void __init omap5xxx_check_revision(voi
        case 0xb942:
                switch (rev) {
                case 0:
 -                      omap_revision = OMAP5430_REV_ES1_0;
 -                      break;
 +                      /* No support for ES1.0 Test chip */
 +                      BUG();
                case 1:
                default:
                        omap_revision = OMAP5430_REV_ES2_0;
@@@ -587,8 -599,8 +599,8 @@@
        case 0xb998:
                switch (rev) {
                case 0:
 -                      omap_revision = OMAP5432_REV_ES1_0;
 -                      break;
 +                      /* No support for ES1.0 Test chip */
 +                      BUG();
                case 1:
                default:
                        omap_revision = OMAP5432_REV_ES2_0;

diff --combined arch/arm/mach-omap2/timer.c
index 89b6c23336c288a9bed7c894272f62befec66fc9,038d384ac2286ada34440c309e0d9f2db6032148..3ca81e0ada5e228e083ed591f0976174e2e6b972
--- 1/arch/arm/mach-omap2/timer.c
--- 2/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@@ -55,7 -55,6 +55,7 @@@
  #include "soc.h"
  #include "common.h"
  #include "powerdomain.h"
 +#include "omap-secure.h"
  
  #define REALTIME_COUNTER_BASE                         0x48243200
  #define INCREMENTER_NUMERATOR_OFFSET                  0x10
@@@ -67,15 -66,6 +67,15 @@@
  static struct omap_dm_timer clkev;
  static struct clock_event_device clockevent_gpt;
  
 +#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 +static unsigned long arch_timer_freq;
 +
 +void set_cntfreq(void)
 +{
 +      omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
 +}
 +#endif
 +
  static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  {
        struct clock_event_device *evt = &clockevent_gpt;
@@@ -88,7 -78,7 +88,7 @@@
  
  static struct irqaction omap2_gp_timer_irq = {
        .name           = "gp_timer",
-       .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+       .flags          = IRQF_TIMER | IRQF_IRQPOLL,
        .handler        = omap2_gp_timer_interrupt,
  };
  
@@@ -525,10 -515,6 +525,10 @@@ static void __init realtime_counter_ini
                num = 8;
                den = 25;
                break;
 +      case 20000000:
 +              num = 192;
 +              den = 625;
 +              break;
        case 2600000:
                num = 384;
                den = 1625;
@@@ -556,9 -542,6 +556,9 @@@
        reg |= den;
        __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
  
 +      arch_timer_freq = (rate / den) * num;
 +      set_cntfreq();
 +
        iounmap(base);
  }
  #else
@@@ -645,7 -628,7 +645,7 @@@ void __init omap4_local_timer_init(void
  #endif /* CONFIG_HAVE_ARM_TWD */
  #endif /* CONFIG_ARCH_OMAP4 */
  
 -#ifdef CONFIG_SOC_OMAP5
 +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
  void __init omap5_realtime_timer_init(void)
  {
        omap4_sync32k_timer_init();
@@@ -653,7 -636,7 +653,7 @@@
  
        clocksource_of_init();
  }
 -#endif /* CONFIG_SOC_OMAP5 */
 +#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
  
  /**
   * omap_timer_init - build and register timer device with an

diff --combined arch/arm/mach-rockchip/Kconfig
index 6fef4647b6fe462a65e6b285081a8ef21b50d0c2,a8487337344a963f11cbe17672f5d92a70a264ff..cf073dea5784b3c0fa125f1931305c55706f81e3
--- 1/arch/arm/mach-rockchip/Kconfig
--- 2/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@@ -5,14 -5,11 +5,13 @@@ config ARCH_ROCKCHI
        select ARCH_REQUIRE_GPIOLIB
        select ARM_GIC
        select CACHE_L2X0
-       select HAVE_ARM_TWD if LOCAL_TIMERS
+       select HAVE_ARM_TWD if SMP
        select HAVE_SMP
-       select LOCAL_TIMERS if SMP
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
        select DW_APB_TIMER_OF
 +      select ARM_GLOBAL_TIMER
 +      select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
        help
          Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
          containing the RK2928, RK30xx and RK31xx series.