Merge branch 'lwmon5-no-ocm'

diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index 6798e80985d63a4b1e70d6b48a2a0be09130506e..5aade72b52f302bab4415b8615f11d97207912fa 100644 (file)
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -57,7 +57,7 @@ tlbtab:
 
 #ifdef CFG_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-       tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+       tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 #endif
 
        /* TLB-entry for PCI Memory */

diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c
index 68aab5b7eab2d6ebda4daf6abe2d8d45f9ac051d..22156dd9ded363c8ae9b467314326a69f211cc6f 100644 (file)
--- a/cpu/ppc4xx/commproc.c
+++ b/cpu/ppc4xx/commproc.c
@@ -26,10 +26,21 @@
 
 #include <common.h>
 #include <commproc.h>
-
+#include <asm/io.h>
 
 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 
+#if defined(CFG_POST_ALT_WORD_ADDR)
+void post_word_store (ulong a)
+{
+       out_be32((void *)CFG_POST_ALT_WORD_ADDR, a);
+}
+
+ulong post_word_load (void)
+{
+       return in_be32((void *)CFG_POST_ALT_WORD_ADDR);
+}
+#else /* CFG_POST_ALT_WORD_ADDR */
 void post_word_store (ulong a)
 {
        volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
@@ -41,6 +52,7 @@ ulong post_word_load (void)
        volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR);
        return *(volatile ulong *) save_addr;
 }
+#endif /* CFG_POST_ALT_WORD_ADDR */
 
 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
 

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 52601ed7003ee3b3d86caeb2d7cf5289261f4840..a730604367d3d94635ad5d34b8dbb8ae9d1937e5 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -636,6 +636,33 @@ _start:
        dcbz    r0,r3
        addi    r3,r3,32
        bdnz    ..d_ag
+
+       /*
+        * Lock the init-ram/stack in d-cache, so that other regions
+        * may use d-cache as well
+        * Note, that this current implementation locks exactly 4k
+        * of d-cache, so please make sure that you don't define a
+        * bigger init-ram area. Take a look at the lwmon5 440EPx
+        * implementation as a reference.
+        */
+       msync
+       isync
+       /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
+       lis     r1,0x0201
+       ori     r1,r1,0xf808
+       mtspr   dvlim,r1
+       lis     r1,0x0808
+       ori     r1,r1,0x0808
+       mtspr   dnv0,r1
+       mtspr   dnv1,r1
+       mtspr   dnv2,r1
+       mtspr   dnv3,r1
+       mtspr   dtv0,r1
+       mtspr   dtv1,r1
+       mtspr   dtv2,r1
+       mtspr   dtv3,r1
+       msync
+       isync
 #endif /* CFG_INIT_RAM_DCACHE */
 
        /* 440EP & 440GR are only 440er PPC's without internal SRAM */
@@ -1345,6 +1372,31 @@ relocate_code:
        mr      r4,r10
        mr      r5,r11
 #endif
+
+#ifdef CFG_INIT_RAM_DCACHE
+       /*
+        * Unlock the previously locked d-cache
+        */
+       msync
+       isync
+       /* set TFLOOR/NFLOOR to 0 again */
+       lis     r6,0x0001
+       ori     r6,r6,0xf800
+       mtspr   dvlim,r6
+       lis     r6,0x0000
+       ori     r6,r6,0x0000
+       mtspr   dnv0,r6
+       mtspr   dnv1,r6
+       mtspr   dnv2,r6
+       mtspr   dnv3,r6
+       mtspr   dtv0,r6
+       mtspr   dtv1,r6
+       mtspr   dtv2,r6
+       mtspr   dtv3,r6
+       msync
+       isync
+#endif /* CFG_INIT_RAM_DCACHE */
+
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_440SP) || defined(CONFIG_440SPE)

diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 5210024d8f2863af209cc08dbecf24d5a3a83a90..0bf536b6b59ffe3f865158d74d7a8bc05785f790 100644 (file)
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -71,15 +71,20 @@
 /*-----------------------------------------------------------------------
  * Initial RAM & stack pointer
  *----------------------------------------------------------------------*/
-/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache    */
-#define CFG_INIT_RAM_ADDR      CFG_OCM_BASE    /* OCM                  */
-#define CFG_OCM_DATA_ADDR      CFG_OCM_BASE
-
+/*
+ * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
+ * the POST_WORD from OCM to a 440EPx register that preserves it's
+ * content during reset (GPT0_COM6). This way we reserve the OCM (16k)
+ * for logbuffer only.
+ */
+#define CFG_INIT_RAM_DCACHE    1               /* d-cache as init ram  */
+#define CFG_INIT_RAM_ADDR      0x70000000              /* DCache       */
 #define CFG_INIT_RAM_END       (4 << 10)
-#define CFG_GBL_DATA_SIZE      256             /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE      256             /* num bytes initial data*/
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_POST_WORD_ADDR     (CFG_GBL_DATA_OFFSET - 0x4)
-#define CFG_INIT_SP_OFFSET     CFG_POST_WORD_ADDR
+#define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
+#define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
+                                               /* unused GPT0 COMP reg */
 
 /*-----------------------------------------------------------------------
  * Serial Port

diff --git a/include/ppc440.h b/include/ppc440.h
index bfd1e10338de56d717b004a2dc25c0b8eaf86316..907744b87245eff210b9db0f9f97bd48f765c4b4 100644 (file)
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1362,8 +1362,6 @@
 #define plb1_bearl                (PLB_ARBITER_BASE+ 0x0C)
 #define plb1_bearh                (PLB_ARBITER_BASE+ 0x0D)
 
-#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 /* Pin Function Control Register 1 */
 #define SDR0_PFC1                    0x4101
 #define   SDR0_PFC1_U1ME_MASK         0x02000000    /* UART1 Mode Enable */
@@ -1429,7 +1427,7 @@
 #define   SDR0_MFR_PKT_REJ_EN1         0x00080000   /* Pkt Rej. Enable on EMAC3(1) */
 #define   SDR0_MFR_PKT_REJ_POL         0x00200000   /* Packet Reject Polarity */
 
-#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
+#define GPT0_COMP6                     0x00000098
 
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 #define SDR0_USB2D0CR                 0x0320

diff --git a/post/tests.c b/post/tests.c
index e1c3d28f5bd5704f8434f39ebc12a3f3d11edb22..0c49e324471036e9d2d2ac6dc20c0b6c4eeafa2d 100644 (file)
--- a/post/tests.c
+++ b/post/tests.c
@@ -194,7 +194,7 @@ struct post_test post_list[] =
        "SPR test",
        "spr",
        "This test checks SPR contents.",
-       POST_ROM | POST_ALWAYS | POST_PREREL,
+       POST_RAM | POST_ALWAYS,
        &spr_post_test,
        NULL,
        NULL,