drm/amd/powerplay: revise caching the soft pptable and add it's size

This fixes a bug in the pptable access interface that could lead to
a crash.  Check the pointer before using it.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
index 96a27876a704a488f9d25cd003301d61fa38f1ac..10e3630ee39d8d86c4897754274d70b451203328 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c
@@ -138,12 +138,15 @@ const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
 
        u16 size;
        u8 frev, crev;
-       void *table_address;
-
-       table_address = (ATOM_Tonga_POWERPLAYTABLE *)
-               cgs_atom_get_data_table(hwmgr->device, index, &size, &frev, &crev);
-
-       hwmgr->soft_pp_table = table_address;   /*Cache the result in RAM.*/
+       void *table_address = (void *)hwmgr->soft_pp_table;
+
+       if (!table_address) {
+               table_address = (ATOM_Tonga_POWERPLAYTABLE *)
+                               cgs_atom_get_data_table(hwmgr->device,
+                                               index, &size, &frev, &crev);
+               hwmgr->soft_pp_table = table_address;   /*Cache the result in RAM.*/
+               hwmgr->soft_pp_table_size = size;
+       }
 
        return table_address;
 }

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index b1a9ae509ed8415d8cd9ceaaa46f3f62850c2895..c96e5b1baae04addc389988a193e51529843dae2 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -577,6 +577,7 @@ struct pp_hwmgr {
        void *device;
        struct pp_smumgr *smumgr;
        const void *soft_pp_table;
+       uint32_t soft_pp_table_size;
        bool need_pp_table_upload;
        enum amd_dpm_forced_level dpm_level;
        bool block_hw_access;