]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
authorTom Rini <trini@ti.com>
Fri, 26 Sep 2014 13:51:18 +0000 (09:51 -0400)
committerTom Rini <trini@ti.com>
Fri, 26 Sep 2014 13:51:18 +0000 (09:51 -0400)
14 files changed:
arch/powerpc/config.mk
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
arch/powerpc/cpu/mpc8xxx/fdt.c
board/freescale/t1040qds/eth.c
board/freescale/t104xrdb/MAINTAINERS
board/freescale/t104xrdb/README
board/freescale/t104xrdb/ddr.c
board/freescale/t104xrdb/eth.c
board/freescale/t104xrdb/t1042_pi_rcw.cfg [new file with mode: 0644]
board/freescale/t104xrdb/t1042_rcw.cfg
configs/T1042RDB_defconfig [new file with mode: 0644]
drivers/net/fm/t1040.c
include/configs/B4860QDS.h
include/configs/T104xRDB.h

index 6329b6c74f57fccc898affe617dcb507d79c590e..fec02f2b82d727e3bf0f31d50677aea80533d6f9 100644 (file)
@@ -11,6 +11,7 @@ endif
 
 CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
 LDFLAGS_FINAL += --gc-sections
+LDFLAGS_FINAL += --bss-plt
 PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections \
                                                                -meabi
 PLATFORM_CPPFLAGS += -D__powerpc__ -ffixed-r2
index d1fc76a13ed25c99e7272b916288cd04fe1c1a41..8edf5bb20ef79dc834c5ec5467f03f9cce21c155 100644 (file)
@@ -186,11 +186,6 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
 #endif
 
        cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
-       /* Is serdes enabled at all? */
-       if (!cfg) {
-               printf("SERDES%d is not enabled\n", sd + 1);
-               return 0;
-       }
 
 /* Erratum A-007186
  * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
index 92737452994bc28a0fdee5a9c18af3a66d4b3626..4cec5e118ffc7d6666fde11e988cd3f7bbf02aa2 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2012 Freescale Semiconductor, Inc.
+ * Copyright 2009-2014 Freescale Semiconductor, Inc.
  *
  * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
  * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
@@ -123,14 +123,14 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 {
        const char *modes[] = { "host", "peripheral", "otg" };
        const char *phys[] = { "ulpi", "utmi" };
-       const char *dr_mode_type = NULL;
-       const char *dr_phy_type = NULL;
        int usb_mode_off = -1;
        int usb_phy_off = -1;
        char str[5];
        int i, j;
 
        for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+               const char *dr_mode_type = NULL;
+               const char *dr_phy_type = NULL;
                int mode_idx = -1, phy_idx = -1;
                snprintf(str, 5, "%s%d", "usb", i);
                if (hwconfig(str)) {
@@ -150,18 +150,16 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
                                }
                        }
 
-                       if (mode_idx < 0 || phy_idx < 0) {
-                               puts("ERROR: wrong usb mode/phy defined!!\n");
-                               return;
-                       }
-
-                       dr_mode_type = modes[mode_idx];
-                       dr_phy_type = phys[phy_idx];
-
                        if (mode_idx < 0 && phy_idx < 0) {
                                printf("WARNING: invalid phy or mode\n");
                                return;
                        }
+
+                       if (mode_idx > -1)
+                               dr_mode_type = modes[mode_idx];
+
+                       if (phy_idx > -1)
+                               dr_phy_type = phys[phy_idx];
                }
 
                usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
index 1929bba20b3b1215f48e124348ee1f374bc60e15..06d908658dad62098a8e39602d3d2d6cffbd6fe0 100644 (file)
@@ -241,6 +241,8 @@ static void initialize_lane_to_slot(void)
                break;
        case 0xA7:
                lane_to_slot[1] = 7;
+               lane_to_slot[2] = 6;
+               lane_to_slot[3] = 5;
                lane_to_slot[7] = 7;
                break;
        case 0xAA:
@@ -410,6 +412,8 @@ void t1040_handle_phy_interface_sgmii(int i)
                        fm_info_set_phy_address(i, riser_phy_addr[1]);
                if (FM1_DTSEC3 == i)
                        fm_info_set_phy_address(i, riser_phy_addr[2]);
+               if (FM1_DTSEC5 == i)
+                       fm_info_set_phy_address(i, riser_phy_addr[3]);
 
                mdio_mux[i] = EMI1_SLOT7;
                fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
index a4775c02e621f2b795c4be7c71578dd394338005..b61e1c025404d673f9c6e0056055868225b66635 100644 (file)
@@ -6,6 +6,7 @@ F:      include/configs/T104xRDB.h
 F:     configs/T1040RDB_defconfig
 F:     configs/T1040RDB_NAND_defconfig
 F:     configs/T1040RDB_SPIFLASH_defconfig
+F:     configs/T1042RDB_defconfig
 F:     configs/T1042RDB_PI_defconfig
 F:     configs/T1042RDB_PI_NAND_defconfig
 F:     configs/T1042RDB_PI_SPIFLASH_defconfig
index cdbe1fafd9a0ab384d0a26bc42d935fcb7b22417..ac95b5e5094da83c54b797b945f4e98784bbcf8e 100644 (file)
@@ -4,10 +4,23 @@ The T1040RDB is a Freescale reference board that hosts the T1040 SoC
 (and variants). Variants inclued T1042 presonality of T1040, in which
 case T1040RDB can also be called T1042RDB.
 
+The T1042RDB is a Freescale reference board that hosts the T1042 SoC
+(and variants). The board is similar to T1040RDB, T1040 is a reduced
+personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
+
 The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
 (a personality of T1040 SoC). The board is similar to T1040RDB but is
 designed specially with low power features targeted for Printing Image Market.
 
+Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
+-------------------------------------------------------------------------
+Board          Si              Protocol                Targeted Market
+-------------------------------------------------------------------------
+T1040RDB       T1040           0x66                    Networking
+T1040RDB       T1042           0x86                    Networking
+T1042RDB_PI    T1042           0x06                    Printing & Imaging
+
+
 T1040 SoC Overview
 ------------------
 The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
@@ -194,10 +207,10 @@ The below commands apply to the board
    Commands for switching to alternate bank.
 
        1. To change from vbank0 to vbank4
-               => qixis_reset altbank (it will boot using vbank4)
+               => cpld reset altbank (it will boot using vbank4)
 
        2.To change from vbank4 to vbank0
-               => qixis reset (it will boot using vbank0)
+               => cpld reset (it will boot using vbank0)
 
 NAND boot with 2 Stage boot loader
 ----------------------------------
@@ -259,15 +272,15 @@ Switch Settings: (ON is 0, OFF is 1)
 ===============
 NAND boot SW setting:
 SW1: 10001000
-SW2: 00111001
+SW2: 00111011
 SW3: 11110001
 
 SPI boot SW setting:
 SW1: 00100010
-SW2: 10111001
+SW2: 10111011
 SW3: 11100001
 
 SD boot SW setting:
 SW1: 00100000
-SW2: 00111001
+SW2: 00111011
 SW3: 11100001
index 34c9224adb67e11b5ee149894e2e6def9442e890..2c331eebf9e60710b0dddd6bf58dd0a9df2190bb 100644 (file)
@@ -105,8 +105,8 @@ found:
        popts->zq_en = 1;
 
        /* DHC_EN =1, ODT = 75 Ohm */
-       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
-       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 }
 
 phys_size_t initdram(int board_type)
index 63e5f900da73ec45b1b29b24ba8b21c01dd7d906..c8b6c672a683a2e5b19213e792a575e621003457 100644 (file)
@@ -42,6 +42,16 @@ int board_eth_init(bd_t *bis)
                        fm_info_set_phy_address(FM1_DTSEC3,
                                                CONFIG_SYS_SGMII1_PHY_ADDR);
                        break;
+#endif
+#ifdef CONFIG_T1042RDB
+               case PHY_INTERFACE_MODE_SGMII:
+                       /* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
+                       if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
+                               fm_info_set_phy_address(i, 0);
+                       /* T1042RDB only supports SGMII on DTSEC3 */
+                       fm_info_set_phy_address(FM1_DTSEC3,
+                                               CONFIG_SYS_SGMII1_PHY_ADDR);
+                       break;
 #endif
                case PHY_INTERFACE_MODE_RGMII:
                        if (FM1_DTSEC4 == i)
diff --git a/board/freescale/t104xrdb/t1042_pi_rcw.cfg b/board/freescale/t104xrdb/t1042_pi_rcw.cfg
new file mode 100644 (file)
index 0000000..57de89a
--- /dev/null
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x06
+0c18000e 0e000000 00000000 00000000
+06000002 00400002 e8106000 01000000
+00000000 00000000 00000000 00030810
+00000000 01fe0a06 00000000 00000000
index a3ea8ada56c816801ea9824c109df264e0fb35ed..db4d52f397d883af186be398d43430c4f9eeb8d3 100644 (file)
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 aa55aa55 010e0100
-# serdes protocol 0x66
+# serdes protocol 0x86
 0c18000e 0e000000 00000000 00000000
-06000002 00400002 e8106000 01000000
-00000000 00000000 00000000 00030810
-00000000 01fe0a06 00000000 00000000
+86000002 80000002 ec027000 01000000
+00000000 00000000 00000000 00032810
+00000000 0342500f 00000000 00000000
diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig
new file mode 100644 (file)
index 0000000..85eceb9
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
index bcc871d8420f7abbf4f954f3c6fa0525d26d9d46..4cce46d7f85014a510db7f8007a5539958f3db0a 100644 (file)
@@ -49,8 +49,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
                else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
                                FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
                        return PHY_INTERFACE_MODE_MII;
-               else
-                       return PHY_INTERFACE_MODE_NONE;
        }
 
        switch (port) {
index 953d06b53c4afc36fa7a012f08b6d8472002cd8a..9063c57b4092e73746553a539719875ea2f180a3 100644 (file)
@@ -227,6 +227,7 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 /* EEPROM */
+#define CONFIG_ID_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
@@ -819,9 +820,16 @@ unsigned long get_board_ddr_clk(void);
 
 #define __USB_PHY_TYPE ulpi
 
+#ifdef CONFIG_PPC_B4860
+#define HWCONFIG       "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
+                       "bank_intlv=cs0_cs1;"   \
+                       "en_cpc:cpc2;"
+#else
+#define        HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
+#endif
+
 #define        CONFIG_EXTRA_ENV_SETTINGS                               \
-       "hwconfig=fsl_ddr:ctlr_intlv=null,"             \
-       "bank_intlv=cs0_cs1;"                                   \
+       HWCONFIG                                                \
        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
        "netdev=eth0\0"                                         \
        "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
index d4c6f588b62b8b64330dd84599c560f7d7b1728e..5e2c100d9309b1b86cbc1ffa06e43031c0ddb076 100644 (file)
@@ -19,6 +19,9 @@
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
 #endif
 #ifdef CONFIG_T1042RDB_PI
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_rcw.cfg
+#endif
+#ifdef CONFIG_T1042RDB
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
 #endif
 
 
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR                0x70
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define I2C_MUX_CH_DEFAULT      0x8
 #endif
 
 #define CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_DPAA_PME
 
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define CONFIG_QE
 #define CONFIG_U_QE
 #endif
 #define CONFIG_SYS_FMAN_FW_ADDR                0xEFF00000
 #endif
 
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #if defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_QE_FW_ADDR          0x130000
 #elif defined(CONFIG_SDCARD)
 #endif
 
 #ifdef CONFIG_FMAN_ENET
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
 #define CONFIG_SYS_SGMII1_PHY_ADDR             0x03
 #endif
 #define CONFIG_SYS_RGMII1_PHY_ADDR             0x01
 #define CONFIG_BAUDRATE        115200
 
 #define __USB_PHY_TYPE utmi
+#define RAMDISKFILE    "t104xrdb/ramdisk.uboot"
 
 #ifdef CONFIG_T1040RDB
 #define FDTFILE                "t1040rdb/t1040rdb.dtb"
-#define RAMDISKFILE    "t1040rdb/ramdisk.uboot"
-#elif CONFIG_T1042RDB_PI
-#define FDTFILE                "t1040rdb_pi/t1040rdb_pi.dtb"
-#define RAMDISKFILE    "t1040rdb_pi/ramdisk.uboot"
+#elif defined(CONFIG_T1042RDB_PI)
+#define FDTFILE                "t1042rdb_pi/t1042rdb_pi.dtb"
+#elif defined(CONFIG_T1042RDB)
+#define FDTFILE                "t1042rdb/t1042rdb.dtb"
 #endif
 
 #ifdef CONFIG_FSL_DIU_FB