static void or1k_pic_mask(struct irq_data *data)
{
- mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->irq));
+ mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
}
static void or1k_pic_unmask(struct irq_data *data)
{
- mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->irq));
+ mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (1UL << data->hwirq));
}
static void or1k_pic_ack(struct irq_data *data)
{
/* EDGE-triggered interrupts need to be ack'ed in order to clear
* the latch.
- * LEVER-triggered interrupts do not need to be ack'ed; however,
+ * LEVEL-triggered interrupts do not need to be ack'ed; however,
* ack'ing the interrupt has no ill-effect and is quicker than
* trying to figure out what type it is...
*/
* as opposed to a 1 as mandated by the spec
*/
- mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->irq));
+ mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
#else
- WARN(1, "Interrupt handling possibily broken\n");
- mtspr(SPR_PICSR, (1UL << irq));
+ WARN(1, "Interrupt handling possibly broken\n");
+ mtspr(SPR_PICSR, (1UL << data->hwirq));
#endif
}
/* Comments for pic_ack apply here, too */
#ifdef CONFIG_OR1K_1200
- mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->irq));
+ mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(1UL << data->hwirq));
+ mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(1UL << data->hwirq));
#else
- WARN(1, "Interrupt handling possibily broken\n");
- mtspr(SPR_PICSR, (1UL << irq));
+ WARN(1, "Interrupt handling possibly broken\n");
+ mtspr(SPR_PICMR, (1UL << data->hwirq));
+ mtspr(SPR_PICSR, (1UL << data->hwirq));
#endif
}
void __delay(unsigned long cycles)
{
- cycles_t target = get_cycles() + cycles;
+ cycles_t start = get_cycles();
- while (get_cycles() < target)
+ while ((get_cycles() - start) < cycles)
cpu_relax();
}
EXPORT_SYMBOL(__delay);
{
unsigned long long loops;
- loops = xloops * loops_per_jiffy * HZ;
+ loops = (unsigned long long)xloops * loops_per_jiffy * HZ;
__delay(loops >> 32);
}
#define AUDIT_ARCH_MIPSEL (EM_MIPS|__AUDIT_ARCH_LE)
#define AUDIT_ARCH_MIPS64 (EM_MIPS|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_MIPSEL64 (EM_MIPS|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE)
+#define AUDIT_ARCH_OPENRISC (EM_OPENRISC)
#define AUDIT_ARCH_PARISC (EM_PARISC)
#define AUDIT_ARCH_PARISC64 (EM_PARISC|__AUDIT_ARCH_64BIT)
#define AUDIT_ARCH_PPC (EM_PPC)