Merge branch 'dt/irq-fix' into next/dt64

* dt/irq-fix:
  arm64: dts: Fix broken architected timer interrupt trigger

This resolves a non-obvious conflict between a bugfix from
v4.8 and a cleanup for the exynos7 platform.

diff --cc arch/arm64/boot/dts/broadcom/ns2.dtsi
Simple merge

diff --cc arch/arm64/boot/dts/exynos/exynos7.dtsi
index 8d7ce97c0ddbb67461e24f1bebacd8fb9d3acc40,162831546e183d192459fee3ae40df1b6bf2929d..6328a66ed97e42ae744d2553121e2791d3f11781
--- 1/arch/arm64/boot/dts/exynos/exynos7.dtsi
--- 2/arch/arm64/boot/dts/exynos/exynos7.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi
@@@ -474,14 -473,10 +474,14 @@@
  
                timer {
                        compatible = "arm,armv8-timer";
 -                      interrupts = <1 13 0xff08>,
 -                                   <1 14 0xff08>,
 -                                   <1 11 0xff08>,
 -                                   <1 10 0xff08>;
 +                      interrupts = <GIC_PPI 13
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
++                                      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +                                   <GIC_PPI 14
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
++                                      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +                                   <GIC_PPI 11
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>,
++                                      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 +                                   <GIC_PPI 10
-                                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_EDGE_RISING)>;
++                                      (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
                };
  
                pmu_system_controller: system-controller@105c0000 {

diff --cc arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
Simple merge

diff --cc arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
Simple merge

diff --cc arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index e70b9961115de8ba6327f1ecf09bf8530c29ce3b,c2a6745f168cbd32116f478d8c76bcc18d23104e..7b6136182ad08d0e352c9e1981a72b2a57021b3f
--- 1/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
--- 2/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@@ -122,18 -122,12 +122,18 @@@
  
                        timer {
                                compatible = "arm,armv8-timer";
-                               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-                                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-                                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
-                                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+                               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
                        };
  
 +                      pmu {
 +                              compatible = "arm,cortex-a72-pmu";
 +                              interrupt-parent = <&pic>;
 +                              interrupts = <17>;
 +                      };
 +
                        odmi: odmi@300000 {
                                compatible = "marvell,odmi-controller";
                                interrupt-controller;

diff --cc arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
Simple merge

diff --cc arch/arm64/boot/dts/xilinx/zynqmp.dtsi
Simple merge