Merge nommu branch

diff --combined arch/arm/mm/proc-arm1020.S
index efeebe77891fdc1ec24cc4dbf7aa75b51ee9146e,a1b85d9ae48eadb9b2fc249219328af1ef2df27f..6c731a4f70c9d80af519a9dae8a45473e7060642
--- 1/arch/arm/mm/proc-arm1020.S
--- 2/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@@ -440,11 -440,12 +440,12 @@@ __arm1020_setup
  #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
  #endif
+ 
+       adr     r5, arm1020_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm1020_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm1020_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
  #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .R.. .... .... ....
  #endif
@@@ -456,12 -457,9 +457,9 @@@
         * .RVI ZFRS BLDP WCAM
         * .011 1001 ..11 0101
         */
-       .type   arm1020_cr1_clear, #object
-       .type   arm1020_cr1_set, #object
- arm1020_cr1_clear:
-       .word   0x593f
- arm1020_cr1_set:
-       .word   0x3935
+       .type   arm1020_crval, #object
+ arm1020_crval:
+       crval   clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
  
        __INITDATA
  
@@@ -524,9 -522,6 +522,9 @@@ cpu_arm1020_name
  __arm1020_proc_info:
        .long   0x4104a200                      @ ARM 1020T (Architecture v5T)
        .long   0xff0ffff0
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        .long   PMD_TYPE_SECT | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ

diff --combined arch/arm/mm/proc-arm1020e.S
index 78622ac1e732fb9ec405961c7d76cbe2c9c14bd0,6130930a800aad2b249e77a881a60235f1129663..269f485d092d47a8b0e7c04d40732f8758b7259a
--- 1/arch/arm/mm/proc-arm1020e.S
--- 2/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@@ -422,11 -422,11 +422,11 @@@ __arm1020e_setup
  #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
  #endif
+       adr     r5, arm1020e_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm1020e_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm1020e_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
  #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .R.. .... .... ....
  #endif
@@@ -438,12 -438,9 +438,9 @@@
         * .RVI ZFRS BLDP WCAM
         * .011 1001 ..11 0101
         */
-       .type   arm1020e_cr1_clear, #object
-       .type   arm1020e_cr1_set, #object
- arm1020e_cr1_clear:
-       .word   0x5f3f
- arm1020e_cr1_set:
-       .word   0x3935
+       .type   arm1020e_crval, #object
+ arm1020e_crval:
+       crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
  
        __INITDATA
  
@@@ -488,10 -485,6 +485,10 @@@ cpu_arm1020e_name
  __arm1020e_proc_info:
        .long   0x4105a200                      @ ARM 1020TE (Architecture v5TE)
        .long   0xff0ffff0
 +      .long   PMD_TYPE_SECT | \
 +              PMD_BIT4 | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        .long   PMD_TYPE_SECT | \
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \

diff --combined arch/arm/mm/proc-arm1022.S
index 840dfc85ba6dd427a2a3e65509db58cb85833555,e435974062f65f102690dc763425acc59380b82c..0643bd46496936e55ad5af9ce2f006db0488d200
--- 1/arch/arm/mm/proc-arm1022.S
--- 2/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@@ -404,11 -404,11 +404,11 @@@ __arm1022_setup
  #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
  #endif
+       adr     r5, arm1022_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm1022_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm1022_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
  #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .R..............
  #endif
@@@ -421,12 -421,9 +421,9 @@@
         * .011 1001 ..11 0101
         * 
         */
-       .type   arm1022_cr1_clear, #object
-       .type   arm1022_cr1_set, #object
- arm1022_cr1_clear:
-       .word   0x7f3f
- arm1022_cr1_set:
-       .word   0x3935
+       .type   arm1022_crval, #object
+ arm1022_crval:
+       crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
  
        __INITDATA
  
@@@ -471,10 -468,6 +468,10 @@@ cpu_arm1022_name
  __arm1022_proc_info:
        .long   0x4105a220                      @ ARM 1022E (v5TE)
        .long   0xff0ffff0
 +      .long   PMD_TYPE_SECT | \
 +              PMD_BIT4 | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        .long   PMD_TYPE_SECT | \
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \

diff --combined arch/arm/mm/proc-arm1026.S
index 72b75d9c712a31804fa2fd1f5bdaacbd27b5d939,85d8fb0f25b585576bd23364332fe527a75d1b27..0668bfbac67b01e6b0b37b812bb74fecbdb63881
--- 1/arch/arm/mm/proc-arm1026.S
--- 2/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@@ -399,11 -399,11 +399,11 @@@ __arm1026_setup
        mov     r0, #4                          @ explicitly disable writeback
        mcr     p15, 7, r0, c15, c0, 0
  #endif
+       adr     r5, arm1026_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm1026_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm1026_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
  #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .R.. .... .... ....
  #endif
@@@ -416,12 -416,9 +416,9 @@@
         * .011 1001 ..11 0101
         * 
         */
-       .type   arm1026_cr1_clear, #object
-       .type   arm1026_cr1_set, #object
- arm1026_cr1_clear:
-       .word   0x7f3f
- arm1026_cr1_set:
-       .word   0x3935
+       .type   arm1026_crval, #object
+ arm1026_crval:
+       crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
  
        __INITDATA
  
@@@ -467,10 -464,6 +464,10 @@@ cpu_arm1026_name
  __arm1026_proc_info:
        .long   0x4106a260                      @ ARM 1026EJ-S (v5TEJ)
        .long   0xff0ffff0
 +      .long   PMD_TYPE_SECT | \
 +              PMD_BIT4 | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        .long   PMD_TYPE_SECT | \
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \

diff --combined arch/arm/mm/proc-arm720.S
index fb4110a9db6f123b4a3946bb0bc1d91d6b2a6f58,b22bc3af232eff17379de3017b2c612a7f7d52a7..0e6946ab6e5bbc5de65ea7a60a2b6ac68ee904f7
--- 1/arch/arm/mm/proc-arm720.S
--- 2/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@@ -169,11 -169,11 +169,11 @@@ __arm720_setup
  #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7, 0           @ flush TLB (v4)
  #endif
+       adr     r5, arm720_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register
-       ldr     r5, arm720_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm720_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
        mov     pc, lr                          @ __ret (head.S)
        .size   __arm720_setup, . - __arm720_setup
  
@@@ -183,12 -183,9 +183,9 @@@
         * ..1. 1001 ..11 1101
         * 
         */
-       .type   arm720_cr1_clear, #object
-       .type   arm720_cr1_set, #object
- arm720_cr1_clear:
-       .word   0x2f3f
- arm720_cr1_set:
-       .word   0x213d
+       .type   arm720_crval, #object
+ arm720_crval:
+       crval   clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
  
                __INITDATA
  
@@@ -246,10 -243,6 +243,10 @@@ __arm710_proc_info
                        PMD_BIT4 | \
                        PMD_SECT_AP_WRITE | \
                        PMD_SECT_AP_READ
 +              .long   PMD_TYPE_SECT | \
 +                      PMD_BIT4 | \
 +                      PMD_SECT_AP_WRITE | \
 +                      PMD_SECT_AP_READ
                b       __arm710_setup                          @ cpu_flush
                .long   cpu_arch_name                           @ arch_name
                .long   cpu_elf_name                            @ elf_name
@@@ -271,10 -264,6 +268,10 @@@ __arm720_proc_info
                        PMD_BIT4 | \
                        PMD_SECT_AP_WRITE | \
                        PMD_SECT_AP_READ
 +              .long   PMD_TYPE_SECT | \
 +                      PMD_BIT4 | \
 +                      PMD_SECT_AP_WRITE | \
 +                      PMD_SECT_AP_READ
                b       __arm720_setup                          @ cpu_flush
                .long   cpu_arch_name                           @ arch_name
                .long   cpu_elf_name                            @ elf_name

diff --combined arch/arm/mm/proc-arm920.S
index b9f1bd11bc62f51a1f40bd9d400d4e5b4a10b6b1,e647c3ae1351b1549f9e7707ac224ce1c8473093..45292f46c3b229590be0a7eb3af670e7319b79df
--- 1/arch/arm/mm/proc-arm920.S
--- 2/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@@ -391,11 -391,11 +391,11 @@@ __arm920_setup
  #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
  #endif
+       adr     r5, arm920_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm920_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm920_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
        mov     pc, lr
        .size   __arm920_setup, . - __arm920_setup
  
@@@ -405,12 -405,9 +405,9 @@@
         * ..11 0001 ..11 0101
         * 
         */
-       .type   arm920_cr1_clear, #object
-       .type   arm920_cr1_set, #object
- arm920_cr1_clear:
-       .word   0x3f3f
- arm920_cr1_set:
-       .word   0x3135
+       .type   arm920_crval, #object
+ arm920_crval:
+       crval   clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
  
        __INITDATA
  
@@@ -461,10 -458,6 +458,10 @@@ __arm920_proc_info
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_BIT4 | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __arm920_setup
        .long   cpu_arch_name
        .long   cpu_elf_name

diff --combined arch/arm/mm/proc-arm922.S
index bda0aea4ce82122c7da9f24055d292462f89f116,0d237693d0a427aebd412fc43a4005a0e25d7295..3c57519494d7368b771ae6afd9215a3fd646775d
--- 1/arch/arm/mm/proc-arm922.S
--- 2/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@@ -395,11 -395,11 +395,11 @@@ __arm922_setup
  #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
  #endif
+       adr     r5, arm922_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm922_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm922_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
        mov     pc, lr
        .size   __arm922_setup, . - __arm922_setup
  
@@@ -409,12 -409,9 +409,9 @@@
         * ..11 0001 ..11 0101
         * 
         */
-       .type   arm922_cr1_clear, #object
-       .type   arm922_cr1_set, #object
- arm922_cr1_clear:
-       .word   0x3f3f
- arm922_cr1_set:
-       .word   0x3135
+       .type   arm922_crval, #object
+ arm922_crval:
+       crval   clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
  
        __INITDATA
  
@@@ -465,10 -462,6 +462,10 @@@ __arm922_proc_info
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_BIT4 | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __arm922_setup
        .long   cpu_arch_name
        .long   cpu_elf_name

diff --combined arch/arm/mm/proc-arm925.S
index a28da8f0578fb29000d8ff1fdca039b0b5943abd,07f2a888c93c2d4fe96c4ab0101bb8f0287de986..66d5a32ba0f5419e8398de7d3a1652ca8718b8c2
--- 1/arch/arm/mm/proc-arm925.S
--- 2/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@@ -455,11 -455,10 +455,10 @@@ __arm925_setup
        mcr     p15, 7, r0, c15, c0, 0
  #endif
  
+       adr     r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm925_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm925_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
  #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .1.. .... .... ....
  #endif
@@@ -472,12 -471,9 +471,9 @@@
         * .011 0001 ..11 1101
         * 
         */
-       .type   arm925_cr1_clear, #object
-       .type   arm925_cr1_set, #object
- arm925_cr1_clear:
-       .word   0x7f3f
- arm925_cr1_set:
-       .word   0x313d
+       .type   arm925_crval, #object
+ arm925_crval:
+       crval   clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
  
        __INITDATA
  
@@@ -522,10 -518,6 +518,10 @@@ cpu_arm925_name
  __arm925_proc_info:
        .long   0x54029250
        .long   0xfffffff0
 +      .long   PMD_TYPE_SECT | \
 +              PMD_BIT4 | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        .long   PMD_TYPE_SECT | \
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \
@@@ -545,10 -537,6 +541,10 @@@
  __arm915_proc_info:
        .long   0x54029150
        .long   0xfffffff0
 +      .long   PMD_TYPE_SECT | \
 +              PMD_BIT4 | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        .long   PMD_TYPE_SECT | \
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \

diff --combined arch/arm/mm/proc-arm926.S
index 496a2335d69ea2d496441fc0812c11ae0df63ff6,77e58375778c1217be285c9b47ef51866fcf940f..189820e25184de78d9f174860fc492857f664c47
--- 1/arch/arm/mm/proc-arm926.S
--- 2/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@@ -404,11 -404,11 +404,11 @@@ __arm926_setup
        mcr     p15, 7, r0, c15, c0, 0
  #endif 
  
+       adr     r5, arm926_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm926_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm926_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
  #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .1.. .... .... ....
  #endif
@@@ -421,12 -421,9 +421,9 @@@
         * .011 0001 ..11 0101
         * 
         */
-       .type   arm926_cr1_clear, #object
-       .type   arm926_cr1_set, #object
- arm926_cr1_clear:
-       .word   0x7f3f
- arm926_cr1_set:
-       .word   0x3135
+       .type   arm926_crval, #object
+ arm926_crval:
+       crval   clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
  
        __INITDATA
  
@@@ -477,10 -474,6 +474,10 @@@ __arm926_proc_info
                PMD_BIT4 | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_BIT4 | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __arm926_setup
        .long   cpu_arch_name
        .long   cpu_elf_name

diff --combined arch/arm/mm/proc-sa110.S
index 31a09087865df8aeaf00f79a984f8a60e147fe78,eeacf601d6e89a7e0c13b6c85651457b49aeac07..e812246277cfbd31fe19b0d1361feb14568a7017
--- 1/arch/arm/mm/proc-sa110.S
--- 2/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@@ -185,11 -185,12 +185,12 @@@ __sa110_setup
  #ifdef CONFIG_MMU
        mcr     p15, 0, r10, c8, c7             @ invalidate I,D TLBs on v4
  #endif
+ 
+       adr     r5, sa110_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, sa110_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, sa110_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
        mov     pc, lr
        .size   __sa110_setup, . - __sa110_setup
  
@@@ -199,12 -200,9 +200,9 @@@
         * ..01 0001 ..11 1101
         * 
         */
-       .type   sa110_cr1_clear, #object
-       .type   sa110_cr1_set, #object
- sa110_cr1_clear:
-       .word   0x3f3f
- sa110_cr1_set:
-       .word   0x113d
+       .type   sa110_crval, #object
+ sa110_crval:
+       crval   clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
  
        __INITDATA
  
@@@ -255,9 -253,6 +253,9 @@@ __sa110_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __sa110_setup
        .long   cpu_arch_name
        .long   cpu_elf_name

diff --combined arch/arm/mm/proc-sa1100.S
index 4e2489c3e1cc6b245e6e066a9dca6cfcf8453c15,b43696c565fcc29888873f5cca47e9296b06a5fb..ba32cc6296a0d608475b573f8f3d1d85f546fc01
--- 1/arch/arm/mm/proc-sa1100.S
--- 2/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@@ -198,11 -198,11 +198,11 @@@ __sa1100_setup
  #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
  #endif
+       adr     r5, sa1100_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, sa1100_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, sa1100_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
        mov     pc, lr
        .size   __sa1100_setup, . - __sa1100_setup
  
@@@ -212,12 -212,9 +212,9 @@@
         * ..11 0001 ..11 1101
         * 
         */
-       .type   sa1100_cr1_clear, #object
-       .type   sa1100_cr1_set, #object
- sa1100_cr1_clear:
-       .word   0x3f3f
- sa1100_cr1_set:
-       .word   0x313d
+       .type   sa1100_crval, #object
+ sa1100_crval:
+       crval   clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
  
        __INITDATA
  
@@@ -276,9 -273,6 +273,9 @@@ __sa1100_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __sa1100_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -299,9 -293,6 +296,9 @@@ __sa1110_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __sa1100_setup
        .long   cpu_arch_name
        .long   cpu_elf_name

diff --combined arch/arm/mm/proc-v6.S
index ff778967a005c3281375fc282e8ea8b9011d3ed2,f0075f1b1fc1404b26faa30bce74ed68977fd49b..6f72549f8843b78043d082382a4599cbce597cde
--- 1/arch/arm/mm/proc-v6.S
--- 2/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@@ -212,11 -212,11 +212,11 @@@ __v6_setup
        orr     r0, r0, #(0xf << 20)
        mcr     p15, 0, r0, c1, c0, 2           @ Enable full access to VFP
  #endif
+       adr     r5, v6_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0, 0           @ read control register
-       ldr     r5, v6_cr1_clear                @ get mask for bits to clear
        bic     r0, r0, r5                      @ clear bits them
-       ldr     r5, v6_cr1_set                  @ get mask for bits to set
-       orr     r0, r0, r5                      @ set them
+       orr     r0, r0, r6                      @ set them
        mov     pc, lr                          @ return to head.S:__ret
  
        /*
@@@ -225,12 -225,9 +225,9 @@@
         * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
         *         0 110       0011 1.00 .111 1101 < we want
         */
-       .type   v6_cr1_clear, #object
-       .type   v6_cr1_set, #object
- v6_cr1_clear:
-       .word   0x01e0fb7f
- v6_cr1_set:
-       .word   0x00c0387d
+       .type   v6_crval, #object
+ v6_crval:
+       crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
  
        .type   v6_processor_functions, #object
  ENTRY(v6_processor_functions)
@@@ -269,10 -266,6 +266,10 @@@ __v6_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_XN | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __v6_setup
        .long   cpu_arch_name
        .long   cpu_elf_name

diff --combined arch/arm/mm/proc-xsc3.S
index 9aea506d3e65cf0609464b607d7b8b7fbf9108e2,2303790dc3ff29cd9baf4b551e0b30fc54741870..4ace2d8090c7dd83bccd8787ef7fcc2cc67a6233
--- 1/arch/arm/mm/proc-xsc3.S
--- 2/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@@ -426,23 -426,26 +426,26 @@@ __xsc3_setup
        orr     r0, r0, #(1 << 10)              @ enable L2 for LLR cache
  #endif
        mcr     p15, 0, r0, c1, c0, 1           @ set auxiliary control reg
+ 
+       adr     r5, xsc3_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0, 0           @ get control register
-       bic     r0, r0, #0x0002                 @ .... .... .... ..A.
-       orr     r0, r0, #0x0005                 @ .... .... .... .C.M
+       bic     r0, r0, r5                      @ .... .... .... ..A.
+       orr     r0, r0, r6                      @ .... .... .... .C.M
  #if BTB_ENABLE
-       bic     r0, r0, #0x0200                 @ .... ..R. .... ....
-       orr     r0, r0, #0x3900                 @ ..VI Z..S .... ....
- #else
-       bic     r0, r0, #0x0a00                 @ .... Z.R. .... ....
-       orr     r0, r0, #0x3100                 @ ..VI ...S .... ....
+       orr     r0, r0, #0x00000800             @ ..VI Z..S .... ....
  #endif
  #if L2_CACHE_ENABLE
-       orr     r0, r0, #0x4000000              @ L2 enable
+       orr     r0, r0, #0x04000000             @ L2 enable
  #endif
        mov     pc, lr
  
        .size   __xsc3_setup, . - __xsc3_setup
  
+       .type   xsc3_crval, #object
+ xsc3_crval:
+       crval   clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
+ 
        __INITDATA
  
  /*
@@@ -487,14 -490,7 +490,14 @@@ cpu_xsc3_name
  __xsc3_proc_info:
        .long   0x69056000
        .long   0xffffe000
 -      .long   0x00000c0e
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_BUFFERABLE | \
 +              PMD_SECT_CACHEABLE | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xsc3_setup
        .long   cpu_arch_name
        .long   cpu_elf_name

diff --combined arch/arm/mm/proc-xscale.S
index f4aeb7b069113289dbd0cee10f14f57f529b13ed,1ad0c880c80c2d1cd268087e338553be132cf952..535395e25a8a5b90de9f2e61277ef8ade7632446
--- 1/arch/arm/mm/proc-xscale.S
--- 2/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@@ -475,11 -475,12 +475,12 @@@ __xscale_setup
        orr     r0, r0, #1 << 6                 @ cp6 for IOP3xx and Bulverde
        orr     r0, r0, #1 << 13                @ Its undefined whether this
        mcr     p15, 0, r0, c15, c1, 0          @ affects USR or SVC modes
+ 
+       adr     r5, xscale_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0, 0           @ get control register
-       ldr     r5, xscale_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, xscale_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
        mov     pc, lr
        .size   __xscale_setup, . - __xscale_setup
  
@@@ -489,12 -490,9 +490,9 @@@
         * ..11 1.01 .... .101
         * 
         */
-       .type   xscale_cr1_clear, #object
-       .type   xscale_cr1_set, #object
- xscale_cr1_clear:
-       .word   0x3b07
- xscale_cr1_set:
-       .word   0x3905
+       .type   xscale_crval, #object
+ xscale_crval:
+       crval   clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
  
        __INITDATA
  
@@@ -595,9 -593,6 +593,9 @@@ __80200_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -618,9 -613,6 +616,9 @@@ __8032x_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -641,9 -633,6 +639,9 @@@ __8033x_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -664,9 -653,6 +662,9 @@@ __pxa250_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -687,9 -673,6 +685,9 @@@ __pxa210_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -710,9 -693,6 +708,9 @@@ __ixp2400_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -733,9 -713,6 +731,9 @@@ __ixp2800_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -756,9 -733,6 +754,9 @@@ __ixp42x_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -774,14 -748,7 +772,14 @@@
  __ixp46x_proc_info:
        .long   0x69054200
        .long   0xffffff00
 -      .long   0x00000c0e
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_BUFFERABLE | \
 +              PMD_SECT_CACHEABLE | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -802,9 -769,6 +800,9 @@@ __pxa255_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
@@@ -825,9 -789,6 +823,9 @@@ __pxa270_proc_info
                PMD_SECT_CACHEABLE | \
                PMD_SECT_AP_WRITE | \
                PMD_SECT_AP_READ
 +      .long   PMD_TYPE_SECT | \
 +              PMD_SECT_AP_WRITE | \
 +              PMD_SECT_AP_READ
        b       __xscale_setup
        .long   cpu_arch_name
        .long   cpu_elf_name