Required properties:
- reg: Physical base address and size of the controller's register area.
- compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
- chip could be ls1021a, ls2085a, ls1043a etc.
+ chip could be ls1021a, ls2080a, ls1043a etc.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt binding.
Optional properties:
- - dma-coherent: Enable ACHI coherency DMA operation.
- - reg-names: register area names when there are more then 1 regster area.
+ - dma-coherent: Enable AHCI coherent DMA operation.
+ - reg-names: register area names when there are more than 1 register area.
Examples:
sata@3200000 {
enum ahci_qoriq_type {
AHCI_LS1021A,
AHCI_LS1043A,
- AHCI_LS2085A,
+ AHCI_LS2080A,
};
struct ahci_qoriq_priv {
static const struct of_device_id ahci_qoriq_of_match[] = {
{ .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
- { .compatible = "fsl,ls2085a-ahci", .data = (void *)AHCI_LS2085A},
+ { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
.hardreset = ahci_qoriq_hardreset,
};
-static const struct ata_port_info ahci_qoriq_port_info = {
+static struct ata_port_info ahci_qoriq_port_info = {
.flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
.pio_mask = ATA_PIO4,
.udma_mask = ATA_UDMA6,
break;
case AHCI_LS1043A:
- case AHCI_LS2085A:
+ case AHCI_LS2080A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
break;
}
if (rc)
goto disable_resources;
+ /* Workaround for ls2080a */
+ if (qoriq_priv->type == AHCI_LS2080A) {
+ hpriv->flags |= AHCI_HFLAG_NO_NCQ;
+ ahci_qoriq_port_info.flags &= ~ATA_FLAG_NCQ;
+ }
+
rc = ahci_platform_init_host(pdev, hpriv, &ahci_qoriq_port_info,
&ahci_qoriq_sht);
if (rc)