powerpc/64: Hard code cache geometry on POWER8

All shipping firmware versions have it wrong in the device-tree

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index db18f7b68a1d59b2f01ed64eb626df6a78cfbae1..364fbffd7e834d4d01b78764f9219fe8a2c4fca0 100644 (file)
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -472,11 +472,27 @@ static bool __init parse_cache_info(struct device_node *np,
 
 void __init initialize_cache_info(void)
 {
-       struct device_node *cpu, *l2, *l3 = NULL;
+       struct device_node *cpu = NULL, *l2, *l3 = NULL;
+       u32 pvr;
 
        DBG(" -> initialize_cache_info()\n");
 
-       cpu = of_find_node_by_type(NULL, "cpu");
+       /*
+        * All shipping POWER8 machines have a firmware bug that
+        * puts incorrect information in the device-tree. This will
+        * be (hopefully) fixed for future chips but for now hard
+        * code the values if we are running on one of these
+        */
+       pvr = PVR_VER(mfspr(SPRN_PVR));
+       if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
+           pvr == PVR_POWER8NVL) {
+                                               /* size    lsize   blk  sets */
+               init_cache_info(&ppc64_caches.l1i, 0x8000,   128,  128, 32);
+               init_cache_info(&ppc64_caches.l1d, 0x10000,  128,  128, 64);
+               init_cache_info(&ppc64_caches.l2,  0x80000,  128,  0,   512);
+               init_cache_info(&ppc64_caches.l3,  0x800000, 128,  0,   8192);
+       } else
+               cpu = of_find_node_by_type(NULL, "cpu");
 
        /*
         * We're assuming *all* of the CPUs have the same