i7core_edac: Fix ecc enable shift

From: Keith Mannthey <kmannth@us.ibm.com>

Simple correction to a shift value.
ECC_ENABLED is bit 4 of MC_STATUS, Dev 3 Fun 0 Offset 0x4c

This correctly identifies the state of the ECC at the machine.

Signed-off-by: Keith Mannthey <kmannth@us.ibm.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

diff --git a/drivers/edac/i7core_edac.c b/drivers/edac/i7core_edac.c
index 26205e2efecfd9fb3daabc90126def7c923d54f4..87d5695f5fb06d9cb23ef13cf8d684247ce8ef68 100644 (file)
--- a/drivers/edac/i7core_edac.c
+++ b/drivers/edac/i7core_edac.c
@@ -286,7 +286,7 @@ static struct edac_pci_ctl_info *i7core_pci;
 #define ECCx8(pvt)             ((pvt)->info.mc_control & (1 << 1))
 
        /* MC_STATUS bits */
-#define ECC_ENABLED(pvt)       ((pvt)->info.mc_status & (1 << 3))
+#define ECC_ENABLED(pvt)       ((pvt)->info.mc_status & (1 << 4))
 #define CH_DISABLED(pvt, ch)   ((pvt)->info.mc_status & (1 << ch))
 
        /* MC_MAX_DOD read functions */