+++ /dev/null
-#
-# Parts of the development effort for this project have been
-# sponsored by SIEMENS AG, Austria. Thanks to SIEMENS for
-# supporting an Open Source project!
-#
-#
-# This is at least a partial credits-file of individual people that
-# have contributed to the U-Boot project. It is sorted by name and
-# formatted to allow easy grepping and beautification by scripts.
-# The fields are: name (N), email (E), web-address (W), PGP key ID
-# and fingerprint (P), description (D), and snail-mail address (S).
-# Thanks,
-#
-# Wolfgang Denk
-#----------
-
-N: Dr. Bruno Achauer
-E: bruno@exet-ag.de
-D: Support for NetBSD (both as host and target system)
-
-N: Guillaume Alexandre
-E: guillaume.alexandre@gespac.ch
-D: Add PCIPPC6 configuration
-
-N: Pantelis Antoniou
-E: panto@intracom.gr
-D: NETVIA & NETPHONE board support, ARTOS support.
-D: Support for Silicon Turnkey eXpress XTc
-
-N: Pierre Aubert
-E: <p.aubert@staubli.com>
-D: Support for RPXClassic board
-
-N: Yuli Barcohen
-E: yuli@arabellasw.com
-D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
-D: Support for Zephyr Engineering ZPC.1900 board.
-D: Support for Interphase iSPAN boards.
-D: Support for Analogue&Micro Adder boards.
-D: Support for Analogue&Micro Rattler boards.
-W: http://www.arabellasw.com
-
-N: Jerry van Baren
-E: <vanbaren@cideas.com>
-D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test.
-
-N: Pavel Bartusek
-E: <pba@sysgo.com>
-D: Reiserfs support
-W: http://www.elinos.com
-
-N: Andre Beaudin
-E: <andre.beaudin@colubris.com>
-D: PCMCIA, Ethernet, TFTP
-
-N: Jon Benediktsson
-E: jonb@marel.is
-D: Support for Marel V37 board
-
-N: Raphael Bossek
-E: raphael.bossek@solutions4linux.de
-D: 8xxrom-0.3.0
-
-N: Cliff Brake
-E: cliff.brake@gmail.com
-D: Port to Vibren PXA255 IDP platform
-W: http://www.vibren.com
-W: http://bec-systems.com
-
-N: Rick Bronson
-E: rick@efn.org
-D: Atmel AT91RM9200DK and NAND support
-
-N: David Brown
-E: DBrown03@harris.com
-D: Extensions to 8xxrom-0.3.0
-
-N: Oliver Brown
-E: obrown@adventnetworks.com
-D: Port to the gw8260 board
-
-N: Jonathan De Bruyne
-E: jonathan.debruyne@siemens.atea.be
-D: Port to Siemens IAD210 board
-
-N: Ken Chou
-E: kchou@ieee.org
-D: Support for A3000 SBC board
-
-N: Conn Clark
-E: clark@esteem.com
-D: ESTEEM192E support
-
-N: Magnus Damm
-E: damm@opensource.se
-D: 8xxrom
-
-N: Richard Danter
-E: richard.danter@windriver.com
-D: Support for Wind River PPMC 7xx/74xx boards
-
-N: George G. Davis
-E: gdavis@mvista.com
-D: Board ports for ADS GraphicsClient+ and Intel Assabet
-
-N: Arun Dharankar
-E: ADharankar@ATTBI.Com
-D: threads / scheduler example code
-
-N: K?ri Dav??sson
-E: kd@flaga.is
-D: FLAGA DM Support
-
-N: Wolfgang Denk
-E: wd@denx.de
-D: U-Boot initial version, continuing maintenance, ARMBoot merge
-W: http://www.denx.de
-
-N: Dan A. Dickey
-E: ddickey@charter.net
-D: FADS Support
-
-N: Mike Dunn
-E: mikedunn@newsguy.com
-D: Palmtreo680 board, docg4 nand flash driver
-
-N: Dave Ellis
-E: DGE@sixnetio.com
-D: EEPROM Speedup
-
-N: Daniel Engstr?m
-E: daniel@omicron.se
-D: x86 port, Support for sc520_cdp board
-
-N: Hayden Fraser
-E: Hayden.Fraser@freescale.com
-D: Support for ColdFire MCF5253
-W: www.freescale.com
-
-N: Dr. Wolfgang Grandegger
-E: wg@denx.de
-D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards
-W: www.denx.de
-
-N: Peter Figuli
-E: peposh@etc.sk
-D: Support for WEP EP250 (PXA) board
-
-N: Thomas Frieden
-E: ThomasF@hyperion-entertainment.com
-D: Support for AmigaOne
-
-N: Paul Gortmaker
-E: paul.gortmaker@windriver.com
-D: Support for WRS SBC8347/8349 boards
-
-N: Frank Gottschling
-E: fgottschling@eltec.de
-D: Support for ELTEC MHPC/ELPPC boards, cfb-console, i8042, SMI LynxEM
-W: www.eltec.de
-
-N: Marius Groeger
-E: mgroeger@sysgo.de
-D: MBX Support, board specific function interface, EST SBC8260 support; initial support for StrongARM (LART), ARM720TDMI (implementa A7)
-W: www.elinos.com
-
-N: Kirk Haderlie
-E: khaderlie@vividimage.com
-D: Added TFTP to 8xxrom (-> 0.3.1)
-
-N: Chris Hallinan
-E: clh@net1plus.com
-D: DHCP Support
-
-N: Anne-Sophie Harnois
-E: Anne-Sophie.Harnois@nextream.fr
-D: Port to Walnut405 board
-
-N: Andreas Heppel
-E: aheppel@sysgo.de
-D: CPU Support for MPC 75x
-
-N: Josh Huber
-E: huber@alum.wpi.edu
-D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series.
-W: http://www.mclx.com/
-
-H: Stuart Hughes
-E: stuarth@lineo.com
-D: Port to MPC8260ADS board
-
-H: Rich Ireland
-E: r.ireland@computer.org
-D: FPGA device configuration driver
-
-H: Mark Jackson
-E: mpfj@mimc.co.uk
-D: Port to MIMC200 board
-
-N: Gary Jennejohn
-E: garyj@jennejohn.org
-D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
-W: www.denx.de
-
-N: Murray Jensen
-E: Murray.Jensen@csiro.au
-D: Initial 8260 support; GDB support
-D: Port to Cogent+Hymod boards; Hymod Board Database
-
-N: Yoo. Jonghoon
-E: yooth@ipone.co.kr
-D: Added port to the RPXlite board
-
-N: Mark Jonas
-E: mark.jonas@freescale.com
-D: Support for Freescale Total5200 platform
-W: http://www.mobilegt.com/
-
-N: Mark Jonas
-E: mark.jonas@de.bosch.com
-D: Support for MPR2 board
-
-N: Sam Song
-E: samsongshu@yahoo.com.cn
-D: Port to the RPXlite_DW board
-
-N: Brad Kemp
-E: Brad.Kemp@seranoa.com
-D: Port to Windriver ppmc8260 board
-
-N: Sangmoon Kim
-E: dogoil@etinsys.com
-D: Support for debris board
-D: Support for KVME080 board
-
-N: Frederick W. Klatt
-E: fred.klatt@windriver.com
-D: Support for Wind River SBC8540/SBC8560 boards
-
-N: Thomas Koeller
-E: tkoeller@gmx.net
-D: Port to Motorola Sandpoint 3 (MPC8240)
-
-N: Raghu Krishnaprasad
-E: Raghu.Krishnaprasad@fci.com
-D: Support for Adder-II MPC852T evaluation board
-W: http://www.forcecomputers.com
-
-N: Sergey Kubushyn
-E: ksi@koi8.net
-D: Support for various TI DaVinci based boards.
-
-N: Bernhard Kuhn
-E: bkuhn@metrowerks.com
-D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
-
-N: Prakash Kumar
-E: prakash@embedx.com
-D Support for Intrinsyc CERF PXA250 board.
-
-N: Thomas Lange
-E: thomas@corelatus.se
-D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
-
-N: The LEOX team
-E: team@leox.org
-D: Support for LEOX boards, DS164x RTC
-W: http://www.leox.org
-
-N: TsiChung Liew
-E: Tsi-Chung.Liew@freescale.com
-D: Support for ColdFire MCF523x, MCF532x, MCF5445x, MCF547x_8x
-W: www.freescale.com
-
-N: Leif Lindholm
-E: leif.lindholm@i3micro.com
-D: Support for AMD dbau1550 board.
-
-N: Stephan Linz
-E: linz@li-pro.net
-D: Support for Nios Stratix Development Kit (DK-1S10)
-D: Support for SSV ADNP/ESC1 (Nios Cyclone)
-W: http://www.li-pro.net
-
-N: Dave Liu
-E: daveliu@freescale.com
-D: Support for MPC8315, MPC832x, MPC8360, MPC837x
-W: www.freescale.com
-
-N: Raymond Lo
-E: lo@routefree.com
-D: Support for DOS partitions
-
-N: James MacAulay
-E: james.macaulay@amirix.com
-D: Suppport for Amirix AP1000
-W: www.amirix.com
-
-N: Dan Malek
-E: dan@embeddedalley.com
-D: FADSROM, the grandfather of all of this
-D: Support for Silicon Turnkey eXpress XTc
-
-N: Andrea "llandre" Marson
-E: andrea.marson@dave-tech.it
-D: Port to PPChameleonEVB board
-W: www.dave-tech.it
-
-N: Reinhard Meyer
-E: r.meyer@emk-elektronik.de
-D: Port to EMK TOP860 Module
-
-N: Jay Monkman
-E: jtm@smoothsmoothie.com
-D: EST SBC8260 support
-
-N: Frank Morauf
-E: frank.morauf@salzbrenner.com
-D: Support for Embedded Planet RPX Super Board
-
-N: David M?ller
-E: d.mueller@elsoft.ch
-D: Support for Samsung ARM920T SMDK2410 eval board
-
-N: Scott McNutt
-E: smcnutt@psyent.com
-D: Support for Altera Nios-32 CPU
-D: Support for Altera Nios-II CPU
-D: Support for Nios Cyclone Development Kit (DK-1C20)
-W: http://www.psyent.com
-
-N: Rolf Offermanns
-E: rof@sysgo.de
-D: Initial support for SSV-DNP1110, SMC91111 driver
-W: www.elinos.com
-
-N: John Otken
-E: jotken@softadvances.com
-D: Support for AMCC Luan 440SP board
-
-N: Tolunay Orkun
-E: torkun@nextio.com
-D: Support for Cogent CSB272 & CSB472 boards
-
-N: Keith Outwater
-E: keith_outwater@mvis.com
-D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC)
-
-N: Frank Panno
-E: fpanno@delphintech.com
-D: Support for Embedded Planet EP8260 Board
-
-N: Denis Peter
-E: d.peter@mpl.ch
-D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ...
-D: Support for PIP405 board
-D: Support for MIP405 board
-
-N: Dave Peverley
-E: dpeverley@mpc-data.co.uk
-W: http://www.mpc-data.co.uk
-D: OMAP730 P2 board support
-
-N: Bill Pitts
-E: wlp@mindspring.com
-D: BedBug embedded debugger code
-
-N: Daniel Poirot
-E: dan.poirot@windriver.com
-D: Support for the Wind River sbc405, sbc8240 board
-W: http://www.windriver.com
-
-N: Stelian Pop
-E: stelian@popies.net
-D: Atmel AT91CAP9ADK support
-
-N: Ricardo Ribalda Delgado
-E: ricardo.ribalda@uam.es
-D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval
-D: Virtex ppc440 generic architecture
-D: Virtex ppc405 generic architecture
-W: http://www.ii.uam.es/~rribalda
-
-N: Stefan Roese
-E: sr@denx.de
-D: AMCC PPC4xx Support
-W: http://www.denx.de
-
-N: Erwin Rol
-E: erwin@muffin.org
-D: boot support for RTEMS
-
-N: Paul Ruhland
-E: pruhland@rochester.rr.com
-D: Port to Logic Zoom LH7A40x SDK board(s)
-
-N: Neil Russell
-E: caret@c-side.com
-D: Author of LiMon-1.4.2, which contributed some ideas
-
-N: Travis B. Sawyer
-E: travis.sawyer@sandburst.com
-D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea)
-
-N: Paolo Scaffardi
-E: arsenio@tin.it
-D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more
-
-N: Andre Schwarz
-E: andre.schwarz@matrix-vision.de
-D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR)
-
-N: Robert Schwebel
-E: r.schwebel@pengutronix.de
-D: Support for csb226 and innokom boards (PXA2xx)
-
-N: Aaron Sells
-E: sellsa@embeddedplanet.com
-D: Support for EP82xxM
-
-N: Art Shipkowski
-E: art@videon-central.com
-D: Support for NetSilicon NS7520
-D: Support for ColdFire MCF5275
-
-N: Jeremy C. Andrus
-E: jeremy@jeremya.com
-D: ColdFire MCF5249 initialization code
-W: jeremya.com
-
-N: Michal Simek
-E: monstr@monstr.eu
-D: Support for Microblaze, ML401, XUPV2P board
-W: www.monstr.eu
-
-N: Yasushi Shoji
-E: yashi@atmark-techno.com
-D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
-
-N: Kurt Stremerch
-E: kurt@exys.be
-D: Support for Exys XSEngine board
-
-N: Andrea Scian
-E: andrea.scian@dave-tech.it
-D: Port to B2 board
-W: www.dave-tech.it
-
-N: Timur Tabi
-E: timur@freescale.com
-D: Support for MPC8349E-mITX
-W: www.freescale.com
-
-N: Rob Taylor
-E: robt@flyingpig.com
-D: Port to MBX860T and Sandpoint8240
-
-N: Erik Theisen
-E: etheisen@mindspring.com
-D: MBX8xx and many other patches
-
-N: Jim Thompson
-E: jim@musenki.com
-D: Support for MUSENKI board
-
-N: Rune Torgersen
-E: <runet@innovsys.com>
-D: Support for Motorola MPC8266ADS board
-
-N: Greg Ungerer
-E: greg.ungerer@opengear.com
-D: Support for ks8695 CPU, and OpenGear cmXXXX boards
-
-N: David Updegraff
-E: dave@cray.com
-D: Port to Cray L1 board; DHCP vendor extensions
-
-N: Christian Vejlbo
-E: christian.vejlbo@tellabs.com
-D: FADS860T ethernet support
-
-N: Robert Whaley
-E: rwhaley@applieddata.net
-D: Port to ARM PXA27x adsvix SBC
-
-N: Martin Winistoerfer
-E: martinwinistoerfer@gmx.ch
-D: Port to MPC555/556 microcontrollers and support for cmi board
-
-N: David Wu
-E: support@arcturusnetworks.com
-D: Mercury Security EP2500
-W: http://www.arcturusnetworks.com
-
-N: Ming-Len Wu
-E: minglen_wu@techware.com.tw
-D: Motorola MX1ADS board support
-W: http://www.techware.com.tw/
-
-N: Xianghua Xiao
-E: x.xiao@motorola.com
-D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
-
-N: John Zhan
-E: zhanz@sinovee.com
-D: Support for SinoVee Microsystems SC8xx SBC
-
-N: Alex Zuepke
-E: azu@sysgo.de
-D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
-W: www.elinos.com
-
-N: Nobuhiro Iwamatsu
-E: iwamatsu@nigauri.org
-D: Support for SuperH, MS7750SE01 and MS7722SE01 boards.
-W: http://www.nigauri.org/~iwamatsu/
-
-N: Alan Lu
-E: alnalu001@gmail.com
-D: Support for Artila M-501 starter kit
-W: http://www.artila.com/
-
-N: Kimmo Leppala
-E: kimmo.leppala@sysart.fi
-D: Support for Artila M-501 starter kit
-W: http://www.sysart.fi/
-
-N: Timo Tuunainen
-E: timo.tuunainen@sysart.fi
-D: Support for Artila M-501 starter kit
-W: http://www.sysart.fi/
-
-N: Philip Balister
-E: philip@opensdr.com
-D: Port to Lyrtech SFFSDR development board.
-W: www.opensdr.com
configuration to Kconfig. Since this option will be removed sometime,
new boards should not use this option.
+config SYS_TEXT_BASE
+ depends on SPARC
+ hex "Text Base"
+ help
+ TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture
+
endmenu # Boot images
source "arch/Kconfig"
M: Stefan Roese <sr@denx.de>
S: Maintained
T: git git://git.denx.de/u-boot-cfi-flash.git
-F: drivers/mtd/*
+F: drivers/mtd/cfi_flash.c
+F: drivers/mtd/jedec_flash.c
COLDFIRE
M: Jason Jin <jason.jin@freescale.com>
F: arch/mips/
MMC
-M: Pantelis Antoniou <panto.antoniou-consulting.com>
+M: Pantelis Antoniou <panto@antoniou-consulting.com>
S: Maintained
T: git git://git.denx.de/u-boot-mmc.git
F: drivers/mmc/
-#
-# (C) Copyright 2000-2013
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-VERSION = 2014
-PATCHLEVEL = 10
+VERSION = 2015
+PATCHLEVEL = 01
SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = -rc1
NAME =
# *DOCUMENTATION*
# Comments in this file are targeted only to the developer, do not
# expect to learn how to build the kernel reading this file.
-# Do not:
-# o use make's built-in rules and variables
-# (this increases performance and avoids hard-to-debug behaviour);
-# o print "Entering directory ...";
-MAKEFLAGS += -rR --no-print-directory
+# Do not use make's built-in rules and variables
+# (this increases performance and avoids hard-to-debug behaviour);
+MAKEFLAGS += -rR
# Avoid funny character set dependencies
unexport LC_ALL
LC_NUMERIC=C
export LC_COLLATE LC_NUMERIC
+# Avoid interference with shell env settings
+unexport GREP_OPTIONS
+
# We are using a recursive build, so we need to do a little thinking
# to get the ordering right.
#
# descending is started. They are now explicitly listed as the
# prepare rule.
+# Beautify output
+# ---------------------------------------------------------------------------
+#
+# Normally, we echo the whole command before executing it. By making
+# that echo $($(quiet)$(cmd)), we now have the possibility to set
+# $(quiet) to choose other forms of output instead, e.g.
+#
+# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@
+# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
+#
+# If $(quiet) is empty, the whole command will be printed.
+# If it is set to "quiet_", only the short version will be printed.
+# If it is set to "silent_", nothing will be printed at all, since
+# the variable $(silent_cmd_cc_o_c) doesn't exist.
+#
+# A simple variant is to prefix commands with $(Q) - that's useful
+# for commands that shall be hidden in non-verbose mode.
+#
+# $(Q)ln $@ :<
+#
+# If KBUILD_VERBOSE equals 0 then the above command will be hidden.
+# If KBUILD_VERBOSE equals 1 then the above command is displayed.
+#
# To put more focus on warnings, be less verbose as default
# Use 'make V=1' to see the full commands
KBUILD_VERBOSE = 0
endif
-# Call a source code checker (by default, "sparse") as part of the
-# C compilation.
-#
-# Use 'make C=1' to enable checking of only re-compiled files.
-# Use 'make C=2' to enable checking of *all* source files, regardless
-# of whether they are re-compiled or not.
-#
-# See the file "Documentation/sparse.txt" for more details, including
-# where to get the "sparse" utility.
+ifeq ($(KBUILD_VERBOSE),1)
+ quiet =
+ Q =
+else
+ quiet=quiet_
+ Q = @
+endif
-ifeq ("$(origin C)", "command line")
- KBUILD_CHECKSRC = $(C)
+# If the user is running make -s (silent mode), suppress echoing of
+# commands
+
+ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
+ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
+ quiet=silent_
endif
-ifndef KBUILD_CHECKSRC
- KBUILD_CHECKSRC = 0
+else # make-3.8x
+ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
+ quiet=silent_
endif
-
-# Use make M=dir to specify directory of external module to build
-# Old syntax make ... SUBDIRS=$PWD is still supported
-# Setting the environment variable KBUILD_EXTMOD take precedence
-ifdef SUBDIRS
- KBUILD_EXTMOD ?= $(SUBDIRS)
endif
-ifeq ("$(origin M)", "command line")
- KBUILD_EXTMOD := $(M)
-endif
+export quiet Q KBUILD_VERBOSE
# kbuild supports saving output files in a separate directory.
# To locate output files in a separate directory two syntaxes are supported.
# The O= assignment takes precedence over the KBUILD_OUTPUT environment
# variable.
-
# KBUILD_SRC is set on invocation of make in OBJ directory
# KBUILD_SRC is not intended to be used by the regular user (for now)
ifeq ($(KBUILD_SRC),)
@:
sub-make: FORCE
- $(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \
- KBUILD_SRC=$(CURDIR) \
- KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \
- $(filter-out _all sub-make,$(MAKECMDGOALS))
+ $(Q)$(MAKE) -C $(KBUILD_OUTPUT) KBUILD_SRC=$(CURDIR) \
+ -f $(CURDIR)/Makefile $(filter-out _all sub-make,$(MAKECMDGOALS))
# Leave processing to above invocation of make
skip-makefile := 1
# We process the rest of the Makefile if this is the final invocation of make
ifeq ($(skip-makefile),)
+# Do not print "Entering directory ...",
+# but we want to display it when entering to the output directory
+# so that IDEs/editors are able to understand relative filenames.
+MAKEFLAGS += --no-print-directory
+
+# Call a source code checker (by default, "sparse") as part of the
+# C compilation.
+#
+# Use 'make C=1' to enable checking of only re-compiled files.
+# Use 'make C=2' to enable checking of *all* source files, regardless
+# of whether they are re-compiled or not.
+#
+# See the file "Documentation/sparse.txt" for more details, including
+# where to get the "sparse" utility.
+
+ifeq ("$(origin C)", "command line")
+ KBUILD_CHECKSRC = $(C)
+endif
+ifndef KBUILD_CHECKSRC
+ KBUILD_CHECKSRC = 0
+endif
+
+# Use make M=dir to specify directory of external module to build
+# Old syntax make ... SUBDIRS=$PWD is still supported
+# Setting the environment variable KBUILD_EXTMOD take precedence
+ifdef SUBDIRS
+ KBUILD_EXTMOD ?= $(SUBDIRS)
+endif
+
+ifeq ("$(origin M)", "command line")
+ KBUILD_EXTMOD := $(M)
+endif
+
# If building an external module we do not care about the all: rule
# but instead _all depend on modules
PHONY += all
_all: modules
endif
-srctree := $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR))
-objtree := $(CURDIR)
+ifeq ($(KBUILD_SRC),)
+ # building in the source tree
+ srctree := .
+else
+ ifeq ($(KBUILD_SRC)/,$(dir $(CURDIR)))
+ # building in a subdirectory of the source tree
+ srctree := ..
+ else
+ srctree := $(KBUILD_SRC)
+ endif
+endif
+objtree := .
src := $(srctree)
obj := $(objtree)
export KBUILD_MODULES KBUILD_BUILTIN
export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
-# Beautify output
-# ---------------------------------------------------------------------------
-#
-# Normally, we echo the whole command before executing it. By making
-# that echo $($(quiet)$(cmd)), we now have the possibility to set
-# $(quiet) to choose other forms of output instead, e.g.
-#
-# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@
-# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
-#
-# If $(quiet) is empty, the whole command will be printed.
-# If it is set to "quiet_", only the short version will be printed.
-# If it is set to "silent_", nothing will be printed at all, since
-# the variable $(silent_cmd_cc_o_c) doesn't exist.
-#
-# A simple variant is to prefix commands with $(Q) - that's useful
-# for commands that shall be hidden in non-verbose mode.
-#
-# $(Q)ln $@ :<
-#
-# If KBUILD_VERBOSE equals 0 then the above command will be hidden.
-# If KBUILD_VERBOSE equals 1 then the above command is displayed.
-
-ifeq ($(KBUILD_VERBOSE),1)
- quiet =
- Q =
-else
- quiet=quiet_
- Q = @
-endif
-
-# If the user is running make -s (silent mode), suppress echoing of
-# commands
-
-ifneq ($(filter 4.%,$(MAKE_VERSION)),) # make-4
-ifneq ($(filter %s ,$(firstword x$(MAKEFLAGS))),)
- quiet=silent_
-endif
-else # make-3.8x
-ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
- quiet=silent_
-endif
-endif
-
-export quiet Q KBUILD_VERBOSE
-
# Look for make include files relative to root of kernel src
MAKEFLAGS += --include-dir=$(srctree)
cmd_pad_cat = $(cmd_objcopy) && $(append) || rm -f $@
all: $(ALL-y)
+ifneq ($(CONFIG_SYS_GENERIC_BOARD),y)
+ @echo "===================== WARNING ======================"
+ @echo "Please convert this board to generic board."
+ @echo "Otherwise it will be removed by the end of 2014."
+ @echo "See doc/README.generic-board for further information"
+ @echo "===================================================="
+endif
PHONY += dtbs
dtbs dts/dt.dtb: checkdtc u-boot
u-boot.ldr: u-boot
$(CREATE_LDR_ENV)
- $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
+ $(LDR) -T $(CONFIG_CPU) -c $@ $< $(LDR_FLAGS)
$(BOARD_SIZE_CHECK)
OBJCOPYFLAGS_u-boot.ldr.hex := -I binary -O ihex
ifneq ($(CONFIG_SUNXI),)
OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
--pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin \
+ u-boot$(if $(CONFIG_OF_CONTROL),-dtb,).img FORCE
$(call if_changed,pad_cat)
endif
# make distclean Remove editor backup files, patch leftover files and the like
# Directories & files removed with 'make clean'
-CLEAN_DIRS += $(MODVERDIR)
-CLEAN_FILES += u-boot.lds include/bmp_logo.h include/bmp_logo_data.h
-
-# Directories & files removed with 'make clobber'
-CLOBBER_DIRS += $(foreach d, spl tpl, $(patsubst %,$d/%, \
+CLEAN_DIRS += $(MODVERDIR) \
+ $(foreach d, spl tpl, $(patsubst %,$d/%, \
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
-CLOBBER_FILES += u-boot* MLO* SPL System.map
+
+CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
+ u-boot* MLO* SPL System.map
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name '*.gcno' \) -type f -print | xargs rm -f
-# clobber
-#
-clobber: rm-dirs := $(CLOBBER_DIRS)
-clobber: rm-files := $(CLOBBER_FILES)
-
-PHONY += clobber
-
-clobber: clean
- $(call cmd,rmdirs)
- $(call cmd,rmfiles)
-
# mrproper - Delete all generated files, including .config
#
mrproper: rm-dirs := $(wildcard $(MRPROPER_DIRS))
$(mrproper-dirs):
$(Q)$(MAKE) $(clean)=$(patsubst _mrproper_%,%,$@)
-mrproper: clobber $(mrproper-dirs)
+mrproper: clean $(mrproper-dirs)
$(call cmd,rmdirs)
$(call cmd,rmfiles)
@rm -f arch/*/include/asm/arch
help:
@echo 'Cleaning targets:'
- @echo ' clean - Remove most generated files but keep the config and'
- @echo ' necessities for testing u-boot'
- @echo ' clobber - Remove most generated files but keep the config'
+ @echo ' clean - Remove most generated files but keep the config'
@echo ' mrproper - Remove all generated files + config + various backup files'
@echo ' distclean - mrproper + remove editor backup and patch files'
@echo ''
@echo ''
@echo 'Other generic targets:'
@echo ' all - Build all necessary images depending on configuration'
- @echo ' u-boot - Build the bare u-boot'
+ @echo '* u-boot - Build the bare u-boot'
@echo ' dir/ - Build all files in dir and below'
@echo ' dir/file.[oisS] - Build specified target only'
@echo ' dir/file.lst - Build specified mixed source/assembly target only'
@echo ' tags/ctags - Generate ctags file for editors'
@echo ' etags - Generate etags file for editors'
@echo ' cscope - Generate cscope index'
- @echo ' ubootrelease - Output the release version string'
- @echo ' ubootversion - Output the version stored in Makefile'
+ @echo ' ubootrelease - Output the release version string (use with make -s)'
+ @echo ' ubootversion - Output the version stored in Makefile (use with make -s)'
@echo ''
@echo 'Static analysers'
@echo ' checkstack - Generate a list of stack hogs'
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.clean obj=dir
# Usage:
# $(Q)$(MAKE) $(clean)=dir
-clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj
+clean := -f $(srctree)/scripts/Makefile.clean obj
endif # skip-makefile
make O=/tmp/build NAME_defconfig
make O=/tmp/build all
-2. Set environment variable BUILD_DIR to point to the desired location:
+2. Set environment variable KBUILD_OUTPUT to point to the desired location:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
make distclean
make NAME_defconfig
make all
-Note that the command line "O=" setting overrides the BUILD_DIR environment
+Note that the command line "O=" setting overrides the KBUILD_OUTPUT environment
variable.
default "armv7" if CPU_V7
default "pxa" if CPU_PXA
default "sa1100" if CPU_SA1100
+ default "armv8" if ARM64
choice
prompt "Target select"
bool "Support ethernut5"
select CPU_ARM926EJS
-config TARGET_TOP9000
- bool "Support top9000"
- select CPU_ARM926EJS
-
config TARGET_MEESC
bool "Support meesc"
select CPU_ARM926EJS
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
+ select CPU_V7
config TARGET_MAXBCM
bool "Support maxbcm"
+ select CPU_V7
config TARGET_DEVKIT3250
bool "Support devkit3250"
config TARGET_MX6SABRESD
bool "Support mx6sabresd"
select CPU_V7
+ select SUPPORT_SPL
config TARGET_MX6SLEVK
bool "Support mx6slevk"
bool "Support hummingboard"
select CPU_V7
+config TARGET_KOSAGI_NOVENA
+ bool "Support Kosagi Novena"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config TARGET_TBS2910
+ bool "Support tbs2910"
+
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
select CPU_V7
select CPU_V7
select SUPPORT_SPL
-config TARGET_SUN4I
- bool "Support sun4i"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SUN5I
- bool "Support sun5i"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SUN6I
- bool "Support sun6i"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SUN7I
- bool "Support sun7i"
- select CPU_V7
- select SUPPORT_SPL
-
-config TARGET_SUN8I
- bool "Support sun8i"
- select CPU_V7
- select SUPPORT_SPL
+config ARCH_SUNXI
+ bool "Support sunxi (Allwinner) SoCs"
config TARGET_SNOWBALL
bool "Support snowball"
endchoice
-source "arch/arm/cpu/armv8/Kconfig"
-
source "arch/arm/cpu/arm926ejs/davinci/Kconfig"
source "arch/arm/cpu/armv7/exynos/Kconfig"
source "board/isee/igep0033/Kconfig"
source "board/jornada/Kconfig"
source "board/karo/tx25/Kconfig"
+source "board/kosagi/novena/Kconfig"
source "board/logicpd/imx27lite/Kconfig"
source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
source "board/syteco/jadecpu/Kconfig"
source "board/syteco/zmx25/Kconfig"
source "board/taskit/stamp9g20/Kconfig"
+source "board/tbs/tbs2910/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/xaeniax/Kconfig"
source "board/zipitz2/Kconfig"
+source "arch/arm/Kconfig.debug"
+
endmenu
--- /dev/null
+menu "ARM debug"
+
+config DEBUG_LL
+ bool "Low-level debugging functions"
+ depends on !ARM64
+ help
+ Say Y here to include definitions of printascii, printch, printhex
+ in U-Boot. This is helpful if you are debugging code that
+ executes before the console is initialized.
+
+choice
+ prompt "Low-level debugging port"
+ depends on DEBUG_LL
+
+ config DEBUG_LL_UART_8250
+ bool "Low-level debugging via 8250 UART"
+ help
+ Say Y here if you wish the debug print routes to direct
+ their output to an 8250 UART. You can use this option
+ to provide the parameters for the 8250 UART rather than
+ selecting one of the platform specific options above if
+ you know the parameters for the port.
+
+ This option is preferred over the platform specific
+ options; the platform specific options are deprecated
+ and will be soon removed.
+
+endchoice
+
+config DEBUG_LL_INCLUDE
+ string
+ depends on DEBUG_LL
+ default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
+ default "mach/debug-macro.S"
+
+# Compatibility options for 8250
+config DEBUG_UART_8250
+ bool
+
+config DEBUG_UART_PHYS
+ hex "Physical base address of debug UART"
+ depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
+
+# This is not used in U-Boot
+config DEBUG_UART_VIRT
+ hex
+ default DEBUG_UART_PHYS
+ depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
+
+config DEBUG_UART_8250_SHIFT
+ int "Register offset shift for the 8250 debug UART"
+ depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
+ default 2
+
+config DEBUG_UART_8250_WORD
+ bool "Use 32-bit accesses for 8250 UART"
+ depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
+ depends on DEBUG_UART_8250_SHIFT >= 2
+
+config DEBUG_UART_8250_FLOW_CONTROL
+ bool "Enable flow control for 8250 UART"
+ depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250
+
+endmenu
/*
* Stub implementations for l2 cache operations
*/
-void __l2_cache_disable(void) {}
-
-void l2_cache_disable(void)
- __attribute__((weak, alias("__l2_cache_disable")));
+__weak void l2_cache_disable(void) {}
int i;
for (i = 0; i < 8; i++) {
+ /* cppcheck-suppress nullPointer */
vt[i] = ldr_pc;
+ /* cppcheck-suppress nullPointer */
vt[i + 8] = start_addr + (4 * i);
}
}
* fine.
*/
extern uint32_t _start;
+
+ /* cppcheck-suppress nullPointer */
memcpy(0x0, &_start, 0x60);
}
TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
#elif defined(CONFIG_MX28)
now = readl(&timrot_regs->hw_timrot_running_count0);
+#else
+#error "Don't know how to read timrot_regs"
#endif
if (lastdec >= now) {
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-extra-y = start.o
-obj-y = cpu.o
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * CPU specific code for an unknown cpu
- * - hence fairly empty......
- */
-
-#include <common.h>
-#include <command.h>
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * we turn off caches etc ...
- */
-
- disable_interrupts ();
-
- /* Since the CM has unknown processor we do not support
- * cache operations
- */
-
- return (0);
-}
+++ /dev/null
-/*
- * armboot - Startup Code for ARM926EJS CPU-core
- *
- * Copyright (c) 2003 Texas Instruments
- *
- * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
- *
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
- * Copyright (c) 2003 Kshitij <kshitij@ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * setup memory and board specific bits prior to relocation.
- * relocate armboot to ram
- * setup stack
- *
- *************************************************************************
- */
-
- .globl reset
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
- bl _main
-
-/*------------------------------------------------------------------------------*/
-
- .globl c_runtime_cpu_setup
-c_runtime_cpu_setup:
-
- mov pc, lr
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-cpu_init_crit:
- /* arm_int_generic assumes the ARM boot monitor, or user software,
- * has initialized the platform
- */
- mov pc, lr /* back to my caller */
-#endif
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
#include <power/tps65910.h>
+#include <linux/compiler.h>
struct ctrl_stat *cstat = (struct ctrl_stat *)CTRL_BASE;
/**
* get_board_rev() - setup to pass kernel board revision information
- * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
+ * returns: 0 for the ATAG REVISION tag value.
*/
-u32 get_board_rev(void)
+u32 __weak get_board_rev(void)
{
- return BOARD_REV_ID;
+ return 0;
}
/**
* to get size details from Current Cache Size ID Register(CCSIDR)
*/
static void set_csselr(u32 level, u32 type)
-{ u32 csselr = level << 1 | type;
+{
+ u32 csselr = level << 1 | type;
/* Write to Cache Size Selection Register(CSSELR) */
asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
u32 num_ways, u32 way_shift,
u32 log2_line_len)
{
- int way, set, setway;
+ int way, set;
+ u32 setway;
/*
* For optimal assembly code:
u32 num_ways, u32 way_shift,
u32 log2_line_len)
{
- int way, set, setway;
+ int way, set;
+ u32 setway;
/*
* For optimal assembly code:
static void v7_maint_dcache_all(u32 operation)
{
u32 level, cache_type, level_start_bit = 0;
-
u32 clidr = get_clidr();
for (level = 0; level < 7; level++) {
}
}
-static void v7_dcache_clean_inval_range(u32 start,
- u32 stop, u32 line_len)
+static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
{
u32 mva;
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
-
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
v7_outer_cache_inval_range(start, stop);
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+ if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+ return MXC_HCLK; /* OSC 24Mhz */
+#endif
perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1);
writel(0, &mxc_ccm->ccdr);
}
+#ifdef CONFIG_MX6SL
+static void set_preclk_from_osc(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ u32 reg;
+
+ reg = readl(&mxc_ccm->cscmr1);
+ reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
+ writel(reg, &mxc_ccm->cscmr1);
+}
+#endif
+
int arch_cpu_init(void)
{
init_aips();
if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
set_ahb_rate(132000000);
+ /* Set perclk to source from OSC 24MHz */
+#if defined(CONFIG_MX6SL)
+ set_preclk_from_osc();
+#endif
+
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
- * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
- * to SBMR1, which will determine the boot device.
+ * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
+ * instead of SBMR1 to determine the boot device.
*/
const struct boot_mode soc_boot_modes[] = {
{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
bool "CompuLab CM-T3530 and CM-T3730 boards"
select SUPPORT_SPL
+config TARGET_CM_T3517
+ bool "CompuLab CM-T3517 boards"
+
config TARGET_DEVKIT8000
bool "TimLL OMAP3 Devkit8000"
select SUPPORT_SPL
source "board/ti/sdp3430/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
+source "board/compulab/cm_t3517/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
config SYS_SOC
default "rmobile"
+config RMOBILE_EXTRAM_BOOT
+ bool "Enable boot from RAM"
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
+ default n
+
source "board/atmark-techno/armadillo-800eva/Kconfig"
source "board/renesas/koelsch/Kconfig"
source "board/renesas/lager/Kconfig"
cmp r1, #3 /* has already been set up */
bicne r0, r0, #0xe7
orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */
-
- ldr r2, =0xFF000044 /* PRR */
- ldr r1, [r2]
- and r1, r1, #0x7F00
- lsrs r1, r1, #8
- cmp r1, #0x45 /* 0x45 is ID of r8a7790 */
- bne L2CTLR_5_SKIP
+#if defined(CONFIG_R8A7790)
orrne r0, r0, #0x20 /* L2CTLR[5] */
-L2CTLR_5_SKIP:
+#endif
mcrne p15, 1, r0, c9, c0, 2
-
_exit_init_l2_a15:
ldr r3, =(CONFIG_SYS_INIT_SP_ADDR)
sub sp, r3, #4
return clock;
}
+unsigned int cm_get_spi_controller_clk_hz(void)
+{
+ uint32_t reg, clock = 0;
+
+ clock = cm_get_per_vco_clk_hz();
+
+ /* get the clock prior L4 SP divider (periph_base_clk) */
+ reg = readl(&clock_manager_base->per_pll.perbaseclk);
+ clock /= (reg + 1);
+
+ return clock;
+}
+
static void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+ printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
}
int set_cpu_clk_info(void)
/* Add device descriptor to FPGA device table */
socfpga_fpga_add();
+
+#ifdef CONFIG_DESIGNWARE_SPI
+ /* Get Designware SPI controller out of reset */
+ socfpga_spim_enable();
+#endif
+
return 0;
}
#endif
}
}
+
+/* SPI Master enable (its held in reset by the preloader) */
+void socfpga_spim_enable(void)
+{
+ const void *reset = &reset_manager_base->per_mod_reset;
+
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
+ clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
+}
obj-y += board.o
obj-y += clock.o
obj-y += pinmux.o
-obj-$(CONFIG_SUN6I) += prcm.o
-obj-$(CONFIG_SUN8I) += prcm.o
-obj-$(CONFIG_SUN4I) += clock_sun4i.o
-obj-$(CONFIG_SUN5I) += clock_sun4i.o
-obj-$(CONFIG_SUN6I) += clock_sun6i.o
-obj-$(CONFIG_SUN7I) += clock_sun4i.o
-obj-$(CONFIG_SUN8I) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN6I) += prcm.o
+obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN6I) += p2wi.o
+obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
+obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
ifndef CONFIG_SPL_BUILD
obj-y += cpu_info.o
endif
ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_SUN4I) += dram.o
-obj-$(CONFIG_SUN5I) += dram.o
-obj-$(CONFIG_SUN7I) += dram.o
+obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
+obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
-#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
+#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
+#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
void reset_cpu(ulong addr)
{
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
static const struct sunxi_wdog *wdog =
&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
/* sun5i sometimes gets stuck without this */
writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
}
-#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
/* do some early init */
void s_init(void)
{
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \
- defined CONFIG_SUN6I || defined CONFIG_SUN8I)
+#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
+ /* Magic (undocmented) value taken from boot0, without this DRAM
+ * access gets messed up (seems cache related) */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
+#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
+ defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
"mrc p15, 0, r0, c1, c0, 1\n"
APB0_DIV_1 << APB0_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_DMA);
#endif
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_prcm_reg * const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ /* Set PLL ldo voltage without this PLL6 does not work properly */
+ clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
+ PRCM_PLL_CTRL_LDO_KEY);
+ clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
+ PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+ clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+ clock_set_pll1(408000000);
+
+ writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
+
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
+ writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
+}
+#endif
+
void clock_init_uart(void)
{
struct sunxi_ccm_reg *const ccm =
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int k = 1;
+ int m = 1;
+
+ if (clk > 1152000000) {
+ k = 2;
+ } else if (clk > 768000000) {
+ k = 3;
+ m = 2;
+ }
+
+ /* Switch to 24MHz clock while changing PLL1 */
+ writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+ ATB_DIV_2 << ATB_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+
+ /* PLL1 rate = 24000000 * n * k / m */
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
+ CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
+ CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
+ sdelay(200);
+
+ /* Switch CPU to PLL1 */
+ writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+ ATB_DIV_2 << ATB_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll5(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int k = 2;
+ const int m = 1;
+
+ /* PLL5 rate = 24000000 * n * k / m */
+ writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+ CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
+ CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
+
+ udelay(5500);
+}
+
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
puts("CPU: Allwinner A10 (SUN4I)\n");
-#elif defined CONFIG_SUN5I
+#elif defined CONFIG_MACH_SUN5I
u32 val = readl(SUNXI_SID_BASE + 0x08);
switch ((val >> 12) & 0xf) {
case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
default: puts("CPU: Allwinner A1X (SUN5I)\n");
}
-#elif defined CONFIG_SUN6I
+#elif defined CONFIG_MACH_SUN6I
puts("CPU: Allwinner A31 (SUN6I)\n");
-#elif defined CONFIG_SUN7I
+#elif defined CONFIG_MACH_SUN7I
puts("CPU: Allwinner A20 (SUN7I)\n");
-#elif defined CONFIG_SUN8I
+#elif defined CONFIG_MACH_SUN8I
puts("CPU: Allwinner A23 (SUN8I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
struct sunxi_dram_reg *dram =
(struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
struct sunxi_timer_reg *timer =
(struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
u32 reg_val;
{
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
#else
clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
}
static u32 hpcr_value[32] = {
-#ifdef CONFIG_SUN5I
+#ifdef CONFIG_MACH_SUN5I
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0
#endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0, 0,
0, 0, 0, 0,
0x1035, 0x1031, 0x0731, 0x1035,
0x1031, 0x0301, 0x0301, 0x0731
#endif
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
0x0301, 0x0301, 0x0301, 0x0301,
0x0301, 0x0301, 0x0301, 0x0301,
0, 0, 0, 0,
setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
/* reset GPS */
clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
/* PLL5P and PLL6 are the potential clock sources for MBUS */
pll6x_clk = clock_get_pll6() / 1000000;
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
#endif
pll5p_clk = clock_get_pll5p() / 1000000;
* open DRAMC AHB & DLL register clock
* close it first
*/
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
udelay(22);
/* then open it */
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
#else
setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
static void dramc_clock_output_en(u32 on)
{
-#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
if (on)
else
clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
#endif
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (on)
setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
u32 reg_val;
u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
-#ifndef CONFIG_SUN7I
+#ifndef CONFIG_MACH_SUN7I
/* Appears that some kind of automatically initiated default
* ZQ calibration is already in progress at this point on sun4i/sun5i
* hardware, but not on sun7i. So it is reasonable to wait for its
if (!odt_en)
return;
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
/* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
* unless bit 24 is set in SDR_ZQCR1. Not much is known about the
* SDR_ZQCR1 register, but there are hints indicating that it might
/* dram clock off */
dramc_clock_output_en(0);
-#ifdef CONFIG_SUN4I
+#ifdef CONFIG_MACH_SUN4I
/* select dram controller 1 */
writel(DRAM_CSEL_MAGIC, &dram->csel);
#endif
writel(para->tpr2, &dram->tpr2);
reg_val = DRAM_MR_BURST_LENGTH(0x0);
-#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
+#if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
reg_val |= DRAM_MR_POWER_DOWN;
#endif
reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
/* disable drift compensation and set passive DQS window mode */
clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
-#ifdef CONFIG_SUN7I
+#ifdef CONFIG_MACH_SUN7I
/* Command rate timing mode 2T & 1T */
if (para->tpr4 & 0x1)
setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
/* try to autodetect the DRAM bus width and density */
para->io_width = 16;
para->bus_width = 32;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
/* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
para->density = 4096;
#else
--- /dev/null
+/*
+ * Sun6i platform dram controller init.
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/dram.h>
+#include <asm/arch/prcm.h>
+
+/* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */
+#define DRAM_CLK_DEFAULT 312000000
+#define DRAM_ZQ_DEFAULT 0x78
+
+struct dram_sun6i_para {
+ u8 bus_width;
+ u8 chan;
+ u8 rank;
+ u8 rows;
+ u16 page_size;
+};
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+static void await_completion(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ while ((readl(reg) & mask) != val) {
+ if (timer_get_us() > tmo)
+ panic("Timeout initialising DRAM\n");
+ }
+}
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int dram_clk_div = 2;
+
+ clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
+
+ clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
+ CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
+ CCM_DRAMCLK_CFG_UPD);
+ await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
+
+ /* deassert mctl reset */
+ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
+
+ /* enable mctl clock */
+ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
+{
+ struct sunxi_mctl_phy_reg *mctl_phy;
+
+ if (ch_index == 0)
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ else
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+
+ /* disable + reset dlls */
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
+ if (para->bus_width == 32) {
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
+ writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
+ }
+ udelay(2);
+
+ /* enable + reset dlls */
+ writel(0, &mctl_phy->acdllcr);
+ writel(0, &mctl_phy->dx0dllcr);
+ writel(0, &mctl_phy->dx1dllcr);
+ if (para->bus_width == 32) {
+ writel(0, &mctl_phy->dx2dllcr);
+ writel(0, &mctl_phy->dx3dllcr);
+ }
+ udelay(22);
+
+ /* enable and release reset of dlls */
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
+ if (para->bus_width == 32) {
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
+ writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
+ }
+ udelay(22);
+}
+
+static bool mctl_rank_detect(u32 *gsr0, int rank)
+{
+ const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
+ const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
+
+ await_completion(gsr0, done, done);
+ await_completion(gsr0 + 0x10, done, done);
+
+ return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
+}
+
+static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_ctl_reg *mctl_ctl;
+ struct sunxi_mctl_phy_reg *mctl_phy;
+
+ if (ch_index == 0) {
+ mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ } else {
+ mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+ }
+
+ writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
+ await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
+
+ /* PHY initialization */
+ writel(MCTL_PGCR, &mctl_phy->pgcr);
+ writel(MCTL_MR0, &mctl_phy->mr0);
+ writel(MCTL_MR1, &mctl_phy->mr1);
+ writel(MCTL_MR2, &mctl_phy->mr2);
+ writel(MCTL_MR3, &mctl_phy->mr3);
+
+ writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
+ &mctl_phy->ptr0);
+ /* Unknown magic performed by boot0 */
+ if ((readl(SUNXI_RTC_BASE + 0x20c) & 3) == 2)
+ setbits_le32(&mctl_phy->ptr0, 1 << 18);
+
+ writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
+ writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
+
+ writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
+ (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
+ (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
+ &mctl_phy->dtpr0);
+
+ writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
+ (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
+ ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
+ (MCTL_TAOND << 0), &mctl_phy->dtpr1);
+
+ writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
+ (MCTL_TEXSR << 0), &mctl_phy->dtpr2);
+
+ writel(1, &mctl_ctl->dfitphyupdtype0);
+ writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
+ writel(MCTL_DSGCR, &mctl_phy->dsgcr);
+ writel(MCTL_DXCCR, &mctl_phy->dxccr);
+ writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
+ writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
+ writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
+ writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
+
+ await_completion(&mctl_phy->pgsr, 0x03, 0x03);
+
+ writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1);
+
+ setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
+ writel(MCTL_PIR_STEP1, &mctl_phy->pir);
+ udelay(10);
+ await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
+
+ /* rank detect */
+ if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
+ para->rank = 1;
+ clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
+ }
+
+ /*
+ * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
+ * assume nothing is connected to channel 1.
+ */
+ if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
+ para->chan = 1;
+ clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
+ return;
+ }
+
+ /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
+ if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
+ para->bus_width = 16;
+ para->page_size = 2048;
+ setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
+ setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
+ clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
+ clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
+ }
+
+ setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
+ writel(MCTL_PIR_STEP2, &mctl_phy->pir);
+ udelay(10);
+ await_completion(&mctl_phy->pgsr, 0x11, 0x11);
+
+ if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
+ panic("Training error initialising DRAM\n");
+
+ /* Move to configure state */
+ writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
+ await_completion(&mctl_ctl->sstat, 0x07, 0x01);
+
+ /* Set number of clks per micro-second */
+ writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u);
+ /* Set number of clks per 100 nano-seconds */
+ writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n);
+ /* Set memory timing registers */
+ writel(MCTL_TREFI, &mctl_ctl->trefi);
+ writel(MCTL_TMRD, &mctl_ctl->tmrd);
+ writel(MCTL_TRFC, &mctl_ctl->trfc);
+ writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
+ writel(MCTL_TRTW, &mctl_ctl->trtw);
+ writel(MCTL_TAL, &mctl_ctl->tal);
+ writel(MCTL_TCL, &mctl_ctl->tcl);
+ writel(MCTL_TCWL, &mctl_ctl->tcwl);
+ writel(MCTL_TRAS, &mctl_ctl->tras);
+ writel(MCTL_TRC, &mctl_ctl->trc);
+ writel(MCTL_TRCD, &mctl_ctl->trcd);
+ writel(MCTL_TRRD, &mctl_ctl->trrd);
+ writel(MCTL_TRTP, &mctl_ctl->trtp);
+ writel(MCTL_TWR, &mctl_ctl->twr);
+ writel(MCTL_TWTR, &mctl_ctl->twtr);
+ writel(MCTL_TEXSR, &mctl_ctl->texsr);
+ writel(MCTL_TXP, &mctl_ctl->txp);
+ writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
+ writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
+ writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
+ writel(MCTL_TDQS, &mctl_ctl->tdqs);
+ writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
+ writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
+ writel(MCTL_TCKE, &mctl_ctl->tcke);
+ writel(MCTL_TMOD, &mctl_ctl->tmod);
+ writel(MCTL_TRSTL, &mctl_ctl->trstl);
+ writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
+ writel(MCTL_TMRR, &mctl_ctl->tmrr);
+ writel(MCTL_TCKESR, &mctl_ctl->tckesr);
+ writel(MCTL_TDPD, &mctl_ctl->tdpd);
+
+ /* Unknown magic performed by boot0 */
+ setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
+ clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
+
+ /* Select 16/32-bits mode for MCTL */
+ if (para->bus_width == 16)
+ setbits_le32(&mctl_ctl->ppcfg, 1);
+
+ /* Set DFI timing registers */
+ writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
+ writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
+ writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
+ writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
+
+ writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
+
+ /* DFI update configuration register */
+ writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
+
+ /* Move to access state */
+ writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
+ await_completion(&mctl_ctl->sstat, 0x07, 0x03);
+}
+
+static void mctl_com_init(struct dram_sun6i_para *para)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_mctl_phy_reg * const mctl_phy1 =
+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+ struct sunxi_prcm_reg * const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
+ ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
+ MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
+ MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
+
+ /* Unknown magic performed by boot0 */
+ setbits_le32(&mctl_com->dbgcr, (1 << 6));
+
+ if (para->chan == 1) {
+ /* Shutdown channel 1 */
+ setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
+ setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
+ clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
+ /*
+ * CH0 ?? this is what boot0 does. Leave as is until we can
+ * confirm this.
+ */
+ setbits_le32(&prcm->vdd_sys_pwroff,
+ PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
+ }
+}
+
+static void mctl_port_cfg(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ /* enable DRAM AXI clock for CPU access */
+ setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
+
+ /* Bunch of magic writes performed by boot0 */
+ writel(0x00400302, &mctl_com->rmcr[0]);
+ writel(0x01000307, &mctl_com->rmcr[1]);
+ writel(0x00400302, &mctl_com->rmcr[2]);
+ writel(0x01000307, &mctl_com->rmcr[3]);
+ writel(0x01000307, &mctl_com->rmcr[4]);
+ writel(0x01000303, &mctl_com->rmcr[6]);
+ writel(0x01000303, &mctl_com->mmcr[0]);
+ writel(0x00400310, &mctl_com->mmcr[1]);
+ writel(0x01000307, &mctl_com->mmcr[2]);
+ writel(0x01000303, &mctl_com->mmcr[3]);
+ writel(0x01800303, &mctl_com->mmcr[4]);
+ writel(0x01800303, &mctl_com->mmcr[5]);
+ writel(0x01800303, &mctl_com->mmcr[6]);
+ writel(0x01800303, &mctl_com->mmcr[7]);
+ writel(0x01000303, &mctl_com->mmcr[8]);
+ writel(0x00000002, &mctl_com->mmcr[15]);
+ writel(0x00000310, &mctl_com->mbagcr[0]);
+ writel(0x00400310, &mctl_com->mbagcr[1]);
+ writel(0x00400310, &mctl_com->mbagcr[2]);
+ writel(0x00000307, &mctl_com->mbagcr[3]);
+ writel(0x00000317, &mctl_com->mbagcr[4]);
+ writel(0x00000307, &mctl_com->mbagcr[5]);
+}
+
+static bool mctl_mem_matches(u32 offset)
+{
+ const int match_count = 64;
+ int i, matches = 0;
+
+ for (i = 0; i < match_count; i++) {
+ if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
+ readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
+ matches++;
+ }
+
+ return matches == match_count;
+}
+
+unsigned long sunxi_dram_init(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+ u32 offset;
+ int bank, bus, columns;
+
+ /* Set initial parameters, these get modified by the autodetect code */
+ struct dram_sun6i_para para = {
+ .bus_width = 32,
+ .chan = 2,
+ .rank = 2,
+ .page_size = 4096,
+ .rows = 16,
+ };
+
+ mctl_sys_init();
+
+ mctl_dll_init(0, ¶);
+ mctl_dll_init(1, ¶);
+
+ setbits_le32(&mctl_com->ccr,
+ MCTL_CCR_MASTER_CLK_EN |
+ MCTL_CCR_CH0_CLK_EN |
+ MCTL_CCR_CH1_CLK_EN);
+
+ mctl_channel_init(0, ¶);
+ mctl_channel_init(1, ¶);
+ mctl_com_init(¶);
+ mctl_port_cfg();
+
+ /*
+ * Change to 1 ch / sequence / 8192 byte pages / 16 rows /
+ * 8 bit banks / 1 rank mode.
+ */
+ clrsetbits_le32(&mctl_com->cr,
+ MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
+ MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
+ MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
+ MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
+ MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
+
+ /* Detect and set page size */
+ for (columns = 7; columns < 20; columns++) {
+ if (mctl_mem_matches(1 << columns))
+ break;
+ }
+ bus = (para.bus_width == 32) ? 2 : 1;
+ columns -= bus;
+ para.page_size = (1 << columns) * (bus << 1);
+ clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
+ MCTL_CR_PAGE_SIZE(para.page_size));
+
+ /* Detect and set rows */
+ for (para.rows = 11; para.rows < 16; para.rows++) {
+ offset = 1 << (para.rows + columns + bus);
+ if (mctl_mem_matches(offset))
+ break;
+ }
+ clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
+ MCTL_CR_ROW(para.rows));
+
+ /* Detect bank size */
+ offset = 1 << (para.rows + columns + bus + 2);
+ bank = mctl_mem_matches(offset) ? 0 : 1;
+
+ /* Restore interleave, chan and rank values, set bank size */
+ clrsetbits_le32(&mctl_com->cr,
+ MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
+ MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
+ MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
+ MCTL_CR_RANK(para.rank));
+
+ return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);
+}
--- /dev/null
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/p2wi.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+void p2wi_init(void)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+ /* Enable p2wi and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+
+ /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+ writel(P2WI_CTRL_RESET, &p2wi->ctrl);
+ sdelay(0x100);
+ writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+ &p2wi->cc);
+}
+
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ unsigned long tmo = timer_get_us() + 1000000;
+
+ writel(P2WI_PM_DEV_ADDR(slave_addr) |
+ P2WI_PM_CTRL_ADDR(ctrl_reg) |
+ P2WI_PM_INIT_DATA(init_data) |
+ P2WI_PM_INIT_SEND,
+ &p2wi->pm);
+
+ while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
+ if (timer_get_us() > tmo)
+ return -ETIME;
+ }
+
+ return 0;
+}
+
+static int p2wi_await_trans(void)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ unsigned long tmo = timer_get_us() + 1000000;
+ int ret;
+ u8 reg;
+
+ while (1) {
+ reg = readl(&p2wi->status);
+ if (reg & P2WI_STAT_TRANS_ERR) {
+ ret = -EIO;
+ break;
+ }
+ if (reg & P2WI_STAT_TRANS_DONE) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() > tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(reg, &p2wi->status); /* Clear status bits */
+ return ret;
+}
+
+int p2wi_read(const u8 addr, u8 *data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ int ret;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+ writel(P2WI_DATA_NUM_BYTES(1) |
+ P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+ writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+ ret = p2wi_await_trans();
+
+ *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
+ return ret;
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
+ writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
+ writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
+ writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
+ writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
+
+ return p2wi_await_trans();
+}
#include <asm/io.h>
#include <asm/arch/gpio.h>
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val)
{
- u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_CFG_INDEX(pin);
- u32 offset = GPIO_CFG_OFFSET(pin);
- struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
-
- return 0;
}
-int sunxi_gpio_get_cfgpin(u32 pin)
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val)
{
- u32 cfg;
u32 bank = GPIO_BANK(pin);
- u32 index = GPIO_CFG_INDEX(pin);
- u32 offset = GPIO_CFG_OFFSET(pin);
struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+ sunxi_gpio_set_cfgbank(pio, pin, val);
+}
+
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset)
+{
+ u32 index = GPIO_CFG_INDEX(bank_offset);
+ u32 offset = GPIO_CFG_OFFSET(bank_offset);
+ u32 cfg;
+
cfg = readl(&pio->cfg[0] + index);
cfg >>= offset;
return cfg & 0xf;
}
+int sunxi_gpio_get_cfgpin(u32 pin)
+{
+ u32 bank = GPIO_BANK(pin);
+ struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
+
+ return sunxi_gpio_get_cfgbank(pio, pin);
+}
+
int sunxi_gpio_set_drv(u32 pin, u32 val)
{
u32 bank = GPIO_BANK(pin);
str r2, [r0]
dsb
- movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
- movt r0, #(SUNXI_CPUCFG_BASE >> 16)
+ movw r0, #(SUN7I_CPUCFG_BASE & 0xffff)
+ movt r0, #(SUN7I_CPUCFG_BASE >> 16)
@ CPU mask
and r1, r1, #3 @ only care about first cluster
config USE_PRIVATE_LIBGCC
default y if SPL_BUILD
-config SYS_CPU
- default "arm720t" if SPL_BUILD
- default "armv7" if !SPL_BUILD
-
source "arch/arm/cpu/armv7/tegra20/Kconfig"
source "arch/arm/cpu/armv7/tegra30/Kconfig"
source "arch/arm/cpu/armv7/tegra114/Kconfig"
endchoice
+config CMD_PINMON
+ bool "Enable boot mode pins monitor command"
+ depends on !SPL_BUILD
+ default y
+ help
+ The command "pinmon" shows the state of the boot mode pins.
+ The boot mode pins are latched when the system reset is deasserted
+ and determine which device the system should load a boot image from.
+
+config SOC_INIT
+ bool
+ default SPL_BUILD
+
+config DRAM_INIT
+ bool
+ default SPL_BUILD
+
+choice
+ prompt "DDR3 Frequency select"
+ depends on DRAM_INIT
+
+config DDR_FREQ_1600
+ bool "DDR3 1600"
+ depends on MACH_PH1_PRO4 || MACH_PH1_LD4
+
+config DDR_FREQ_1333
+ bool "DDR3 1333"
+ depends on MACH_PH1_LD4 || MACH_PH1_SLD8
+
+endchoice
+
+config DDR_FREQ
+ int
+ default 1333 if DDR_FREQ_1333
+ default 1600 if DDR_FREQ_1600
+
endmenu
obj-y += timer.o
obj-y += reset.o
obj-y += cache_uniphier.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o
obj-y += dram_init.o
obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
obj-$(CONFIG_UNIPHIER_SMP) += smp.o
-obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o
+obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-y += board_common.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
+#include <linux/compiler.h>
#include <asm/arch/led.h>
#include <asm/arch/board.h>
-void bcu_init(void);
+void __weak bcu_init(void)
+{
+};
void sbc_init(void);
void sg_init(void);
void pll_init(void);
int board_postclk_init(void)
{
+#ifdef CONFIG_SOC_INIT
bcu_init();
sbc_init();
sg_init();
+ uniphier_board_reset();
+
pll_init();
uniphier_board_init();
clkrst_init();
led_write(B, 2, , );
-
+#endif
pin_init();
led_write(B, 3, , );
DECLARE_GLOBAL_DATA_PTR;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_DRAM_INIT
led_write(B, 4, , );
{
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
- sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
-obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
- umc_init.o
+obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
+ clkrst_init.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
+
+/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
+struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
+ {
+ .base = 0x5a800100,
+ },
+ {
+ .base = 0x5a810100,
+ },
+ {
+ .base = 0x5a820100,
+ },
+};
CONFIG_SDRAM1_SIZE / 0x08000000);
}
-#if CONFIG_DDR_FREQ != 1333 && CONFIG_DDR_FREQ != 1600
-#error Unsupported DDR Frequency.
-#endif
-
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o sbc_init.o \
- sg_init.o pll_init.o clkrst_init.o pinctrl.o
-obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
- umc_init.o
+obj-$(CONFIG_SOC_INIT) += sbc_init.o sg_init.o pll_init.o clkrst_init.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+++ /dev/null
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/led.h>
-#include <asm/arch/board.h>
-
-void sbc_init(void);
-void sg_init(void);
-void pll_init(void);
-void pin_init(void);
-void clkrst_init(void);
-
-int board_postclk_init(void)
-{
- sbc_init();
-
- sg_init();
-
- pll_init();
-
- uniphier_board_init();
-
- led_write(B, 1, , );
-
- clkrst_init();
-
- led_write(B, 2, , );
-
- pin_init();
-
- led_write(B, 3, , );
-
- return 0;
-}
sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
#endif
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */
+ sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */
+#endif
+
writel(1, SG_LOADPINCTRL);
}
SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
+
+/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
+struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
+ {
+ .base = 0x5a800100,
+ },
+ {
+ .base = 0x5a810100,
+ },
+};
CONFIG_SDRAM1_SIZE / 0x08000000);
}
-#if CONFIG_DDR_FREQ != 1600
-#error Unsupported DDR frequency.
-#endif
-
#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
(CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o
obj-y += platdevice.o
obj-y += boot-mode.o
-obj-$(CONFIG_BOARD_POSTCLK_INIT) += board_postclk_init.o bcu_init.o \
- sbc_init.o sg_init.o pll_init.o clkrst_init.o pinctrl.o
-obj-$(CONFIG_SPL_BUILD) += pll_spectrum.o \
- umc_init.o
+obj-$(CONFIG_SOC_INIT) += bcu_init.o sbc_init.o sg_init.o pll_init.o \
+ clkrst_init.o
+obj-$(CONFIG_BOARD_POSTCLK_INIT) += pinctrl.o
+obj-$(CONFIG_DRAM_INIT) += pll_spectrum.o umc_init.o
+++ /dev/null
-#include "../ph1-ld4/board_postclk_init.c"
SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
+
+/* USB : TODO for Masahiro Yamada: move base address to Device Tree */
+struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
+ {
+ .base = 0x5a800100,
+ },
+ {
+ .base = 0x5a810100,
+ },
+ {
+ .base = 0x5a820100,
+ },
+};
CONFIG_SDRAM1_SIZE / 0x08000000);
}
-#if CONFIG_DDR_FREQ != 1333
-#error Unsupported DDR frequency.
-#endif
-
#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
(CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
-#include <asm/arch/board.h>
void reset_cpu(unsigned long ignored)
{
u32 tmp;
- uniphier_board_reset();
-
writel(5, SC_IRQTIMSET); /* default value */
tmp = readl(SC_SLFRSTSEL);
config TARGET_ZYNQ_ZC770
bool "Zynq ZC770 Board"
+config TARGET_ZYNQ_ZYBO
+ bool "Zynq Zybo Board"
+
endchoice
config SYS_BOARD
default "zynq_microzed" if TARGET_ZYNQ_MICROZED
default "zynq_zc70x" if TARGET_ZYNQ_ZC70X
default "zynq_zc770" if TARGET_ZYNQ_ZC770
+ default "zynq_zybo" if TARGET_ZYNQ_ZYBO
endif
* first stage bootloader. To get ECC to work all memory has
* been initialized by writing any value.
*/
+ /* cppcheck-suppress nullPointer */
memset((void *)0, 0, 1 * 1024 * 1024);
} else {
puts("ECC disabled ");
+++ /dev/null
-if ARM64
-
-config SYS_CPU
- default "armv8"
-
-endif
+dtb-$(CONFIG_MACH_SUN7I) += sun7i-a20-pcduino3.dtb
dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
+ zynq-zybo.dtb \
zynq-microzed.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
+dtb-$(CONFIG_SOCFPGA) += socfpga_cyclone5_socrates.dtb
+
targets += $(dtb-y)
DTC_FLAGS += -R 4 -p 0x1000
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ timer0 = &timer0;
+ timer1 = &timer1;
+ timer2 = &timer2;
+ timer3 = &timer3;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ intc: intc@fffed000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffed000 0x1000>,
+ <0xfffec100 0x100>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+ ranges;
+
+ amba {
+ compatible = "arm,amba-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma@ffe01000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xffe01000 0x1000>;
+ interrupts = <0 104 4>,
+ <0 105 4>,
+ <0 106 4>,
+ <0 107 4>,
+ <0 108 4>,
+ <0 109 4>,
+ <0 110 4>,
+ <0 111 4>;
+ #dma-cells = <1>;
+ #dma-channels = <8>;
+ #dma-requests = <32>;
+ clocks = <&l4_main_clk>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ can0: can@ffc00000 {
+ compatible = "bosch,d_can";
+ reg = <0xffc00000 0x1000>;
+ interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+ clocks = <&can0_clk>;
+ status = "disabled";
+ };
+
+ can1: can@ffc01000 {
+ compatible = "bosch,d_can";
+ reg = <0xffc01000 0x1000>;
+ interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
+ clocks = <&can1_clk>;
+ status = "disabled";
+ };
+
+ clkmgr@ffd04000 {
+ compatible = "altr,clk-mgr";
+ reg = <0xffd04000 0x1000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ osc2: osc2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_periph_ref_clk: f2s_periph_ref_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_sdram_ref_clk: f2s_sdram_ref_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ main_pll: main_pll {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-pll-clock";
+ clocks = <&osc1>;
+ reg = <0x40>;
+
+ mpuclk: mpuclk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0xe0 0 9>;
+ reg = <0x48>;
+ };
+
+ mainclk: mainclk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0xe4 0 9>;
+ reg = <0x4C>;
+ };
+
+ dbg_base_clk: dbg_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ div-reg = <0xe8 0 9>;
+ reg = <0x50>;
+ };
+
+ main_qspi_clk: main_qspi_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x54>;
+ };
+
+ main_nand_sdmmc_clk: main_nand_sdmmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x58>;
+ };
+
+ cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&main_pll>;
+ reg = <0x5C>;
+ };
+ };
+
+ periph_pll: periph_pll {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-pll-clock";
+ clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
+ reg = <0x80>;
+
+ emac0_clk: emac0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x88>;
+ };
+
+ emac1_clk: emac1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x8C>;
+ };
+
+ per_qspi_clk: per_qsi_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x90>;
+ };
+
+ per_nand_mmc_clk: per_nand_mmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x94>;
+ };
+
+ per_base_clk: per_base_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x98>;
+ };
+
+ h2f_usr1_clk: h2f_usr1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&periph_pll>;
+ reg = <0x9C>;
+ };
+ };
+
+ sdram_pll: sdram_pll {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-pll-clock";
+ clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
+ reg = <0xC0>;
+
+ ddr_dqs_clk: ddr_dqs_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&sdram_pll>;
+ reg = <0xC8>;
+ };
+
+ ddr_2x_dqs_clk: ddr_2x_dqs_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&sdram_pll>;
+ reg = <0xCC>;
+ };
+
+ ddr_dq_clk: ddr_dq_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&sdram_pll>;
+ reg = <0xD0>;
+ };
+
+ h2f_usr2_clk: h2f_usr2_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&sdram_pll>;
+ reg = <0xD4>;
+ };
+ };
+
+ mpu_periph_clk: mpu_periph_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&mpuclk>;
+ fixed-divider = <4>;
+ };
+
+ mpu_l2_ram_clk: mpu_l2_ram_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&mpuclk>;
+ fixed-divider = <2>;
+ };
+
+ l4_main_clk: l4_main_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>;
+ clk-gate = <0x60 0>;
+ };
+
+ l3_main_clk: l3_main_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-perip-clk";
+ clocks = <&mainclk>;
+ fixed-divider = <1>;
+ };
+
+ l3_mp_clk: l3_mp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>;
+ div-reg = <0x64 0 2>;
+ clk-gate = <0x60 1>;
+ };
+
+ l3_sp_clk: l3_sp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>;
+ div-reg = <0x64 2 2>;
+ };
+
+ l4_mp_clk: l4_mp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>, <&per_base_clk>;
+ div-reg = <0x64 4 3>;
+ clk-gate = <0x60 2>;
+ };
+
+ l4_sp_clk: l4_sp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&mainclk>, <&per_base_clk>;
+ div-reg = <0x64 7 3>;
+ clk-gate = <0x60 3>;
+ };
+
+ dbg_at_clk: dbg_at_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ div-reg = <0x68 0 2>;
+ clk-gate = <0x60 4>;
+ };
+
+ dbg_clk: dbg_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ div-reg = <0x68 2 2>;
+ clk-gate = <0x60 5>;
+ };
+
+ dbg_trace_clk: dbg_trace_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ div-reg = <0x6C 0 3>;
+ clk-gate = <0x60 6>;
+ };
+
+ dbg_timer_clk: dbg_timer_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&dbg_base_clk>;
+ clk-gate = <0x60 7>;
+ };
+
+ cfg_clk: cfg_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&cfg_h2f_usr0_clk>;
+ clk-gate = <0x60 8>;
+ };
+
+ h2f_user0_clk: h2f_user0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&cfg_h2f_usr0_clk>;
+ clk-gate = <0x60 9>;
+ };
+
+ emac_0_clk: emac_0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&emac0_clk>;
+ clk-gate = <0xa0 0>;
+ };
+
+ emac_1_clk: emac_1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&emac1_clk>;
+ clk-gate = <0xa0 1>;
+ };
+
+ usb_mp_clk: usb_mp_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 2>;
+ div-reg = <0xa4 0 3>;
+ };
+
+ spi_m_clk: spi_m_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 3>;
+ div-reg = <0xa4 3 3>;
+ };
+
+ can0_clk: can0_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 4>;
+ div-reg = <0xa4 6 3>;
+ };
+
+ can1_clk: can1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 5>;
+ div-reg = <0xa4 9 3>;
+ };
+
+ gpio_db_clk: gpio_db_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&per_base_clk>;
+ clk-gate = <0xa0 6>;
+ div-reg = <0xa8 0 24>;
+ };
+
+ h2f_user1_clk: h2f_user1_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&h2f_usr1_clk>;
+ clk-gate = <0xa0 7>;
+ };
+
+ sdmmc_clk: sdmmc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clk-gate = <0xa0 8>;
+ clk-phase = <0 135>;
+ };
+
+ nand_x_clk: nand_x_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clk-gate = <0xa0 9>;
+ };
+
+ nand_clk: nand_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clk-gate = <0xa0 10>;
+ fixed-divider = <4>;
+ };
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+ clk-gate = <0xa0 11>;
+ };
+ };
+ };
+
+ gmac0: ethernet@ff700000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x60 0>;
+ reg = <0xff700000 0x2000>;
+ interrupts = <0 115 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+ clocks = <&emac0_clk>;
+ clock-names = "stmmaceth";
+ resets = <&rst EMAC0_RESET>;
+ reset-names = "stmmaceth";
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@ff702000 {
+ compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+ altr,sysmgr-syscon = <&sysmgr 0x60 2>;
+ reg = <0xff702000 0x2000>;
+ interrupts = <0 120 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+ clocks = <&emac1_clk>;
+ clock-names = "stmmaceth";
+ resets = <&rst EMAC1_RESET>;
+ reset-names = "stmmaceth";
+ snps,multicast-filter-bins = <256>;
+ snps,perfect-filter-entries = <128>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@ffc04000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc04000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 158 0x4>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffc05000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc05000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 159 0x4>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffc06000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc06000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 160 0x4>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffc07000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0xffc07000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ interrupts = <0 161 0x4>;
+ status = "disabled";
+ };
+
+ gpio0: gpio@ff708000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff708000 0x1000>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <29>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 164 4>;
+ };
+ };
+
+ gpio1: gpio@ff709000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff709000 0x1000>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <29>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 165 4>;
+ };
+ };
+
+ gpio2: gpio@ff70a000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0xff70a000 0x1000>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+
+ portc: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <27>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 166 4>;
+ };
+ };
+
+ sdr: sdr@ffc25000 {
+ compatible = "syscon";
+ reg = <0xffc25000 0x1000>;
+ };
+
+ sdramedac {
+ compatible = "altr,sdram-edac";
+ altr,sdr-syscon = <&sdr>;
+ interrupts = <0 39 4>;
+ };
+
+ L2: l2-cache@fffef000 {
+ compatible = "arm,pl310-cache";
+ reg = <0xfffef000 0x1000>;
+ interrupts = <0 38 0x04>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <1 1 1>;
+ arm,data-latency = <2 1 1>;
+ };
+
+ mmc: dwmmc0@ff704000 {
+ compatible = "altr,socfpga-dw-mshc";
+ reg = <0xff704000 0x1000>;
+ interrupts = <0 139 4>;
+ fifo-depth = <0x400>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&l4_mp_clk>, <&sdmmc_clk>;
+ clock-names = "biu", "ciu";
+ };
+
+ /* Local timer */
+ timer@fffec600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xfffec600 0x100>;
+ interrupts = <1 13 0xf04>;
+ clocks = <&mpu_periph_clk>;
+ };
+
+ timer0: timer0@ffc08000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 167 4>;
+ reg = <0xffc08000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer";
+ };
+
+ timer1: timer1@ffc09000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 168 4>;
+ reg = <0xffc09000 0x1000>;
+ clocks = <&l4_sp_clk>;
+ clock-names = "timer";
+ };
+
+ timer2: timer2@ffd00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 169 4>;
+ reg = <0xffd00000 0x1000>;
+ clocks = <&osc1>;
+ clock-names = "timer";
+ };
+
+ timer3: timer3@ffd01000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 170 4>;
+ reg = <0xffd01000 0x1000>;
+ clocks = <&osc1>;
+ clock-names = "timer";
+ };
+
+ uart0: serial0@ffc02000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xffc02000 0x1000>;
+ interrupts = <0 162 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&l4_sp_clk>;
+ };
+
+ uart1: serial1@ffc03000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xffc03000 0x1000>;
+ interrupts = <0 163 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&l4_sp_clk>;
+ };
+
+ rst: rstmgr@ffd05000 {
+ #reset-cells = <1>;
+ compatible = "altr,rst-mgr";
+ reg = <0xffd05000 0x1000>;
+ };
+
+ usbphy0: usbphy@0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ status = "okay";
+ };
+
+ usb0: usb@ffb00000 {
+ compatible = "snps,dwc2";
+ reg = <0xffb00000 0xffff>;
+ interrupts = <0 125 4>;
+ clocks = <&usb_mp_clk>;
+ clock-names = "otg";
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb1: usb@ffb40000 {
+ compatible = "snps,dwc2";
+ reg = <0xffb40000 0xffff>;
+ interrupts = <0 128 4>;
+ clocks = <&usb_mp_clk>;
+ clock-names = "otg";
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@ffd02000 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd02000 0x1000>;
+ interrupts = <0 171 4>;
+ clocks = <&osc1>;
+ status = "disabled";
+ };
+
+ watchdog1: watchdog@ffd03000 {
+ compatible = "snps,dw-wdt";
+ reg = <0xffd03000 0x1000>;
+ interrupts = <0 172 4>;
+ clocks = <&osc1>;
+ status = "disabled";
+ };
+
+ sysmgr: sysmgr@ffd08000 {
+ compatible = "altr,sys-mgr", "syscon";
+ reg = <0xffd08000 0x4000>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+ soc {
+ clkmgr@ffd04000 {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+
+ mmc0: dwmmc0@ff704000 {
+ num-slots = <1>;
+ broken-cd;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ };
+
+ ethernet@ff702000 {
+ phy-mode = "rgmii";
+ phy-addr = <0xffffffff>; /* probe for phy addr */
+ status = "okay";
+ };
+
+ sysmgr@ffd08000 {
+ cpu1-start-addr = <0xffd080c4>;
+ };
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "EBV SOCrates";
+ compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x40000000>; /* 1GB */
+ };
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ rtc: rtc@68 {
+ compatible = "stm,m41t82";
+ reg = <0x68>;
+ };
+};
+
+&mmc {
+ status = "okay";
+};
--- /dev/null
+/*
+ * Copyright 2014 Zoltan HERPAI
+ * Zoltan HERPAI <wigyori@uid0.hu>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "LinkSprite pcDuino3";
+ compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ soc@01c00000 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+ };
+
+ usbphy: phy@01c13400 {
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+ };
+
+ ehci0: usb@01c14000 {
+ status = "okay";
+ };
+
+ ohci0: usb@01c14400 {
+ status = "okay";
+ };
+
+ ahci: sata@01c18000 {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+ };
+
+ ehci1: usb@01c1c000 {
+ status = "okay";
+ };
+
+ ohci1: usb@01c1c400 {
+ status = "okay";
+ };
+
+ pinctrl@01c20800 {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = "PH2";
+ };
+
+ led_pins_pcduino3: led_pins@0 {
+ allwinner,pins = "PH15", "PH16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ key_pins_pcduino3: key_pins@0 {
+ allwinner,pins = "PH17", "PH18", "PH19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ ir0: ir@01c21800 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_pins_a>;
+ status = "okay";
+ };
+
+ uart0: serial@01c28000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ compatible = "x-powers,axp209";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 8>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ gmac: ethernet@01c50000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_mii_a>;
+ phy = <&phy1>;
+ phy-mode = "mii";
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_pcduino3>;
+
+ tx {
+ label = "pcduino3:green:tx";
+ gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
+ };
+
+ rx {
+ label = "pcduino3:green:rx";
+ gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_pins_pcduino3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ button@0 {
+ label = "Key Back";
+ linux,code = <KEY_BACK>;
+ gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
+ };
+ button@1 {
+ label = "Key Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
+ };
+ button@2 {
+ label = "Key Menu";
+ linux,code = <KEY_MENU>;
+ gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ status = "okay";
+ };
+
+ reg_usb2_vbus: usb2-vbus {
+ status = "okay";
+ };
+
+ reg_ahci_5v: ahci-5v {
+ gpio = <&pio 7 2 0>;
+ status = "okay";
+ };
+};
--- /dev/null
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+
+ aliases {
+ ethernet0 = &gmac;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ memory {
+ reg = <0x40000000 0x80000000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+ interrupts = <0 120 4>,
+ <0 121 4>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc24M: clk@01c20050 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-osc-clk";
+ reg = <0x01c20050 0x4>;
+ clock-frequency = <24000000>;
+ clock-output-names = "osc24M";
+ };
+
+ osc32k: clk@0 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "osc32k";
+ };
+
+ pll1: clk@01c20000 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-pll1-clk";
+ reg = <0x01c20000 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll1";
+ };
+
+ pll4: clk@01c20018 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-pll4-clk";
+ reg = <0x01c20018 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll4";
+ };
+
+ pll5: clk@01c20020 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll5-clk";
+ reg = <0x01c20020 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll5_ddr", "pll5_other";
+ };
+
+ pll6: clk@01c20028 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll6-clk";
+ reg = <0x01c20028 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll6_sata", "pll6_other", "pll6";
+ };
+
+ pll8: clk@01c20040 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-pll4-clk";
+ reg = <0x01c20040 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll8";
+ };
+
+ cpu: cpu@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-cpu-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
+ clock-output-names = "cpu";
+ };
+
+ axi: axi@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-axi-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&cpu>;
+ clock-output-names = "axi";
+ };
+
+ ahb: ahb@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-ahb-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&axi>;
+ clock-output-names = "ahb";
+ };
+
+ ahb_gates: clk@01c20060 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-ahb-gates-clk";
+ reg = <0x01c20060 0x8>;
+ clocks = <&ahb>;
+ clock-output-names = "ahb_usb0", "ahb_ehci0",
+ "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
+ "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+ "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
+ "ahb_spi2", "ahb_spi3", "ahb_sata",
+ "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
+ "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
+ "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+ "ahb_de_fe1", "ahb_gmac", "ahb_mp",
+ "ahb_mali";
+ };
+
+ apb0: apb0@01c20054 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb0-clk";
+ reg = <0x01c20054 0x4>;
+ clocks = <&ahb>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01c20068 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-apb0-gates-clk";
+ reg = <0x01c20068 0x4>;
+ clocks = <&apb0>;
+ clock-output-names = "apb0_codec", "apb0_spdif",
+ "apb0_ac97", "apb0_iis0", "apb0_iis1",
+ "apb0_pio", "apb0_ir0", "apb0_ir1",
+ "apb0_iis2", "apb0_keypad";
+ };
+
+ apb1_mux: apb1_mux@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-mux-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
+ clock-output-names = "apb1_mux";
+ };
+
+ apb1: apb1@01c20058 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-apb1-clk";
+ reg = <0x01c20058 0x4>;
+ clocks = <&apb1_mux>;
+ clock-output-names = "apb1";
+ };
+
+ apb1_gates: clk@01c2006c {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun7i-a20-apb1-gates-clk";
+ reg = <0x01c2006c 0x4>;
+ clocks = <&apb1>;
+ clock-output-names = "apb1_i2c0", "apb1_i2c1",
+ "apb1_i2c2", "apb1_i2c3", "apb1_can",
+ "apb1_scr", "apb1_ps20", "apb1_ps21",
+ "apb1_i2c4", "apb1_uart0", "apb1_uart1",
+ "apb1_uart2", "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6", "apb1_uart7";
+ };
+
+ nand_clk: clk@01c20080 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20080 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "nand";
+ };
+
+ ms_clk: clk@01c20084 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20084 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ms";
+ };
+
+ mmc0_clk: clk@01c20088 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20088 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc0";
+ };
+
+ mmc1_clk: clk@01c2008c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2008c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc1";
+ };
+
+ mmc2_clk: clk@01c20090 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20090 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc2";
+ };
+
+ mmc3_clk: clk@01c20094 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20094 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "mmc3";
+ };
+
+ ts_clk: clk@01c20098 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c20098 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ts";
+ };
+
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ss";
+ };
+
+ spi0_clk: clk@01c200a0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi0";
+ };
+
+ spi1_clk: clk@01c200a4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi1";
+ };
+
+ spi2_clk: clk@01c200a8 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200a8 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi2";
+ };
+
+ pata_clk: clk@01c200ac {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200ac 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "pata";
+ };
+
+ ir0_clk: clk@01c200b0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b0 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir0";
+ };
+
+ ir1_clk: clk@01c200b4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200b4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "ir1";
+ };
+
+ usb_clk: clk@01c200cc {
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ compatible = "allwinner,sun4i-a10-usb-clk";
+ reg = <0x01c200cc 0x4>;
+ clocks = <&pll6 1>;
+ clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
+ };
+
+ spi3_clk: clk@01c200d4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c200d4 0x4>;
+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
+ clock-output-names = "spi3";
+ };
+
+ mbus_clk: clk@01c2015c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2015c 0x4>;
+ clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
+ clock-output-names = "mbus";
+ };
+
+ /*
+ * The following two are dummy clocks, placeholders used in the gmac_tx
+ * clock. The gmac driver will choose one parent depending on the PHY
+ * interface mode, using clk_set_rate auto-reparenting.
+ * The actual TX clock rate is not controlled by the gmac_tx clock.
+ */
+ mii_phy_tx_clk: clk@2 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ clock-output-names = "mii_phy_tx";
+ };
+
+ gmac_int_tx_clk: clk@3 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac_int_tx";
+ };
+
+ gmac_tx_clk: clk@01c20164 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-gmac-clk";
+ reg = <0x01c20164 0x4>;
+ clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
+ clock-output-names = "gmac_tx";
+ };
+
+ /*
+ * Dummy clock used by output clocks
+ */
+ osc24M_32k: clk@1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <750>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "osc24M_32k";
+ };
+
+ clk_out_a: clk@01c201f0 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-out-clk";
+ reg = <0x01c201f0 0x4>;
+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+ clock-output-names = "clk_out_a";
+ };
+
+ clk_out_b: clk@01c201f4 {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun7i-a20-out-clk";
+ reg = <0x01c201f4 0x4>;
+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
+ clock-output-names = "clk_out_b";
+ };
+ };
+
+ soc@01c00000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ nmi_intc: interrupt-controller@01c00030 {
+ compatible = "allwinner,sun7i-a20-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01c00030 0x0c>;
+ interrupts = <0 0 4>;
+ };
+
+ spi0: spi@01c05000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <0 10 4>;
+ clocks = <&ahb_gates 20>, <&spi0_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@01c06000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <0 11 4>;
+ clocks = <&ahb_gates 21>, <&spi1_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ emac: ethernet@01c0b000 {
+ compatible = "allwinner,sun4i-a10-emac";
+ reg = <0x01c0b000 0x1000>;
+ interrupts = <0 55 4>;
+ clocks = <&ahb_gates 17>;
+ status = "disabled";
+ };
+
+ mdio@01c0b080 {
+ compatible = "allwinner,sun4i-a10-mdio";
+ reg = <0x01c0b080 0x14>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 32 4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 33 4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 34 4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mmc";
+ interrupts = <0 35 4>;
+ status = "disabled";
+ };
+
+ usbphy: phy@01c13400 {
+ #phy-cells = <1>;
+ compatible = "allwinner,sun7i-a20-usb-phy";
+ reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
+ reg-names = "phy_ctrl", "pmu1", "pmu2";
+ clocks = <&usb_clk 8>;
+ clock-names = "usb_phy";
+ resets = <&usb_clk 1>, <&usb_clk 2>;
+ reset-names = "usb1_reset", "usb2_reset";
+ status = "disabled";
+ };
+
+ ehci0: usb@01c14000 {
+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+ reg = <0x01c14000 0x100>;
+ interrupts = <0 39 4>;
+ clocks = <&ahb_gates 1>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci0: usb@01c14400 {
+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+ reg = <0x01c14400 0x100>;
+ interrupts = <0 64 4>;
+ clocks = <&usb_clk 6>, <&ahb_gates 2>;
+ phys = <&usbphy 1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi2: spi@01c17000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <0 12 4>;
+ clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ahci: sata@01c18000 {
+ compatible = "allwinner,sun4i-a10-ahci";
+ reg = <0x01c18000 0x1000>;
+ interrupts = <0 56 4>;
+ clocks = <&pll6 0>, <&ahb_gates 25>;
+ status = "disabled";
+ };
+
+ ehci1: usb@01c1c000 {
+ compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
+ reg = <0x01c1c000 0x100>;
+ interrupts = <0 40 4>;
+ clocks = <&ahb_gates 3>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ ohci1: usb@01c1c400 {
+ compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
+ reg = <0x01c1c400 0x100>;
+ interrupts = <0 65 4>;
+ clocks = <&usb_clk 7>, <&ahb_gates 4>;
+ phys = <&usbphy 2>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ spi3: spi@01c1f000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c1f000 0x1000>;
+ interrupts = <0 50 4>;
+ clocks = <&ahb_gates 23>, <&spi3_clk>;
+ clock-names = "ahb", "mod";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pio: pinctrl@01c20800 {
+ compatible = "allwinner,sun7i-a20-pinctrl";
+ reg = <0x01c20800 0x400>;
+ interrupts = <0 28 4>;
+ clocks = <&apb0_gates 5>;
+ gpio-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #size-cells = <0>;
+ #gpio-cells = <3>;
+
+ pwm0_pins_a: pwm0@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "pwm";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ pwm1_pins_a: pwm1@0 {
+ allwinner,pins = "PI3";
+ allwinner,function = "pwm";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart0_pins_a: uart0@0 {
+ allwinner,pins = "PB22", "PB23";
+ allwinner,function = "uart0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart2_pins_a: uart2@0 {
+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+ allwinner,function = "uart2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart6_pins_a: uart6@0 {
+ allwinner,pins = "PI12", "PI13";
+ allwinner,function = "uart6";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ uart7_pins_a: uart7@0 {
+ allwinner,pins = "PI20", "PI21";
+ allwinner,function = "uart7";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c0_pins_a: i2c0@0 {
+ allwinner,pins = "PB0", "PB1";
+ allwinner,function = "i2c0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ allwinner,pins = "PB18", "PB19";
+ allwinner,function = "i2c1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ i2c2_pins_a: i2c2@0 {
+ allwinner,pins = "PB20", "PB21";
+ allwinner,function = "i2c2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ emac_pins_a: emac0@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ allwinner,function = "emac";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ clk_out_a_pins_a: clk_out_a@0 {
+ allwinner,pins = "PI12";
+ allwinner,function = "clk_out_a";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ clk_out_b_pins_a: clk_out_b@0 {
+ allwinner,pins = "PI13";
+ allwinner,function = "clk_out_b";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_mii_a: gmac_mii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA9", "PA10",
+ "PA11", "PA12", "PA13", "PA14",
+ "PA15", "PA16";
+ allwinner,function = "gmac";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ gmac_pins_rgmii_a: gmac_rgmii@0 {
+ allwinner,pins = "PA0", "PA1", "PA2",
+ "PA3", "PA4", "PA5", "PA6",
+ "PA7", "PA8", "PA10",
+ "PA11", "PA12", "PA13",
+ "PA15", "PA16";
+ allwinner,function = "gmac";
+ /*
+ * data lines in RGMII mode use DDR mode
+ * and need a higher signal drive strength
+ */
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ spi1_pins_a: spi1@0 {
+ allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+ allwinner,function = "spi1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ spi2_pins_a: spi2@0 {
+ allwinner,pins = "PC19", "PC20", "PC21", "PC22";
+ allwinner,function = "spi2";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
+ mmc3_pins_a: mmc3@0 {
+ allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+ allwinner,function = "mmc3";
+ allwinner,drive = <2>;
+ allwinner,pull = <0>;
+ };
+
+ ir0_pins_a: ir0@0 {
+ allwinner,pins = "PB3","PB4";
+ allwinner,function = "ir0";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ ir1_pins_a: ir1@0 {
+ allwinner,pins = "PB22","PB23";
+ allwinner,function = "ir1";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+
+ timer@01c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <0 22 4>,
+ <0 23 4>,
+ <0 24 4>,
+ <0 25 4>,
+ <0 67 4>,
+ <0 68 4>;
+ clocks = <&osc24M>;
+ };
+
+ wdt: watchdog@01c20c90 {
+ compatible = "allwinner,sun4i-a10-wdt";
+ reg = <0x01c20c90 0x10>;
+ };
+
+ rtc: rtc@01c20d00 {
+ compatible = "allwinner,sun7i-a20-rtc";
+ reg = <0x01c20d00 0x20>;
+ interrupts = <0 24 4>;
+ };
+
+ pwm: pwm@01c20e00 {
+ compatible = "allwinner,sun7i-a20-pwm";
+ reg = <0x01c20e00 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir0: ir@01c21800 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 6>, <&ir0_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <0 5 4>;
+ reg = <0x01c21800 0x40>;
+ status = "disabled";
+ };
+
+ ir1: ir@01c21c00 {
+ compatible = "allwinner,sun4i-a10-ir";
+ clocks = <&apb0_gates 7>, <&ir1_clk>;
+ clock-names = "apb", "ir";
+ interrupts = <0 6 4>;
+ reg = <0x01c21c00 0x40>;
+ status = "disabled";
+ };
+
+ sid: eeprom@01c23800 {
+ compatible = "allwinner,sun7i-a20-sid";
+ reg = <0x01c23800 0x200>;
+ };
+
+ rtp: rtp@01c25000 {
+ compatible = "allwinner,sun4i-a10-ts";
+ reg = <0x01c25000 0x100>;
+ interrupts = <0 29 4>;
+ };
+
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+ interrupts = <0 1 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 16>;
+ status = "disabled";
+ };
+
+ uart1: serial@01c28400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28400 0x400>;
+ interrupts = <0 2 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 17>;
+ status = "disabled";
+ };
+
+ uart2: serial@01c28800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28800 0x400>;
+ interrupts = <0 3 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 18>;
+ status = "disabled";
+ };
+
+ uart3: serial@01c28c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28c00 0x400>;
+ interrupts = <0 4 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 19>;
+ status = "disabled";
+ };
+
+ uart4: serial@01c29000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29000 0x400>;
+ interrupts = <0 17 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 20>;
+ status = "disabled";
+ };
+
+ uart5: serial@01c29400 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29400 0x400>;
+ interrupts = <0 18 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 21>;
+ status = "disabled";
+ };
+
+ uart6: serial@01c29800 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29800 0x400>;
+ interrupts = <0 19 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 22>;
+ status = "disabled";
+ };
+
+ uart7: serial@01c29c00 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c29c00 0x400>;
+ interrupts = <0 20 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&apb1_gates 23>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@01c2ac00 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2ac00 0x400>;
+ interrupts = <0 7 4>;
+ clocks = <&apb1_gates 0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@01c2b000 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b000 0x400>;
+ interrupts = <0 8 4>;
+ clocks = <&apb1_gates 1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c2: i2c@01c2b400 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b400 0x400>;
+ interrupts = <0 9 4>;
+ clocks = <&apb1_gates 2>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c3: i2c@01c2b800 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2b800 0x400>;
+ interrupts = <0 88 4>;
+ clocks = <&apb1_gates 3>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4: i2c@01c2c000 {
+ compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
+ reg = <0x01c2c000 0x400>;
+ interrupts = <0 89 4>;
+ clocks = <&apb1_gates 15>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gmac: ethernet@01c50000 {
+ compatible = "allwinner,sun7i-a20-gmac";
+ reg = <0x01c50000 0x10000>;
+ interrupts = <0 85 4>;
+ interrupt-names = "macirq";
+ clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
+ clock-names = "stmmaceth", "allwinner_gmac_tx";
+ snps,pbl = <2>;
+ snps,fixed-burst;
+ snps,force_sf_dma_mode;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ hstimer@01c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 81 4>,
+ <0 82 4>,
+ <0 83 4>,
+ <0 84 4>;
+ clocks = <&ahb_gates 28>;
+ };
+
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+ <0x01c82000 0x1000>,
+ <0x01c84000 0x2000>,
+ <0x01c86000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <1 9 0xf04>;
+ };
+ };
+};
--- /dev/null
+/*
+ * sunxi boards common regulator (ahci target power supply, usb-vbus) code
+ *
+ * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/ {
+ soc@01c00000 {
+ pio: pinctrl@01c20800 {
+ ahci_pwr_pin_a: ahci_pwr_pin@0 {
+ allwinner,pins = "PB8";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ usb1_vbus_pin_a: usb1_vbus_pin@0 {
+ allwinner,pins = "PH6";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+
+ usb2_vbus_pin_a: usb2_vbus_pin@0 {
+ allwinner,pins = "PH3";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <0>;
+ allwinner,pull = <0>;
+ };
+ };
+ };
+
+ reg_ahci_5v: ahci-5v {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ahci_pwr_pin_a>;
+ regulator-name = "ahci-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 1 8 0>;
+ status = "disabled";
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_vbus_pin_a>;
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 7 6 0>;
+ status = "disabled";
+ };
+
+ reg_usb2_vbus: usb2-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_pin_a>;
+ regulator-name = "usb2-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&pio 7 3 0>;
+ status = "disabled";
+ };
+
+ reg_vcc3v0: vcc3v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
--- /dev/null
+/*
+ * Digilent ZYBO board DTS
+ *
+ * Copyright (C) 2013 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq ZYBO Board";
+ compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x20000000>;
+ };
+};
p += stride;
}
}
+
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value)
+{
+ int i = 0;
+ u32 reg;
+ reg = readl(base + group * 4);
+ while (num_bits) {
+ reg &= ~(1<<(start_bit + i));
+ i++;
+ num_bits--;
+ }
+ reg |= (value << start_bit);
+ writel(reg, base + group * 4);
+}
#include <spl.h>
#if defined(CONFIG_MX6)
-/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
u32 spl_boot_device(void)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
- unsigned reg = readl(&psrc->sbmr1);
+ unsigned int gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
+ unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
/* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
switch ((reg & 0x000000FF) >> 4) {
#include <div64.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
/* General purpose timers registers */
struct mxc_gpt {
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
+#define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
+#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
+#define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
+#define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
+#define GPTCR_CLKSOURCE_MASK (0x7 << 6)
#define GPTCR_TEN 1 /* Timer enable */
+#define GPTPR_PRESCALER24M_SHIFT 12
+#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
+
DECLARE_GLOBAL_DATA_PTR;
+static inline int gpt_has_clk_source_osc(void)
+{
+#if defined(CONFIG_MX6)
+ if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
+ (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
+ return 1;
+
+ return 0;
+#else
+ return 0;
+#endif
+}
+
+static inline ulong gpt_get_clk(void)
+{
+#ifdef CONFIG_MXC_GPT_HCLK
+ if (gpt_has_clk_source_osc())
+ return MXC_HCLK >> 3;
+ else
+ return mxc_get_clock(MXC_IPG_PERCLK);
+#else
+ return MXC_CLK32;
+#endif
+}
static inline unsigned long long tick_to_time(unsigned long long tick)
{
+ ulong gpt_clk = gpt_get_clk();
+
tick *= CONFIG_SYS_HZ;
- do_div(tick, MXC_CLK32);
+ do_div(tick, gpt_clk);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long usec)
{
- usec = usec * MXC_CLK32 + 999999;
+ ulong gpt_clk = gpt_get_clk();
+
+ usec = usec * gpt_clk + 999999;
do_div(usec, 1000000);
return usec;
for (i = 0; i < 100; i++)
__raw_writel(0, &cur_gpt->control);
- __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
-
- /* Freerun Mode, PERCLK1 input */
i = __raw_readl(&cur_gpt->control);
- __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
+ i &= ~GPTCR_CLKSOURCE_MASK;
+
+#ifdef CONFIG_MXC_GPT_HCLK
+ if (gpt_has_clk_source_osc()) {
+ i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
+
+ /* For DL/S, SX, set 24Mhz OSC Enable bit and prescaler */
+ if (is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO) ||
+ is_cpu_type(MXC_CPU_MX6SX)) {
+ i |= GPTCR_24MEN;
+
+ /* Produce 3Mhz clock */
+ __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
+ &cur_gpt->prescaler);
+ }
+ } else {
+ i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
+ }
+#else
+ __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
+ i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+#endif
+ __raw_writel(i, &cur_gpt->control);
gd->arch.tbl = __raw_readl(&cur_gpt->counter);
gd->arch.tbu = 0;
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
- * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
*/
ulong get_tbclk(void)
{
- return MXC_CLK32;
+ return gpt_get_clk();
}
int i;
int ret;
char const *panel = getenv("panel");
+
if (!panel) {
for (i = 0; i < display_count; i++) {
struct display_info_t const *dev = displays+i;
break;
}
}
+
if (i < display_count) {
ret = ipuv3_fb_init(&displays[i].mode, 0,
displays[i].pixfmt);
if (!ret) {
- displays[i].enable(displays+i);
+ if (displays[i].enable)
+ displays[i].enable(displays + i);
+
printf("Display: %s (%ux%u)\n",
displays[i].mode.name,
displays[i].mode.xres,
#include <asm/ti-common/sys_proto.h>
#include <asm/arch/cpu.h>
-#define BOARD_REV_ID 0x0
-
u32 get_cpu_rev(void);
u32 get_sysboot_value(void);
+++ /dev/null
-/*
- * Copyright (C) 2010
- * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
- *
- * Shutdown Controller
- * Based on AT91SAM9XE datasheet
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef AT91_SHDWN_H
-#define AT91_SHDWN_H
-
-#ifndef __ASSEMBLY__
-
-struct at91_shdwn {
- u32 cr; /* Control Rer. WO */
- u32 mr; /* Mode Register RW 0x00000003 */
- u32 sr; /* Status Register RO 0x00000000 */
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define AT91_SHDW_CR_KEY 0xa5000000
-#define AT91_SHDW_CR_SHDW 0x00000001
-
-#define AT91_SHDW_MR_RTTWKEN 0x00010000
-#define AT91_SHDW_MR_CPTWK0 0x000000f0
-#define AT91_SHDW_MR_WKMODE0H2L 0x00000002
-#define AT91_SHDW_MR_WKMODE0L2H 0x00000001
-
-#define AT91_SHDW_SR_RTTWK 0x00010000
-#define AT91_SHDW_SR_WAKEUP0 0x00000001
-
-#endif
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_ACE_SFR_BASE 0x10830000
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */
+#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
#define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4X12_GPIO_PART2_0 0x11000000
+#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */
+#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */
+#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */
#define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */
+#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */
+#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */
#define EXYNOS4X12_FIMD_BASE 0x11C00000
#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
#define EXYNOS4X12_USBOTG_BASE 0x12480000
EXYNOS4_GPIO_Y65,
EXYNOS4_GPIO_Y66,
EXYNOS4_GPIO_Y67,
- EXYNOS4_GPIO_X00, /* 256 0x100 */
+
+ /* GPIO_PART2_1 STARTS */
+ EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */
+ EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0,
EXYNOS4_GPIO_X01,
EXYNOS4_GPIO_X02,
EXYNOS4_GPIO_X03,
EXYNOS4_GPIO_X37,
/* GPIO_PART3_STARTS */
- EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */
- EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2,
+ EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */
+ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1,
EXYNOS4_GPIO_Z1,
EXYNOS4_GPIO_Z2,
EXYNOS4_GPIO_Z3,
};
enum exynos4X12_gpio_pin {
- /* GPIO_PART1_STARTS */
+ /* EXYNOS4X12_GPIO_PART1_0 starts here */
EXYNOS4X12_GPIO_A00, /* 0 */
EXYNOS4X12_GPIO_A01,
EXYNOS4X12_GPIO_A02,
EXYNOS4X12_GPIO_D15,
EXYNOS4X12_GPIO_D16,
EXYNOS4X12_GPIO_D17,
- EXYNOS4X12_GPIO_F00, /* 56 0x38 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */
+ /* EXYNOS4X12_GPIO_PART1_1 starts here */
+ EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0,
EXYNOS4X12_GPIO_F01,
EXYNOS4X12_GPIO_F02,
EXYNOS4X12_GPIO_F03,
EXYNOS4X12_GPIO_F35,
EXYNOS4X12_GPIO_F36,
EXYNOS4X12_GPIO_F37,
- EXYNOS4X12_GPIO_J00, /* 88 0x58 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */
+ /* EXYNOS4X12_GPIO_PART1_2 starts here */
+ EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1,
EXYNOS4X12_GPIO_J01,
EXYNOS4X12_GPIO_J02,
EXYNOS4X12_GPIO_J03,
EXYNOS4X12_GPIO_J16,
EXYNOS4X12_GPIO_J17,
- /* GPIO_PART2_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */
- EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1,
+ /**
+ * EXYNOS4X12_GPIO_PART2_0 is not used
+ * EXYNOS4X12_GPIO_PART2_1 starts here
+ */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */
+ EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2,
EXYNOS4X12_GPIO_K01,
EXYNOS4X12_GPIO_K02,
EXYNOS4X12_GPIO_K03,
EXYNOS4X12_GPIO_Y65,
EXYNOS4X12_GPIO_Y66,
EXYNOS4X12_GPIO_Y67,
- EXYNOS4X12_GPIO_M00, /* 216 0xd8 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */
+ /* EXYNOS4X12_GPIO_PART2_2 starts here */
+ EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1,
EXYNOS4X12_GPIO_M01,
EXYNOS4X12_GPIO_M02,
EXYNOS4X12_GPIO_M03,
EXYNOS4X12_GPIO_M45,
EXYNOS4X12_GPIO_M46,
EXYNOS4X12_GPIO_M47,
- EXYNOS4X12_GPIO_X00, /* 256 0x100 */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */
+ /* EXYNOS4X12_GPIO_PART2_3 starts here */
+ EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2,
EXYNOS4X12_GPIO_X01,
EXYNOS4X12_GPIO_X02,
EXYNOS4X12_GPIO_X03,
EXYNOS4X12_GPIO_X36,
EXYNOS4X12_GPIO_X37,
- /* GPIO_PART3_STARTS */
- EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */
- EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2,
+ /* EXYNOS4X12_GPIO_PART3 starts here */
+ EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */
+ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3,
EXYNOS4X12_GPIO_Z1,
EXYNOS4X12_GPIO_Z2,
EXYNOS4X12_GPIO_Z3,
EXYNOS4X12_GPIO_Z6,
EXYNOS4X12_GPIO_Z7,
- /* GPIO_PART4_STARTS */
+ /* EXYNOS4X12_GPIO_PART4 starts here */
EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */
EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3,
EXYNOS4X12_GPIO_V01,
unsigned int max_gpio; /* Maximum GPIO in this part */
};
-#define EXYNOS4_GPIO_NUM_PARTS 3
+#define EXYNOS4_GPIO_NUM_PARTS 4
static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = {
{ EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 },
+ { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 },
{ EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT },
};
-#define EXYNOS4X12_GPIO_NUM_PARTS 4
+#define EXYNOS4X12_GPIO_NUM_PARTS 8
static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = {
- { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 },
- { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 },
+ { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 },
+ { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 },
+ { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 },
+ { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 },
+ { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 },
{ EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 },
{ EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT },
};
#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100
#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000
#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
-#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
-#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
/* NETCP */
#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00
#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000
#define KS2_NETCP_PDMA_RX_FLOW_NUM 32
-#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
-#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
#define KS2_NETCP_PDMA_TX_SND_QUEUE 648
/* NETCP */
/* OSR memory size */
#define KS2_OSR_SIZE 0x100000
+/* SGMII SerDes */
+#define KS2_SGMII_SERDES2_BASE 0x02320000
+#define KS2_LANES_PER_SGMII_SERDES 2
+
/* Number of DSP cores */
#define KS2_NUM_DSPS 4
#define KS2_NETCP_PDMA_RX_FLOW_NUM 96
#define KS2_NETCP_PDMA_TX_SND_QUEUE 896
+/* NETCP */
+#define KS2_NETCP_BASE 0x26000000
+
#endif /* __ASM_ARCH_HARDWARE_K2L_H */
#define KS2_EDMA_QEESR 0x108c
#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x))
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001
+#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002
+
/* Chip Interrupt Controller */
#define KS2_CIC2_BASE 0x02608000
u32 analog_pll_video_tog;
u32 analog_pll_video_num; /* 0x40b0 */
u32 analog_reserved6[3];
- u32 analog_pll_vedio_denon; /* 0x40c0 */
+ u32 analog_pll_video_denom; /* 0x40c0 */
u32 analog_reserved7[7];
u32 analog_pll_enet; /* 0x40e0 */
u32 analog_pll_enet_set;
#ifdef CONFIG_MX6SX
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
+#endif
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
#endif
#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
MX6_PAD_ECSPI1_SS0__GPIO4_IO11 = IOMUX_PAD(0x0364, 0x0074, 5, 0x0000, 0, 0),
+ MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x0534, 0x022C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0538, 0x0230, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 = IOMUX_PAD(0x053C, 0x0234, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 = IOMUX_PAD(0x0540, 0x0238, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 = IOMUX_PAD(0x0544, 0x023C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 = IOMUX_PAD(0x0548, 0x0240, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT4__USDHC1_DAT4 = IOMUX_PAD(0x054C, 0x0244, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT5__USDHC1_DAT5 = IOMUX_PAD(0x0550, 0x0248, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT6__USDHC1_DAT6 = IOMUX_PAD(0x0554, 0x024C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD1_DAT7__USDHC1_DAT7 = IOMUX_PAD(0x0558, 0x0250, 0, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW7__GPIO_4_7 = IOMUX_PAD(0x04B0, 0x01A8, 5, 0x0000, 0, 0),
MX6_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x055C, 0x0254, 0, 0x0000, 0, 0),
MX6_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0560, 0x0258, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT0__USDHC2_DAT0 = IOMUX_PAD(0x0564, 0x025C, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 = IOMUX_PAD(0x0568, 0x0260, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 = IOMUX_PAD(0x056C, 0x0264, 0, 0x0000, 0, 0),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 = IOMUX_PAD(0x0570, 0x0268, 0, 0x0000, 0, 0),
+ MX6_PAD_SD2_DAT7__GPIO_5_0 = IOMUX_PAD(0x0580, 0x0278, 5, 0x0000, 0, 0),
+ MX6_PAD_SD3_CLK__USDHC3_CLK = IOMUX_PAD(0x0588, 0x0280, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_CMD__USDHC3_CMD = IOMUX_PAD(0x058C, 0x0284, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 = IOMUX_PAD(0x0590, 0x0288, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 = IOMUX_PAD(0x0594, 0x028C, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 = IOMUX_PAD(0x0598, 0x0290, 0, 0x0000, 0, 0),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 = IOMUX_PAD(0x059C, 0x0294, 0, 0x0000, 0, 0),
+ MX6_PAD_REF_CLK_32K__GPIO_3_22 = IOMUX_PAD(0x0530, 0x0228, 5, 0x0000, 0, 0),
MX6_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x05A0, 0x0298, 0, 0x07FC, 0, 0),
MX6_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x05A4, 0x029C, 0, 0x0000, 0, 0),
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F000000
#define PLL0_STC_BIT 24
+#define PLLECR 0xE61500D0
+#define PLL0ST 0x100
#ifndef __ASSEMBLY__
#include <asm/types.h>
--- /dev/null
+/*
+ * Copyright (C) 2014 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SOCFPGA_GPIO_H
+#define _SOCFPGA_GPIO_H
+
+#endif /* _SOCFPGA_GPIO_H */
void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
+void socfpga_spim_enable(void);
struct socfpga_reset_manager {
u32 status;
#define RSTMGR_PERMODRST_EMAC0_LSB 0
#define RSTMGR_PERMODRST_EMAC1_LSB 1
#define RSTMGR_PERMODRST_L4WD0_LSB 6
+#define RSTMGR_PERMODRST_SPIM0_LSB 18
+#define RSTMGR_PERMODRST_SPIM1_LSB 19
#endif /* _RESET_MANAGER_H_ */
#define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
#include <asm/arch/clock_sun6i.h>
#else
#include <asm/arch/clock_sun4i.h>
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
+void clock_set_pll5(unsigned int hz);
unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
void clock_init_safe(void);
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
#define CCM_USB_CTRL_PHYGATE (0x1 << 8)
+/* These 2 are sun6i only, define them as 0 on sun4i */
+#define CCM_USB_CTRL_PHY1_CLK 0
+#define CCM_USB_CTRL_PHY2_CLK 0
#endif /* _SUNXI_CLOCK_SUN4I_H */
#define CPU_CLK_SRC_OSC24M 1
#define CPU_CLK_SRC_PLL1 2
-#define PLL1_CFG_DEFAULT 0x90011b21
+#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
+#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
+#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL1_CTRL_MAGIC (0x1 << 16)
+#define CCM_PLL1_CTRL_EN (0x1 << 31)
+
+#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0)
+#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
+#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8)
+#define CCM_PLL5_CTRL_UPD (0x1 << 20)
+#define CCM_PLL5_CTRL_EN (0x1 << 31)
#define PLL6_CFG_DEFAULT 0x90041811
#define CCM_PLL6_CTRL_K_SHIFT 4
#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
+#define AHB1_ABP1_DIV_DEFAULT 0x00002020
+
+#define AXI_GATE_OFFSET_DRAM 0
+
+#define AHB_GATE_OFFSET_USB_OHCI1 30
+#define AHB_GATE_OFFSET_USB_OHCI0 29
+#define AHB_GATE_OFFSET_USB_EHCI1 27
+#define AHB_GATE_OFFSET_USB_EHCI0 26
+#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
+#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
+#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+/* There is no global phy clk gate on sun6i, define as 0 */
+#define CCM_USB_CTRL_PHYGATE 0
+#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
+#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+
+#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
+
+#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
+#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
+#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
+#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
+
+#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
+
+#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
#define AHB_RESET_OFFSET_MMC2 10
#define AHB_RESET_OFFSET_MMC1 9
#define SUNXI_MMC1_BASE 0x01c10000
#define SUNXI_MMC2_BASE 0x01c11000
#define SUNXI_MMC3_BASE 0x01c12000
+#ifndef CONFIG_MACH_SUN6I
#define SUNXI_USB0_BASE 0x01c13000
#define SUNXI_USB1_BASE 0x01c14000
+#endif
#define SUNXI_SS_BASE 0x01c15000
#define SUNXI_HDMI_BASE 0x01c16000
#define SUNXI_SPI2_BASE 0x01c17000
#define SUNXI_SATA_BASE 0x01c18000
+#ifndef CONFIG_MACH_SUN6I
#define SUNXI_PATA_BASE 0x01c19000
#define SUNXI_ACE_BASE 0x01c1a000
#define SUNXI_TVE1_BASE 0x01c1b000
#define SUNXI_USB2_BASE 0x01c1c000
+#else
+#define SUNXI_USB0_BASE 0x01c19000
+#define SUNXI_USB1_BASE 0x01c1a000
+#define SUNXI_USB2_BASE 0x01c1b000
+#endif
#define SUNXI_CSI1_BASE 0x01c1d000
#define SUNXI_TZASC_BASE 0x01c1e000
#define SUNXI_SPI3_BASE 0x01c1f000
#define SUNXI_TP_BASE 0x01c25000
#define SUNXI_PMU_BASE 0x01c25400
-#define SUNXI_CPUCFG_BASE 0x01c25c00
+#define SUN7I_CPUCFG_BASE 0x01c25c00
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_GMAC_BASE 0x01c50000
#define SUNXI_DRAM_COM_BASE 0x01c62000
-#define SUNXI_DRAM_CTL_BASE 0x01c63000
-#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000
-#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000
+#define SUNXI_DRAM_CTL0_BASE 0x01c63000
+#define SUNXI_DRAM_CTL1_BASE 0x01c64000
+#define SUNXI_DRAM_PHY0_BASE 0x01c65000
+#define SUNXI_DRAM_PHY1_BASE 0x01c66000
/* module sram */
#define SUNXI_SRAM_C_BASE 0x01d00000
#define SUNXI_MP_BASE 0x01e80000
#define SUNXI_AVG_BASE 0x01ea0000
+#define SUNXI_RTC_BASE 0x01f00000
#define SUNXI_PRCM_BASE 0x01f01400
+#define SUN6I_CPUCFG_BASE 0x01f01c00
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUNXI_P2WI_BASE 0x01f03400
--- /dev/null
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPUCFG_H
+#define _SUNXI_CPUCFG_H
+
+#ifndef __ASSEMBLY__
+
+struct sunxi_cpucfg_reg {
+ u8 res0[0x40]; /* 0x000 */
+ u32 cpu0_rst; /* 0x040 */
+ u32 cpu0_ctrl; /* 0x044 */
+ u32 cpu0_status; /* 0x048 */
+ u8 res1[0x34]; /* 0x04c */
+ u32 cpu1_rst; /* 0x080 */
+ u32 cpu1_ctrl; /* 0x084 */
+ u32 cpu1_status; /* 0x088 */
+ u8 res2[0x34]; /* 0x08c */
+ u32 cpu2_rst; /* 0x0c0 */
+ u32 cpu2_ctrl; /* 0x0c4 */
+ u32 cpu2_status; /* 0x0c8 */
+ u8 res3[0x34]; /* 0x0cc */
+ u32 cpu3_rst; /* 0x100 */
+ u32 cpu3_ctrl; /* 0x104 */
+ u32 cpu3_status; /* 0x108 */
+ u8 res4[0x78]; /* 0x10c */
+ u32 gen_ctrl; /* 0x184 */
+ u32 l2_status; /* 0x188 */
+ u8 res5[0x4]; /* 0x18c */
+ u32 event_in; /* 0x190 */
+ u8 res6[0xc]; /* 0x194 */
+ u32 super_standy_flag; /* 0x1a0 */
+ u32 priv0; /* 0x1a4 */
+ u32 priv1; /* 0x1a8 */
+ u8 res7[0x54]; /* 0x1ac */
+ u32 idle_cnt0_low; /* 0x200 */
+ u32 idle_cnt0_high; /* 0x204 */
+ u32 idle_cnt0_ctrl; /* 0x208 */
+ u8 res8[0x4]; /* 0x20c */
+ u32 idle_cnt1_low; /* 0x210 */
+ u32 idle_cnt1_high; /* 0x214 */
+ u32 idle_cnt1_ctrl; /* 0x218 */
+ u8 res9[0x4]; /* 0x21c */
+ u32 idle_cnt2_low; /* 0x220 */
+ u32 idle_cnt2_high; /* 0x224 */
+ u32 idle_cnt2_ctrl; /* 0x228 */
+ u8 res10[0x4]; /* 0x22c */
+ u32 idle_cnt3_low; /* 0x230 */
+ u32 idle_cnt3_high; /* 0x234 */
+ u32 idle_cnt3_ctrl; /* 0x238 */
+ u8 res11[0x4]; /* 0x23c */
+ u32 idle_cnt4_low; /* 0x240 */
+ u32 idle_cnt4_high; /* 0x244 */
+ u32 idle_cnt4_ctrl; /* 0x248 */
+ u8 res12[0x34]; /* 0x24c */
+ u32 cnt64_ctrl; /* 0x280 */
+ u32 cnt64_low; /* 0x284 */
+ u32 cnt64_high; /* 0x288 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_H */
#include <linux/types.h>
-struct sunxi_dram_reg {
- u32 ccr; /* 0x00 controller configuration register */
- u32 dcr; /* 0x04 dram configuration register */
- u32 iocr; /* 0x08 i/o configuration register */
- u32 csr; /* 0x0c controller status register */
- u32 drr; /* 0x10 dram refresh register */
- u32 tpr0; /* 0x14 dram timing parameters register 0 */
- u32 tpr1; /* 0x18 dram timing parameters register 1 */
- u32 tpr2; /* 0x1c dram timing parameters register 2 */
- u32 gdllcr; /* 0x20 global dll control register */
- u8 res0[0x28];
- u32 rslr0; /* 0x4c rank system latency register */
- u32 rslr1; /* 0x50 rank system latency register */
- u8 res1[0x8];
- u32 rdgr0; /* 0x5c rank dqs gating register */
- u32 rdgr1; /* 0x60 rank dqs gating register */
- u8 res2[0x34];
- u32 odtcr; /* 0x98 odt configuration register */
- u32 dtr0; /* 0x9c data training register 0 */
- u32 dtr1; /* 0xa0 data training register 1 */
- u32 dtar; /* 0xa4 data training address register */
- u32 zqcr0; /* 0xa8 zq control register 0 */
- u32 zqcr1; /* 0xac zq control register 1 */
- u32 zqsr; /* 0xb0 zq status register */
- u32 idcr; /* 0xb4 initializaton delay configure reg */
- u8 res3[0x138];
- u32 mr; /* 0x1f0 mode register */
- u32 emr; /* 0x1f4 extended mode register */
- u32 emr2; /* 0x1f8 extended mode register */
- u32 emr3; /* 0x1fc extended mode register */
- u32 dllctr; /* 0x200 dll control register */
- u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
- /* 0x208 dll control register 1(byte 1) */
- /* 0x20c dll control register 2(byte 2) */
- /* 0x210 dll control register 3(byte 3) */
- /* 0x214 dll control register 4(byte 4) */
- u32 dqtr0; /* 0x218 dq timing register */
- u32 dqtr1; /* 0x21c dq timing register */
- u32 dqtr2; /* 0x220 dq timing register */
- u32 dqtr3; /* 0x224 dq timing register */
- u32 dqstr; /* 0x228 dqs timing register */
- u32 dqsbtr; /* 0x22c dqsb timing register */
- u32 mcr; /* 0x230 mode configure register */
- u8 res[0x8];
- u32 ppwrsctl; /* 0x23c pad power save control */
- u32 apr; /* 0x240 arbiter period register */
- u32 pldtr; /* 0x244 priority level data threshold reg */
- u8 res5[0x8];
- u32 hpcr[32]; /* 0x250 host port configure register */
- u8 res6[0x10];
- u32 csel; /* 0x2e0 controller select register */
-};
-
-struct dram_para {
- u32 clock;
- u32 mbus_clock;
- u32 type;
- u32 rank_num;
- u32 density;
- u32 io_width;
- u32 bus_width;
- u32 cas;
- u32 zq;
- u32 odt_en;
- u32 size;
- u32 tpr0;
- u32 tpr1;
- u32 tpr2;
- u32 tpr3;
- u32 tpr4;
- u32 tpr5;
- u32 emr1;
- u32 emr2;
- u32 emr3;
- u32 dqs_gating_delay;
- u32 active_windowing;
-};
-
-#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
-#define DRAM_CCR_DQS_GATE (0x1 << 14)
-#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
-#define DRAM_CCR_ITM_OFF (0x1 << 28)
-#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
-#define DRAM_CCR_INIT (0x1 << 31)
-
-#define DRAM_MEMORY_TYPE_DDR1 1
-#define DRAM_MEMORY_TYPE_DDR2 2
-#define DRAM_MEMORY_TYPE_DDR3 3
-#define DRAM_MEMORY_TYPE_LPDDR2 4
-#define DRAM_MEMORY_TYPE_LPDDR 5
-#define DRAM_DCR_TYPE (0x1 << 0)
-#define DRAM_DCR_TYPE_DDR2 0x0
-#define DRAM_DCR_TYPE_DDR3 0x1
-#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
-#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
-#define DRAM_DCR_IO_WIDTH_8BIT 0x0
-#define DRAM_DCR_IO_WIDTH_16BIT 0x1
-#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
-#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
-#define DRAM_DCR_CHIP_DENSITY_256M 0x0
-#define DRAM_DCR_CHIP_DENSITY_512M 0x1
-#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
-#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
-#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
-#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
-#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
-#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
-#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
-#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
-#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
-#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
-#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
-#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
-#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
-#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
-#define DRAM_DCR_MODE_SEQ 0x0
-#define DRAM_DCR_MODE_INTERLEAVE 0x1
-
-#define DRAM_CSR_DTERR (0x1 << 20)
-#define DRAM_CSR_DTIERR (0x1 << 21)
-#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
-
-#define DRAM_DRR_TRFC(n) ((n) & 0xff)
-#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
-#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
-
-#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
-#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
-#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
-#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
-#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
-#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
-#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
-#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
-#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
-#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
-#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
-#define DRAM_MCR_RESET (0x1 << 12)
-#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
-#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
-#define DRAM_MCR_DCLK_OUT (0x1 << 16)
-
-#define DRAM_DLLCR_NRESET (0x1 << 30)
-#define DRAM_DLLCR_DISABLE (0x1 << 31)
-
-#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
-#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
-#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
-#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
-
-#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
-
-#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
-#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
-
-#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
-#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
-#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
-#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
-#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
-#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
-#define DRAM_MR_POWER_DOWN (0x1 << 12)
-
-#define DRAM_CSEL_MAGIC 0x16237495
+/* dram regs definition */
+#if defined(CONFIG_MACH_SUN6I)
+#include <asm/arch/dram_sun6i.h>
+#else
+#include <asm/arch/dram_sun4i.h>
+#endif
unsigned long sunxi_dram_init(void);
-unsigned long dramc_init(struct dram_para *para);
#endif /* _SUNXI_DRAM_H */
--- /dev/null
+/*
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * Sunxi platform dram register definition.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN4I_H
+#define _SUNXI_DRAM_SUN4I_H
+
+struct sunxi_dram_reg {
+ u32 ccr; /* 0x00 controller configuration register */
+ u32 dcr; /* 0x04 dram configuration register */
+ u32 iocr; /* 0x08 i/o configuration register */
+ u32 csr; /* 0x0c controller status register */
+ u32 drr; /* 0x10 dram refresh register */
+ u32 tpr0; /* 0x14 dram timing parameters register 0 */
+ u32 tpr1; /* 0x18 dram timing parameters register 1 */
+ u32 tpr2; /* 0x1c dram timing parameters register 2 */
+ u32 gdllcr; /* 0x20 global dll control register */
+ u8 res0[0x28];
+ u32 rslr0; /* 0x4c rank system latency register */
+ u32 rslr1; /* 0x50 rank system latency register */
+ u8 res1[0x8];
+ u32 rdgr0; /* 0x5c rank dqs gating register */
+ u32 rdgr1; /* 0x60 rank dqs gating register */
+ u8 res2[0x34];
+ u32 odtcr; /* 0x98 odt configuration register */
+ u32 dtr0; /* 0x9c data training register 0 */
+ u32 dtr1; /* 0xa0 data training register 1 */
+ u32 dtar; /* 0xa4 data training address register */
+ u32 zqcr0; /* 0xa8 zq control register 0 */
+ u32 zqcr1; /* 0xac zq control register 1 */
+ u32 zqsr; /* 0xb0 zq status register */
+ u32 idcr; /* 0xb4 initializaton delay configure reg */
+ u8 res3[0x138];
+ u32 mr; /* 0x1f0 mode register */
+ u32 emr; /* 0x1f4 extended mode register */
+ u32 emr2; /* 0x1f8 extended mode register */
+ u32 emr3; /* 0x1fc extended mode register */
+ u32 dllctr; /* 0x200 dll control register */
+ u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
+ /* 0x208 dll control register 1(byte 1) */
+ /* 0x20c dll control register 2(byte 2) */
+ /* 0x210 dll control register 3(byte 3) */
+ /* 0x214 dll control register 4(byte 4) */
+ u32 dqtr0; /* 0x218 dq timing register */
+ u32 dqtr1; /* 0x21c dq timing register */
+ u32 dqtr2; /* 0x220 dq timing register */
+ u32 dqtr3; /* 0x224 dq timing register */
+ u32 dqstr; /* 0x228 dqs timing register */
+ u32 dqsbtr; /* 0x22c dqsb timing register */
+ u32 mcr; /* 0x230 mode configure register */
+ u8 res[0x8];
+ u32 ppwrsctl; /* 0x23c pad power save control */
+ u32 apr; /* 0x240 arbiter period register */
+ u32 pldtr; /* 0x244 priority level data threshold reg */
+ u8 res5[0x8];
+ u32 hpcr[32]; /* 0x250 host port configure register */
+ u8 res6[0x10];
+ u32 csel; /* 0x2e0 controller select register */
+};
+
+struct dram_para {
+ u32 clock;
+ u32 mbus_clock;
+ u32 type;
+ u32 rank_num;
+ u32 density;
+ u32 io_width;
+ u32 bus_width;
+ u32 cas;
+ u32 zq;
+ u32 odt_en;
+ u32 size;
+ u32 tpr0;
+ u32 tpr1;
+ u32 tpr2;
+ u32 tpr3;
+ u32 tpr4;
+ u32 tpr5;
+ u32 emr1;
+ u32 emr2;
+ u32 emr3;
+ u32 dqs_gating_delay;
+ u32 active_windowing;
+};
+
+#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
+#define DRAM_CCR_DQS_GATE (0x1 << 14)
+#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
+#define DRAM_CCR_ITM_OFF (0x1 << 28)
+#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
+#define DRAM_CCR_INIT (0x1 << 31)
+
+#define DRAM_MEMORY_TYPE_DDR1 1
+#define DRAM_MEMORY_TYPE_DDR2 2
+#define DRAM_MEMORY_TYPE_DDR3 3
+#define DRAM_MEMORY_TYPE_LPDDR2 4
+#define DRAM_MEMORY_TYPE_LPDDR 5
+#define DRAM_DCR_TYPE (0x1 << 0)
+#define DRAM_DCR_TYPE_DDR2 0x0
+#define DRAM_DCR_TYPE_DDR3 0x1
+#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
+#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
+#define DRAM_DCR_IO_WIDTH_8BIT 0x0
+#define DRAM_DCR_IO_WIDTH_16BIT 0x1
+#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
+#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
+#define DRAM_DCR_CHIP_DENSITY_256M 0x0
+#define DRAM_DCR_CHIP_DENSITY_512M 0x1
+#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
+#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
+#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
+#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
+#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
+#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
+#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
+#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
+#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
+#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
+#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
+#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
+#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
+#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
+#define DRAM_DCR_MODE_SEQ 0x0
+#define DRAM_DCR_MODE_INTERLEAVE 0x1
+
+#define DRAM_CSR_DTERR (0x1 << 20)
+#define DRAM_CSR_DTIERR (0x1 << 21)
+#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
+
+#define DRAM_DRR_TRFC(n) ((n) & 0xff)
+#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
+#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
+
+#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
+#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
+#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
+#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
+#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
+#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
+#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
+#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
+#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
+#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
+#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
+#define DRAM_MCR_RESET (0x1 << 12)
+#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
+#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
+#define DRAM_MCR_DCLK_OUT (0x1 << 16)
+
+#define DRAM_DLLCR_NRESET (0x1 << 30)
+#define DRAM_DLLCR_DISABLE (0x1 << 31)
+
+#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
+#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
+#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
+#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
+
+#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
+
+#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
+#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
+
+#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
+#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
+#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
+#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
+#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
+#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
+#define DRAM_MR_POWER_DOWN (0x1 << 12)
+
+#define DRAM_CSEL_MAGIC 0x16237495
+
+unsigned long dramc_init(struct dram_para *para);
+
+#endif /* _SUNXI_DRAM_SUN4I_H */
--- /dev/null
+/*
+ * Sun6i platform dram controller register and constant defines
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_DRAM_SUN6I_H
+#define _SUNXI_DRAM_SUN6I_H
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x00 */
+ u32 ccr; /* 0x04 controller configuration register */
+ u32 dbgcr; /* 0x08 */
+ u32 dbgcr1; /* 0x0c */
+ u32 rmcr[8]; /* 0x10 */
+ u32 mmcr[16]; /* 0x30 */
+ u32 mbagcr[6]; /* 0x70 */
+ u32 maer; /* 0x88 */
+ u8 res0[0x14]; /* 0x8c */
+ u32 mdfscr; /* 0x100 */
+ u32 mdfsmer; /* 0x104 */
+ u32 mdfsmrmr; /* 0x108 */
+ u32 mdfstr0; /* 0x10c */
+ u32 mdfstr1; /* 0x110 */
+ u32 mdfstr2; /* 0x114 */
+ u32 mdfstr3; /* 0x118 */
+ u32 mdfsgcr; /* 0x11c */
+ u8 res1[0x1c]; /* 0x120 */
+ u32 mdfsivr; /* 0x13c */
+ u8 res2[0x0c]; /* 0x140 */
+ u32 mdfstcr; /* 0x14c */
+};
+
+struct sunxi_mctl_ctl_reg {
+ u8 res0[0x04]; /* 0x00 */
+ u32 sctl; /* 0x04 */
+ u32 sstat; /* 0x08 */
+ u8 res1[0x34]; /* 0x0c */
+ u32 mcmd; /* 0x40 */
+ u8 res2[0x08]; /* 0x44 */
+ u32 cmdstat; /* 0x4c */
+ u32 cmdstaten; /* 0x50 */
+ u8 res3[0x0c]; /* 0x54 */
+ u32 mrrcfg0; /* 0x60 */
+ u32 mrrstat0; /* 0x64 */
+ u32 mrrstat1; /* 0x68 */
+ u8 res4[0x10]; /* 0x6c */
+ u32 mcfg1; /* 0x7c */
+ u32 mcfg; /* 0x80 */
+ u32 ppcfg; /* 0x84 */
+ u32 mstat; /* 0x88 */
+ u32 lp2zqcfg; /* 0x8c */
+ u8 res5[0x04]; /* 0x90 */
+ u32 dtustat; /* 0x94 */
+ u32 dtuna; /* 0x98 */
+ u32 dtune; /* 0x9c */
+ u32 dtuprd0; /* 0xa0 */
+ u32 dtuprd1; /* 0xa4 */
+ u32 dtuprd2; /* 0xa8 */
+ u32 dtuprd3; /* 0xac */
+ u32 dtuawdt; /* 0xb0 */
+ u8 res6[0x0c]; /* 0xb4 */
+ u32 togcnt1u; /* 0xc0 */
+ u8 res7[0x08]; /* 0xc4 */
+ u32 togcnt100n; /* 0xcc */
+ u32 trefi; /* 0xd0 */
+ u32 tmrd; /* 0xd4 */
+ u32 trfc; /* 0xd8 */
+ u32 trp; /* 0xdc */
+ u32 trtw; /* 0xe0 */
+ u32 tal; /* 0xe4 */
+ u32 tcl; /* 0xe8 */
+ u32 tcwl; /* 0xec */
+ u32 tras; /* 0xf0 */
+ u32 trc; /* 0xf4 */
+ u32 trcd; /* 0xf8 */
+ u32 trrd; /* 0xfc */
+ u32 trtp; /* 0x100 */
+ u32 twr; /* 0x104 */
+ u32 twtr; /* 0x108 */
+ u32 texsr; /* 0x10c */
+ u32 txp; /* 0x110 */
+ u32 txpdll; /* 0x114 */
+ u32 tzqcs; /* 0x118 */
+ u32 tzqcsi; /* 0x11c */
+ u32 tdqs; /* 0x120 */
+ u32 tcksre; /* 0x124 */
+ u32 tcksrx; /* 0x128 */
+ u32 tcke; /* 0x12c */
+ u32 tmod; /* 0x130 */
+ u32 trstl; /* 0x134 */
+ u32 tzqcl; /* 0x138 */
+ u32 tmrr; /* 0x13c */
+ u32 tckesr; /* 0x140 */
+ u32 tdpd; /* 0x144 */
+ u8 res8[0xb8]; /* 0x148 */
+ u32 dtuwactl; /* 0x200 */
+ u32 dturactl; /* 0x204 */
+ u32 dtucfg; /* 0x208 */
+ u32 dtuectl; /* 0x20c */
+ u32 dtuwd0; /* 0x210 */
+ u32 dtuwd1; /* 0x214 */
+ u32 dtuwd2; /* 0x218 */
+ u32 dtuwd3; /* 0x21c */
+ u32 dtuwdm; /* 0x220 */
+ u32 dturd0; /* 0x224 */
+ u32 dturd1; /* 0x228 */
+ u32 dturd2; /* 0x22c */
+ u32 dturd3; /* 0x230 */
+ u32 dtulfsrwd; /* 0x234 */
+ u32 dtulfsrrd; /* 0x238 */
+ u32 dtueaf; /* 0x23c */
+ u32 dfitctldly; /* 0x240 */
+ u32 dfiodtcfg; /* 0x244 */
+ u32 dfiodtcfg1; /* 0x248 */
+ u32 dfiodtrmap; /* 0x24c */
+ u32 dfitphywrd; /* 0x250 */
+ u32 dfitphywrl; /* 0x254 */
+ u8 res9[0x08]; /* 0x258 */
+ u32 dfitrdden; /* 0x260 */
+ u32 dfitphyrdl; /* 0x264 */
+ u8 res10[0x08]; /* 0x268 */
+ u32 dfitphyupdtype0; /* 0x270 */
+ u32 dfitphyupdtype1; /* 0x274 */
+ u32 dfitphyupdtype2; /* 0x278 */
+ u32 dfitphyupdtype3; /* 0x27c */
+ u32 dfitctrlupdmin; /* 0x280 */
+ u32 dfitctrlupdmax; /* 0x284 */
+ u32 dfitctrlupddly; /* 0x288 */
+ u8 res11[4]; /* 0x28c */
+ u32 dfiupdcfg; /* 0x290 */
+ u32 dfitrefmski; /* 0x294 */
+ u32 dfitcrlupdi; /* 0x298 */
+ u8 res12[0x10]; /* 0x29c */
+ u32 dfitrcfg0; /* 0x2ac */
+ u32 dfitrstat0; /* 0x2b0 */
+ u32 dfitrwrlvlen; /* 0x2b4 */
+ u32 dfitrrdlvlen; /* 0x2b8 */
+ u32 dfitrrdlvlgateen; /* 0x2bc */
+ u8 res13[0x04]; /* 0x2c0 */
+ u32 dfistcfg0; /* 0x2c4 */
+ u32 dfistcfg1; /* 0x2c8 */
+ u8 res14[0x04]; /* 0x2cc */
+ u32 dfitdramclken; /* 0x2d0 */
+ u32 dfitdramclkdis; /* 0x2d4 */
+ u8 res15[0x18]; /* 0x2d8 */
+ u32 dfilpcfg0; /* 0x2f0 */
+};
+
+struct sunxi_mctl_phy_reg {
+ u8 res0[0x04]; /* 0x00 */
+ u32 pir; /* 0x04 */
+ u32 pgcr; /* 0x08 phy general configuration register */
+ u32 pgsr; /* 0x0c */
+ u32 dllgcr; /* 0x10 */
+ u32 acdllcr; /* 0x14 */
+ u32 ptr0; /* 0x18 */
+ u32 ptr1; /* 0x1c */
+ u32 ptr2; /* 0x20 */
+ u32 aciocr; /* 0x24 */
+ u32 dxccr; /* 0x28 DATX8 common configuration register */
+ u32 dsgcr; /* 0x2c dram system general config register */
+ u32 dcr; /* 0x30 */
+ u32 dtpr0; /* 0x34 dram timing parameters register 0 */
+ u32 dtpr1; /* 0x38 dram timing parameters register 1 */
+ u32 dtpr2; /* 0x3c dram timing parameters register 2 */
+ u32 mr0; /* 0x40 mode register 0 */
+ u32 mr1; /* 0x44 mode register 1 */
+ u32 mr2; /* 0x48 mode register 2 */
+ u32 mr3; /* 0x4c mode register 3 */
+ u32 odtcr; /* 0x50 */
+ u32 dtar; /* 0x54 data training address register */
+ u32 dtd0; /* 0x58 */
+ u32 dtd1; /* 0x5c */
+ u8 res1[0x60]; /* 0x60 */
+ u32 dcuar; /* 0xc0 */
+ u32 dcudr; /* 0xc4 */
+ u32 dcurr; /* 0xc8 */
+ u32 dculr; /* 0xcc */
+ u32 dcugcr; /* 0xd0 */
+ u32 dcutpr; /* 0xd4 */
+ u32 dcusr0; /* 0xd8 */
+ u32 dcusr1; /* 0xdc */
+ u8 res2[0x20]; /* 0xe0 */
+ u32 bistrr; /* 0x100 */
+ u32 bistmskr0; /* 0x104 */
+ u32 bistmskr1; /* 0x108 */
+ u32 bistwcr; /* 0x10c */
+ u32 bistlsr; /* 0x110 */
+ u32 bistar0; /* 0x114 */
+ u32 bistar1; /* 0x118 */
+ u32 bistar2; /* 0x11c */
+ u32 bistupdr; /* 0x120 */
+ u32 bistgsr; /* 0x124 */
+ u32 bistwer; /* 0x128 */
+ u32 bistber0; /* 0x12c */
+ u32 bistber1; /* 0x130 */
+ u32 bistber2; /* 0x134 */
+ u32 bistwcsr; /* 0x138 */
+ u32 bistfwr0; /* 0x13c */
+ u32 bistfwr1; /* 0x140 */
+ u8 res3[0x3c]; /* 0x144 */
+ u32 zq0cr0; /* 0x180 zq 0 control register 0 */
+ u32 zq0cr1; /* 0x184 zq 0 control register 1 */
+ u32 zq0sr0; /* 0x188 zq 0 status register 0 */
+ u32 zq0sr1; /* 0x18c zq 0 status register 1 */
+ u8 res4[0x30]; /* 0x190 */
+ u32 dx0gcr; /* 0x1c0 */
+ u32 dx0gsr0; /* 0x1c4 */
+ u32 dx0gsr1; /* 0x1c8 */
+ u32 dx0dllcr; /* 0x1cc */
+ u32 dx0dqtr; /* 0x1d0 */
+ u32 dx0dqstr; /* 0x1d4 */
+ u8 res5[0x28]; /* 0x1d8 */
+ u32 dx1gcr; /* 0x200 */
+ u32 dx1gsr0; /* 0x204 */
+ u32 dx1gsr1; /* 0x208 */
+ u32 dx1dllcr; /* 0x20c */
+ u32 dx1dqtr; /* 0x210 */
+ u32 dx1dqstr; /* 0x214 */
+ u8 res6[0x28]; /* 0x218 */
+ u32 dx2gcr; /* 0x240 */
+ u32 dx2gsr0; /* 0x244 */
+ u32 dx2gsr1; /* 0x248 */
+ u32 dx2dllcr; /* 0x24c */
+ u32 dx2dqtr; /* 0x250 */
+ u32 dx2dqstr; /* 0x254 */
+ u8 res7[0x28]; /* 0x258 */
+ u32 dx3gcr; /* 0x280 */
+ u32 dx3gsr0; /* 0x284 */
+ u32 dx3gsr1; /* 0x288 */
+ u32 dx3dllcr; /* 0x28c */
+ u32 dx3dqtr; /* 0x290 */
+ u32 dx3dqstr; /* 0x294 */
+};
+
+/*
+ * DRAM common (sunxi_mctl_com_reg) register constants.
+ */
+#define MCTL_CR_RANK_MASK (3 << 0)
+#define MCTL_CR_RANK(x) (((x) - 1) << 0)
+#define MCTL_CR_BANK_MASK (3 << 2)
+#define MCTL_CR_BANK(x) ((x) << 2)
+#define MCTL_CR_ROW_MASK (0xf << 4)
+#define MCTL_CR_ROW(x) (((x) - 1) << 4)
+#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8)
+#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
+#define MCTL_CR_BUSW_MASK (3 << 12)
+#define MCTL_CR_BUSW16 (1 << 12)
+#define MCTL_CR_BUSW32 (3 << 12)
+#define MCTL_CR_SEQUENCE (1 << 15)
+#define MCTL_CR_DDR3 (3 << 16)
+#define MCTL_CR_CHANNEL_MASK (1 << 19)
+#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19)
+#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20))
+#define MCTL_CCR_CH0_CLK_EN (1 << 0)
+#define MCTL_CCR_CH1_CLK_EN (1 << 1)
+#define MCTL_CCR_MASTER_CLK_EN (1 << 2)
+
+/*
+ * DRAM control (sunxi_mctl_ctl_reg) register constants.
+ * Note that we use constant values for a lot of the timings, this is what
+ * the original boot0 bootloader does.
+ */
+#define MCTL_SCTL_CONFIG 1
+#define MCTL_SCTL_ACCESS 2
+#define MCTL_MCMD_NOP 0x88000000
+#define MCTL_MCMD_BUSY 0x80000000
+#define MCTL_MCFG_DDR3 0x70061
+#define MCTL_TREFI 78
+#define MCTL_TMRD 4
+#define MCTL_TRFC 115
+#define MCTL_TRP 9
+#define MCTL_TPREA 0
+#define MCTL_TRTW 2
+#define MCTL_TAL 0
+#define MCTL_TCL 9
+#define MCTL_TCWL 8
+#define MCTL_TRAS 18
+#define MCTL_TRC 23
+#define MCTL_TRCD 9
+#define MCTL_TRRD 4
+#define MCTL_TRTP 4
+#define MCTL_TWR 8
+#define MCTL_TWTR 4
+#define MCTL_TEXSR 512
+#define MCTL_TXP 4
+#define MCTL_TXPDLL 14
+#define MCTL_TZQCS 64
+#define MCTL_TZQCSI 0
+#define MCTL_TDQS 1
+#define MCTL_TCKSRE 5
+#define MCTL_TCKSRX 5
+#define MCTL_TCKE 4
+#define MCTL_TMOD 12
+#define MCTL_TRSTL 80
+#define MCTL_TZQCL 512
+#define MCTL_TMRR 2
+#define MCTL_TCKESR 5
+#define MCTL_TDPD 0
+#define MCTL_DFITPHYRDL 15
+#define MCTL_DFIUPDCFG_UPD (1 << 1)
+#define MCTL_DFISTCFG0 5
+
+/*
+ * DRAM phy (sunxi_mctl_phy_reg) register values / constants.
+ */
+#define MCTL_PIR_CLEAR_STATUS (1 << 28)
+#define MCTL_PIR_STEP1 0xe9
+#define MCTL_PIR_STEP2 0x81
+#define MCTL_PGCR_RANK (1 << 19)
+#define MCTL_PGCR 0x018c0202
+#define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5)
+/* constants for both acdllcr as well as dx#dllcr */
+#define MCTL_DLLCR_NRESET (1 << 30)
+#define MCTL_DLLCR_DISABLE (1 << 31)
+/* ptr constants these are or-ed together to get the final ptr# values */
+#define MCTL_TITMSRST 10
+#define MCTL_TDLLLOCK 2250
+#define MCTL_TDLLSRST 23
+#define MCTL_TDINIT0 217000
+#define MCTL_TDINIT1 160
+#define MCTL_TDINIT2 87000
+#define MCTL_TDINIT3 433
+/* end ptr constants */
+#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3))
+#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2))
+#define MCTL_DXCCR 0x800
+#define MCTL_DSGCR_ENABLE (1 << 28)
+#define MCTL_DSGCR 0xf200001b
+#define MCTL_DCR_DDR3 0x0b
+/* dtpr constants these are or-ed together to get the final dtpr# values */
+#define MCTL_TCCD 0
+#define MCTL_TDQSCKMAX 1
+#define MCTL_TDQSCK 1
+#define MCTL_TRTODT 0
+#define MCTL_TFAW 20
+#define MCTL_TAOND 0
+#define MCTL_TDLLK 512
+/* end dtpr constants */
+#define MCTL_MR0 0x1a50
+#define MCTL_MR1 0x4
+#define MCTL_MR2 ((MCTL_TCWL - 5) << 3)
+#define MCTL_MR3 0x0
+#define MCTL_DX_GCR_EN (1 << 0)
+#define MCTL_DX_GCR 0x880
+#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0)
+#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1)
+#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4)
+#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5)
+
+#endif /* _SUNXI_DRAM_SUN6I_H */
#define SUNXI_GPF2_SDC0 2
-#ifdef CONFIG_SUN8I
+#ifdef CONFIG_MACH_SUN8I
#define SUNXI_GPF2_UART0_TX 3
#define SUNXI_GPF4_UART0_RX 3
#else
#define SUN4I_GPI4_SDC3 2
+#define SUNXI_GPL0_R_P2WI_SCK 3
+#define SUNXI_GPL1_R_P2WI_SDA 3
+
#define SUN8I_GPL2_R_UART_TX 2
#define SUN8I_GPL3_R_UART_RX 2
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
-int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
+void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
int sunxi_gpio_get_cfgpin(u32 pin);
int sunxi_gpio_set_drv(u32 pin, u32 val);
int sunxi_gpio_set_pull(u32 pin, u32 val);
u32 chda; /* 0x90 */
u32 cbda; /* 0x94 */
u32 res1[26];
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
u32 res2[64];
#endif
u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */
--- /dev/null
+/*
+ * Sunxi platform Push-Push i2c register definition.
+ *
+ * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ * http://linux-sunxi.org
+ *
+ * (c)Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Berg Xing <bergxing@allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SUNXI_P2WI_H
+#define _SUNXI_P2WI_H
+
+#include <linux/types.h>
+
+#define P2WI_CTRL_RESET (0x1 << 0)
+#define P2WI_CTRL_IRQ_EN (0x1 << 1)
+#define P2WI_CTRL_TRANS_ABORT (0x1 << 6)
+#define P2WI_CTRL_TRANS_START (0x1 << 7)
+
+#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0)
+#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff)
+#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1)
+#define P2WI_CC_CLK_DIV(n) \
+ __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
+#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8)
+#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7)
+
+#define P2WI_IRQ_TRANS_DONE (0x1 << 0)
+#define P2WI_IRQ_TRANS_ERR (0x1 << 1)
+#define P2WI_IRQ_LOAD_BUSY (0x1 << 2)
+
+#define P2WI_STAT_TRANS_DONE (0x1 << 0)
+#define P2WI_STAT_TRANS_ERR (0x1 << 1)
+#define P2WI_STAT_LOAD_BUSY (0x1 << 2)
+#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8)
+#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff)
+#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01
+#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02
+#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04
+#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08
+#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10
+#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20
+#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40
+#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80
+#define P2WI_STAT_TRANS_ERR_BYTE_1 \
+ __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1)
+#define P2WI_STAT_TRANS_ERR_BYTE_2 \
+ __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2)
+#define P2WI_STAT_TRANS_ERR_BYTE_3 \
+ __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3)
+#define P2WI_STAT_TRANS_ERR_BYTE_4 \
+ __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4)
+#define P2WI_STAT_TRANS_ERR_BYTE_5 \
+ __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5)
+#define P2WI_STAT_TRANS_ERR_BYTE_6 \
+ __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6)
+#define P2WI_STAT_TRANS_ERR_BYTE_7 \
+ __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7)
+#define P2WI_STAT_TRANS_ERR_BYTE_8 \
+ __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8)
+
+#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0)
+#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff)
+#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8)
+#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff)
+#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16)
+#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff)
+#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24)
+#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff)
+#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0)
+#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff)
+#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8)
+#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff)
+#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16)
+#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff)
+#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24)
+#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff)
+
+#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0)
+#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7)
+#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1)
+#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4)
+
+#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0)
+#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff)
+#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8)
+#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff)
+#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16)
+#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff)
+#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24)
+#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff)
+#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0)
+#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff)
+#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8)
+#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff)
+#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16)
+#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff)
+#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24)
+#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff)
+
+#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0)
+#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1)
+#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2)
+#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3)
+#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4)
+#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5)
+
+#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0)
+#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff)
+#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8)
+#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff)
+#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16)
+#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff)
+#define P2WI_PM_INIT_SEND (0x1 << 31)
+
+struct sunxi_p2wi_reg {
+ u32 ctrl; /* 0x00 control */
+ u32 cc; /* 0x04 clock control */
+ u32 irq; /* 0x08 interrupt */
+ u32 status; /* 0x0c status */
+ u32 dataddr0; /* 0x10 data address 0 */
+ u32 dataddr1; /* 0x14 data address 1 */
+ u32 numbytes; /* 0x18 num bytes */
+ u32 data0; /* 0x1c data buffer 0 */
+ u32 data1; /* 0x20 data buffer 1 */
+ u32 linectrl; /* 0x24 line control */
+ u32 pm; /* 0x28 power management */
+};
+
+void p2wi_init(void);
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data);
+int p2wi_read(const u8 addr, u8 *data);
+int p2wi_write(const u8 addr, u8 data);
+
+#endif /* _SUNXI_P2WI_H */
#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
__PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
+#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24)
#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
struct sunxi_timer timer[6]; /* We have 6 timers */
u8 res2[16];
struct sunxi_avs avs;
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
struct sunxi_wdog wdog; /* 0x90 */
/* XXX the following is not accurate for sun5i/sun7i */
struct sunxi_64cnt cnt64; /* 0xa0 */
struct sunxi_tgp tgp[4];
u8 res5[8];
u32 cpu_cfg;
-#else /* CONFIG_SUN6I || CONFIG_SUN8I || ... */
+#else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || ... */
u8 res3[16];
struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */
#endif
#define WDT_CTRL_RESTART (0x1 << 0)
#define WDT_CTRL_KEY (0x0a57 << 1)
-#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
#define WDT_MODE_EN (0x1 << 0)
#define WDT_MODE_RESET_EN (0x1 << 1)
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PLAT_UNIPHIER_EHCI_H
+#define __PLAT_UNIPHIER_EHCI_H
+
+#include <linux/types.h>
+#include <asm/io.h>
+#include "mio-regs.h"
+
+struct uniphier_ehci_platform_data {
+ unsigned long base;
+};
+
+extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[];
+
+static inline void uniphier_ehci_reset(int index, int on)
+{
+ u32 tmp;
+
+ tmp = readl(MIO_USB_RSTCTRL(index));
+ if (on)
+ tmp &= ~MIO_USB_RSTCTRL_XRST;
+ else
+ tmp |= MIO_USB_RSTCTRL_XRST;
+ writel(tmp, MIO_USB_RSTCTRL(index));
+}
+
+#endif /* __PLAT_UNIPHIER_EHCI_H */
--- /dev/null
+/*
+ * UniPhier MIO (Media I/O) registers
+ *
+ * Copyright (C) 2014 Panasonic Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_MIO_REGS_H
+#define ARCH_MIO_REGS_H
+
+#define MIO_BASE 0x59810000
+
+#define MIO_CLKCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0020)
+#define MIO_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0110)
+#define MIO_USB_RSTCTRL(i) (MIO_BASE + 0x200 * (i) + 0x0114)
+
+#define MIO_USB_RSTCTRL_XRST (0x1 << 0)
+
+#endif /* ARCH_MIO_REGS_H */
.platdata = &serial_device##n \
};
+#include <asm/arch/ehci-uniphier.h>
+
#endif /* ARCH_PLATDEVICE_H */
#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
-#ifndef __ASSEMBLY__
+#ifdef __ASSEMBLY__
+
+ .macro set_pinsel, n, value, ra, rd
+ ldr \ra, =SG_PINSEL_ADDR(\n)
+ ldr \rd, [\ra]
+ and \rd, \rd, #SG_PINSEL_MASK(\n)
+ orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
+ str \rd, [\ra]
+ .endm
+
+#else
+
#include <linux/types.h>
#include <asm/io.h>
void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/*
+* Set bits for general purpose registers
+*/
+void imx_iomux_set_gpr_register(int group, int start_bit,
+ int num_bits, int value);
/* macros for declaring and using pinmux array */
#if defined(CONFIG_MX6QDL)
0 : wfi
ldr \wreg2, [\xreg1, GICC_AIAR]
str \wreg2, [\xreg1, GICC_AEOIR]
- and \wreg2, \wreg2, #3ff
+ and \wreg2, \wreg2, #0x3ff
cbnz \wreg2, 0b
.endm
#endif
* \param size size of memory region to change
* \param option dcache option to select
*/
-void mmu_set_region_dcache_behaviour(u32 start, int size,
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option);
/**
--- /dev/null
+/*
+ * arch/arm/include/debug/8250.S
+ *
+ * Copyright (C) 1994-2013 Russell King
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <linux/serial_reg.h>
+
+ .macro addruart, rp, rv, tmp
+ ldr \rp, =CONFIG_DEBUG_UART_PHYS
+ ldr \rv, =CONFIG_DEBUG_UART_VIRT
+ .endm
+
+#ifdef CONFIG_DEBUG_UART_8250_WORD
+ .macro store, rd, rx:vararg
+ str \rd, \rx
+ .endm
+
+ .macro load, rd, rx:vararg
+ ldr \rd, \rx
+ .endm
+#else
+ .macro store, rd, rx:vararg
+ strb \rd, \rx
+ .endm
+
+ .macro load, rd, rx:vararg
+ ldrb \rd, \rx
+ .endm
+#endif
+
+#define UART_SHIFT CONFIG_DEBUG_UART_8250_SHIFT
+
+ .macro senduart,rd,rx
+ store \rd, [\rx, #UART_TX << UART_SHIFT]
+ .endm
+
+ .macro busyuart,rd,rx
+1002: load \rd, [\rx, #UART_LSR << UART_SHIFT]
+ and \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ teq \rd, #UART_LSR_TEMT | UART_LSR_THRE
+ bne 1002b
+ .endm
+
+ .macro waituart,rd,rx
+#ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL
+1001: load \rd, [\rx, #UART_MSR << UART_SHIFT]
+ tst \rd, #UART_MSR_CTS
+ beq 1001b
+#endif
+ .endm
obj-y += cache-cp15.o
endif
+obj-$(CONFIG_DEBUG_LL) += debug.o
+
# For EABI conformant tool chains, provide eabi_compat()
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
extra-y += eabi_compat.o
#include <common.h>
#include <command.h>
#include <image.h>
-#include <vxworks.h>
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
#include <libfdt.h>
debug("%s: Warning: not implemented\n", __func__);
}
-void mmu_set_region_dcache_behaviour(u32 start, int size,
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
u32 *page_table = (u32 *)gd->arch.tlb_addr;
- u32 upto, end;
+ unsigned long upto, end;
end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
start = start >> MMU_SECTION_SHIFT;
- debug("%s: start=%x, size=%x, option=%d\n", __func__, start, size,
+ debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
option);
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
--- /dev/null
+/*
+ * linux/arch/arm/kernel/debug.S
+ *
+ * Copyright (C) 1994-1999 Russell King
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * 32-bit debugging code
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ .text
+
+/*
+ * Some debugging routines (useful if you've got MM problems and
+ * printk isn't working). For DEBUGGING ONLY!!! Do not leave
+ * references to these in a production kernel!
+ */
+
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
+
+#ifdef CONFIG_MMU
+ .macro addruart_current, rx, tmp1, tmp2
+ addruart \tmp1, \tmp2, \rx
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1
+ moveq \rx, \tmp1
+ movne \rx, \tmp2
+ .endm
+
+#else /* !CONFIG_MMU */
+ .macro addruart_current, rx, tmp1, tmp2
+ addruart \rx, \tmp1, \tmp2
+ .endm
+
+#endif /* CONFIG_MMU */
+
+/*
+ * Useful debugging routines
+ */
+ENTRY(printhex8)
+ mov r1, #8
+ b printhex
+ENDPROC(printhex8)
+
+ENTRY(printhex4)
+ mov r1, #4
+ b printhex
+ENDPROC(printhex4)
+
+ENTRY(printhex2)
+ mov r1, #2
+printhex: adr r2, hexbuf
+ add r3, r2, r1
+ mov r1, #0
+ strb r1, [r3]
+1: and r1, r0, #15
+ mov r0, r0, lsr #4
+ cmp r1, #10
+ addlt r1, r1, #'0'
+ addge r1, r1, #'a' - 10
+ strb r1, [r3, #-1]!
+ teq r3, r2
+ bne 1b
+ mov r0, r2
+ b printascii
+ENDPROC(printhex2)
+
+hexbuf: .space 16
+
+ .ltorg
+
+#ifndef CONFIG_DEBUG_SEMIHOSTING
+
+ENTRY(printascii)
+ addruart_current r3, r1, r2
+ b 2f
+1: waituart r2, r3
+ senduart r1, r3
+ busyuart r2, r3
+ teq r1, #'\n'
+ moveq r1, #'\r'
+ beq 1b
+2: teq r0, #0
+ ldrneb r1, [r0], #1
+ teqne r1, #0
+ bne 1b
+ mov pc, lr
+ENDPROC(printascii)
+
+ENTRY(printch)
+ addruart_current r3, r1, r2
+ mov r1, r0
+ mov r0, #0
+ b 1b
+ENDPROC(printch)
+
+#ifdef CONFIG_MMU
+ENTRY(debug_ll_addr)
+ addruart r2, r3, ip
+ str r2, [r0]
+ str r3, [r1]
+ mov pc, lr
+ENDPROC(debug_ll_addr)
+#endif
+
+#else
+
+ENTRY(printascii)
+ mov r1, r0
+ mov r0, #0x04 @ SYS_WRITE0
+ ARM( svc #0x123456 )
+ THUMB( svc #0xab )
+ mov pc, lr
+ENDPROC(printascii)
+
+ENTRY(printch)
+ adr r1, hexbuf
+ strb r0, [r1]
+ mov r0, #0x03 @ SYS_WRITEC
+ ARM( svc #0x123456 )
+ THUMB( svc #0xab )
+ mov pc, lr
+ENDPROC(printch)
+
+ENTRY(debug_ll_addr)
+ mov r2, #0
+ str r2, [r0]
+ str r2, [r1]
+ mov pc, lr
+ENDPROC(debug_ll_addr)
+
+#endif
uint32_t *hibernate_magic = 0;
SSYNC();
+ /* cppcheck-suppress nullPointer */
if (hibernate_magic[0] == 0xDEADBEEF) {
serial_putc('c');
bfin_write_EVT15(hibernate_magic[1]);
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_CPU CONFIG_BFIN_CPU
+
#endif
config SYS_ARCH
default "mips"
+config SYS_CPU
+ default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2
+ default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2
+
config USE_PRIVATE_LIBGCC
default y
config TARGET_QEMU_MIPS
bool "Support qemu-mips"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
+ select SUPPORTS_CPU_MIPS64_R1
+ select SUPPORTS_CPU_MIPS64_R2
config TARGET_MALTA
bool "Support malta"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_VCT
bool "Support vct"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_DBAU1X00
bool "Support dbau1x00"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
config TARGET_PB1X00
bool "Support pb1x00"
+ select SUPPORTS_LITTLE_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select SUPPORTS_CPU_MIPS32_R2
-config TARGET_QEMU_MIPS64
- bool "Support qemu-mips64"
endchoice
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
+if MIPS
+
+choice
+ prompt "Endianness selection"
+ help
+ Some MIPS boards can be configured for either little or big endian
+ byte order. These modes require different U-Boot images. In general there
+ is one preferred byteorder for a particular system but some systems are
+ just as commonly used in the one or the other endianness.
+
+config SYS_BIG_ENDIAN
+ bool "Big endian"
+ depends on SUPPORTS_BIG_ENDIAN
+
+config SYS_LITTLE_ENDIAN
+ bool "Little endian"
+ depends on SUPPORTS_LITTLE_ENDIAN
+
+endchoice
+
+choice
+ prompt "CPU selection"
+ default CPU_MIPS32_R2
+
+config CPU_MIPS32_R1
+ bool "MIPS32 Release 1"
+ depends on SUPPORTS_CPU_MIPS32_R1
+ select 32BIT
+ help
+ Choose this option to build an U-Boot for release 1 or later of the
+ MIPS32 architecture.
+
+config CPU_MIPS32_R2
+ bool "MIPS32 Release 2"
+ depends on SUPPORTS_CPU_MIPS32_R2
+ select 32BIT
+ help
+ Choose this option to build an U-Boot for release 2 or later of the
+ MIPS32 architecture.
+
+config CPU_MIPS64_R1
+ bool "MIPS64 Release 1"
+ depends on SUPPORTS_CPU_MIPS64_R1
+ select 64BIT
+ help
+ Choose this option to build a kernel for release 1 or later of the
+ MIPS64 architecture.
+
+config CPU_MIPS64_R2
+ bool "MIPS64 Release 2"
+ depends on SUPPORTS_CPU_MIPS64_R2
+ select 64BIT
+ help
+ Choose this option to build a kernel for release 2 or later of the
+ MIPS64 architecture.
+
+endchoice
+
+config SUPPORTS_BIG_ENDIAN
+ bool
+
+config SUPPORTS_LITTLE_ENDIAN
+ bool
+
+config SUPPORTS_CPU_MIPS32_R1
+ bool
+
+config SUPPORTS_CPU_MIPS32_R2
+ bool
+
+config SUPPORTS_CPU_MIPS64_R1
+ bool
+
+config SUPPORTS_CPU_MIPS64_R2
+ bool
+
+config 32BIT
+ bool
+
+config 64BIT
+ bool
+
+endif
+
endmenu
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := mips_4KC-
+ifdef CONFIG_SYS_BIG_ENDIAN
+32bit-emul := elf32btsmip
+64bit-emul := elf64btsmip
+32bit-bfd := elf32-tradbigmips
+64bit-bfd := elf64-tradbigmips
+PLATFORM_CPPFLAGS += -EB
+PLATFORM_LDFLAGS += -EB
endif
-# Handle special prefix in ELDK 4.0 toolchain
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS := -EL
+ifdef CONFIG_SYS_LITTLE_ENDIAN
+32bit-emul := elf32ltsmip
+64bit-emul := elf64ltsmip
+32bit-bfd := elf32-tradlittlemips
+64bit-bfd := elf64-tradlittlemips
+PLATFORM_CPPFLAGS += -EL
+PLATFORM_LDFLAGS += -EL
endif
-ifdef CONFIG_SYS_LITTLE_ENDIAN
-ENDIANNESS := -EL
+ifdef CONFIG_32BIT
+PLATFORM_CPPFLAGS += -mabi=32
+PLATFORM_LDFLAGS += -m $(32bit-emul)
+OBJCOPYFLAGS += -O $(32bit-bfd)
endif
-ifdef CONFIG_SYS_BIG_ENDIAN
-ENDIANNESS := -EB
+ifdef CONFIG_64BIT
+PLATFORM_CPPFLAGS += -mabi=64
+PLATFORM_LDFLAGS += -m$(64bit-emul)
+OBJCOPYFLAGS += -O $(64bit-bfd)
endif
-# Default to EB if no endianess is configured
-ENDIANNESS ?= -EB
+cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32
+cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2
+cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64
+cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2
+PLATFORM_CPPFLAGS += $(cpuflags-y)
PLATFORM_CPPFLAGS += -D__MIPS__
# On the other hand, we want PIC in the U-Boot code to relocate it from ROM
# to RAM. $28 is always used as gp.
#
-PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS)
+PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic
PLATFORM_CPPFLAGS += -msoft-float
-PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
+PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib
PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections -pie
OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got
-OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn
+OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding
# SPDX-License-Identifier: GPL-2.0+
#
-#
-# Default optimization level for MIPS32
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2
-PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS += -m elf32btsmip
-else
-PLATFORM_LDFLAGS += -m elf32ltsmip
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \
-T $(srctree)/examples/standalone/mips.lds
# SPDX-License-Identifier: GPL-2.0+
#
-#
-# Default optimization level for MIPS64
-#
-# Note: Toolchains with binutils prior to v2.16
-# are no longer supported by U-Boot MIPS tree!
-#
-PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64
-PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
-ifdef CONFIG_SYS_BIG_ENDIAN
-PLATFORM_LDFLAGS += -m elf64btsmip
-else
-PLATFORM_LDFLAGS += -m elf64ltsmip
-endif
-
CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \
-T $(srctree)/examples/standalone/mips64.lds
__rel_dyn_end = .;
}
+ .padding : {
+ /*
+ * Workaround for a binutils feature (or bug?).
+ *
+ * The GNU ld from binutils puts the dynamic relocation
+ * entries into the .rel.dyn section. Sometimes it
+ * allocates more dynamic relocation entries than it needs
+ * and the unused slots are set to R_MIPS_NONE entries.
+ *
+ * However the size of the .rel.dyn section in the ELF
+ * section header does not cover the unused entries, so
+ * objcopy removes those during stripping.
+ *
+ * Create a small section here to avoid that.
+ */
+ LONG(0xFFFFFFFF)
+ }
+
_end = .;
.bss __rel_dyn_start (OVERLAY) : {
config TARGET_JUPITER
bool "Support jupiter"
-config TARGET_MCC200
- bool "Support mcc200"
-
config TARGET_MOTIONPRO
bool "Support motionpro"
config TARGET_V38B
bool "Support v38b"
-config TARGET_TOP5200
- bool "Support TOP5200"
-
config TARGET_CPCI5200
bool "Support cpci5200"
source "board/manroland/hmi1001/Kconfig"
source "board/manroland/mucmc52/Kconfig"
source "board/manroland/uc101/Kconfig"
-source "board/mcc200/Kconfig"
source "board/motionpro/Kconfig"
source "board/munices/Kconfig"
source "board/phytec/pcm030/Kconfig"
setup_ifc_sram = (void *)SRAM_BASE_ADDR;
dst = (u32 *) SRAM_BASE_ADDR;
src = (u32 *) setup_ifc;
- for (i = 0; i < 1024; i++)
+ for (i = 0; i < 1024; i++) {
+ /* cppcheck-suppress nullPointer */
*dst++ = *src++;
+ }
+ /* cppcheck-suppress nullPointer */
setup_ifc_sram();
/* CLEANUP */
config TARGET_SPD823TS
bool "Support SPD823TS"
-config TARGET_TOP860
- bool "Support TOP860"
-
config TARGET_KUP4K
bool "Support KUP4K"
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset((void *)gd, 0, sizeof(gd_t));
}
/*
#define IIC_EXTSTS_XFRA 0x01
#define IIC_EXTSTS_ICT 0x02
#define IIC_EXTSTS_LA 0x04
+#define IIC_EXTSTS_BCS_MASK 0x70
+#define IIC_EXTSTS_BCS_FREE 0x40
/* XTCNTLSS Register Bit definition */
#define IIC_XTCNTLSS_SRST 0x01
#include <common.h>
#include <os.h>
+#include <cli.h>
#include <asm/getopt.h>
#include <asm/io.h>
#include <asm/sections.h>
/* Execute command if required */
if (state->cmd) {
+ cli_init();
+
run_command_list(state->cmd, -1, 0);
if (!state->interactive)
os_exit(state->exit_type);
bootargs = getenv("bootargs");
/* Clear zero page */
+ /* cppcheck-suppress nullPointer */
memset(param, 0, 0x1000);
/* Set commandline */
menu "SPARC architecture"
depends on SPARC
-config SYS_ARCH
- default "sparc"
+config LEON
+ bool
+
+config LEON2
+ bool
+ select LEON
+
+config LEON3
+ bool
+ select LEON
choice
- prompt "Target select"
+ prompt "Board select"
config TARGET_GRSIM_LEON2
- bool "Support grsim_leon2"
+ bool "GRSIM simulating a LEON2 board"
+ select LEON2
config TARGET_GR_CPCI_AX2000
- bool "Support gr_cpci_ax2000"
+ bool "Gaisler GR-CPCI-AX2000 board"
+ select LEON3
config TARGET_GR_EP2S60
- bool "Support gr_ep2s60"
+ bool "Gaisler Template design for Altera NIOS board with Stratix EP2S60"
+ select LEON3
+ help
+ Gaisler Research AB's Template design (GPL Open Source SPARC/LEON3
+ 96MHz) for Altera NIOS Development board Stratix II edition,
+ with the FPGA device EP2S60.
config TARGET_GR_XC3S_1500
- bool "Support gr_xc3s_1500"
+ bool "Gaisler GR-XC3S-1500 spartan board"
+ select LEON3
config TARGET_GRSIM
- bool "Support grsim"
+ bool "GRSIM simulating a LEON3 GR-XC3S-1500 board"
+ select LEON3
endchoice
+config SYS_ARCH
+ default "sparc"
+
+config SYS_CPU
+ default "leon2" if LEON2
+ default "leon3" if LEON3
+
+config SYS_VENDOR
+ default "gaisler"
+
source "board/gaisler/gr_cpci_ax2000/Kconfig"
source "board/gaisler/gr_ep2s60/Kconfig"
source "board/gaisler/gr_xc3s_1500/Kconfig"
-T $(srctree)/examples/standalone/sparc.lds
PLATFORM_CPPFLAGS += -D__sparc__
+
+PLATFORM_RELFLAGS += -fPIC
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fPIC
-
-PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2
+++ /dev/null
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_RELFLAGS += -fPIC
-
-PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3
extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
-obj-y += interrupts.o cpu.o
+obj-y += interrupts.o cpu.o call64.o
--- /dev/null
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Copyright (C) 1991, 1992, 1993 Linus Torvalds
+ *
+ * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/global_data.h>
+#include <asm/msr-index.h>
+#include <asm/processor-flags.h>
+
+.code32
+.globl cpu_call64
+cpu_call64:
+ /*
+ * cpu_call64(ulong pgtable, ulong setup_base, ulong target)
+ *
+ * eax - pgtable
+ * edx - setup_base
+ * ecx - target
+ */
+ cli
+ push %ecx /* arg2 = target */
+ push %edx /* arg1 = setup_base */
+ mov %eax, %ebx
+
+ /* Load new GDT with the 64bit segments using 32bit descriptor */
+ leal gdt, %eax
+ movl %eax, gdt+2
+ lgdt gdt
+
+ /* Enable PAE mode */
+ movl $(X86_CR4_PAE), %eax
+ movl %eax, %cr4
+
+ /* Enable the boot page tables */
+ leal (%ebx), %eax
+ movl %eax, %cr3
+
+ /* Enable Long mode in EFER (Extended Feature Enable Register) */
+ movl $MSR_EFER, %ecx
+ rdmsr
+ btsl $_EFER_LME, %eax
+ wrmsr
+
+ /* After gdt is loaded */
+ xorl %eax, %eax
+ lldt %ax
+ movl $0x20, %eax
+ ltr %ax
+
+ /*
+ * Setup for the jump to 64bit mode
+ *
+ * When the jump is performed we will be in long mode but
+ * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
+ * (and in turn EFER.LMA = 1). To jump into 64bit mode we use
+ * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
+ * We place all of the values on our mini stack so lret can
+ * used to perform that far jump. See the gdt below.
+ */
+ pop %esi /* setup_base */
+
+ pushl $0x10
+ leal lret_target, %eax
+ pushl %eax
+
+ /* Enter paged protected Mode, activating Long Mode */
+ movl $(X86_CR0_PG | X86_CR0_PE), %eax
+ movl %eax, %cr0
+
+ /* Jump from 32bit compatibility mode into 64bit mode. */
+ lret
+
+code64:
+lret_target:
+ pop %eax /* target */
+ mov %eax, %eax /* Clear bits 63:32 */
+ jmp *%eax /* Jump to the 64-bit target */
+
+ .data
+gdt:
+ .word gdt_end - gdt
+ .long gdt
+ .word 0
+ .quad 0x0000000000000000 /* NULL descriptor */
+ .quad 0x00af9a000000ffff /* __KERNEL_CS */
+ .quad 0x00cf92000000ffff /* __KERNEL_DS */
+ .quad 0x0080890000000000 /* TS descriptor */
+ .quad 0x0000000000000000 /* TS continued */
+gdt_end:
#include <common.h>
#include <command.h>
+#include <errno.h>
+#include <malloc.h>
#include <asm/control_regs.h>
+#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/interrupt.h>
{
return 1;
}
+
+void cpu_enable_paging_pae(ulong cr3)
+{
+ __asm__ __volatile__(
+ /* Load the page table address */
+ "movl %0, %%cr3\n"
+ /* Enable pae */
+ "movl %%cr4, %%eax\n"
+ "orl $0x00000020, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ /* Enable paging */
+ "movl %%cr0, %%eax\n"
+ "orl $0x80000000, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ :
+ : "r" (cr3)
+ : "eax");
+}
+
+void cpu_disable_paging_pae(void)
+{
+ /* Turn off paging */
+ __asm__ __volatile__ (
+ /* Disable paging */
+ "movl %%cr0, %%eax\n"
+ "andl $0x7fffffff, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ /* Disable pae */
+ "movl %%cr4, %%eax\n"
+ "andl $0xffffffdf, %%eax\n"
+ "movl %%eax, %%cr4\n"
+ :
+ :
+ : "eax");
+}
+
+static bool has_cpuid(void)
+{
+ unsigned long flag;
+
+ asm volatile("pushf\n" \
+ "pop %%eax\n"
+ "mov %%eax, %%ecx\n" /* ecx = flags */
+ "xor %1, %%eax\n"
+ "push %%eax\n"
+ "popf\n" /* flags ^= $2 */
+ "pushf\n"
+ "pop %%eax\n" /* eax = flags */
+ "push %%ecx\n"
+ "popf\n" /* flags = ecx */
+ "xor %%ecx, %%eax\n"
+ "mov %%eax, %0"
+ : "=r" (flag)
+ : "i" (1 << 21)
+ : "eax", "ecx", "memory");
+
+ return flag != 0;
+}
+
+static bool can_detect_long_mode(void)
+{
+ unsigned long flag;
+
+ asm volatile("mov $0x80000000, %%eax\n"
+ "cpuid\n"
+ "mov %%eax, %0"
+ : "=r" (flag)
+ :
+ : "eax", "ebx", "ecx", "edx", "memory");
+
+ return flag > 0x80000000UL;
+}
+
+static bool has_long_mode(void)
+{
+ unsigned long flag;
+
+ asm volatile("mov $0x80000001, %%eax\n"
+ "cpuid\n"
+ "mov %%edx, %0"
+ : "=r" (flag)
+ :
+ : "eax", "ebx", "ecx", "edx", "memory");
+
+ return flag & (1 << 29) ? true : false;
+}
+
+int cpu_has_64bit(void)
+{
+ return has_cpuid() && can_detect_long_mode() &&
+ has_long_mode();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86");
+
+ return 0;
+}
+
+#define PAGETABLE_SIZE (6 * 4096)
+
+/**
+ * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode
+ *
+ * @pgtable: Pointer to a 24iKB block of memory
+ */
+static void build_pagetable(uint32_t *pgtable)
+{
+ uint i;
+
+ memset(pgtable, '\0', PAGETABLE_SIZE);
+
+ /* Level 4 needs a single entry */
+ pgtable[0] = (uint32_t)&pgtable[1024] + 7;
+
+ /* Level 3 has one 64-bit entry for each GiB of memory */
+ for (i = 0; i < 4; i++) {
+ pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] +
+ 0x1000 * i + 7;
+ }
+
+ /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */
+ for (i = 0; i < 2048; i++)
+ pgtable[2048 + i * 2] = 0x183 + (i << 21UL);
+}
+
+int cpu_jump_to_64bit(ulong setup_base, ulong target)
+{
+ uint32_t *pgtable;
+
+ pgtable = memalign(4096, PAGETABLE_SIZE);
+ if (!pgtable)
+ return -ENOMEM;
+
+ build_pagetable(pgtable);
+ cpu_call64((ulong)pgtable, setup_base, target);
+ free(pgtable);
+
+ return -EFAULT;
+}
void bootm_announce_and_cleanup(void);
+/**
+ * boot_linux_kernel() - boot a linux kernel
+ *
+ * This boots a kernel image, either 32-bit or 64-bit. It will also work with
+ * a self-extracting kernel, if you set @image_64bit to false.
+ *
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @load_address: Pointer to the start of the kernel image
+ * @image_64bit: true if the image is a raw 64-bit kernel, false if it
+ * is raw 32-bit or any type of self-extracting kernel
+ * such as a bzImage.
+ * @return -ve error code. This function does not return if the kernel was
+ * booted successfully.
+ */
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit);
+
#endif
--- /dev/null
+/*
+ * Copyright (c) 2014 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __X86_CPU_H
+#define __X86_CPU_H
+
+ /**
+ * cpu_enable_paging_pae() - Enable PAE-paging
+ *
+ * @pdpt: Value to set in cr3 (PDPT or PML4T)
+ */
+void cpu_enable_paging_pae(ulong cr3);
+
+/**
+ * cpu_disable_paging_pae() - Disable paging and PAE
+ */
+void cpu_disable_paging_pae(void);
+
+/**
+ * cpu_has_64bit() - Check if the CPU has 64-bit support
+ *
+ * @return 1 if this CPU supports long mode (64-bit), 0 if not
+ */
+int cpu_has_64bit(void);
+
+/**
+ * cpu_call64() - Jump to a 64-bit Linux kernel (internal function)
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * This function is used internally - see cpu_jump_to_64bit() for a more
+ * useful function.
+ *
+ * @pgtable: Address of 24KB area containing the page table
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @target: Pointer to the start of the kernel image
+ */
+void cpu_call64(ulong pgtable, ulong setup_base, ulong target);
+
+/**
+ * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel
+ *
+ * The kernel is uncompressed and the 64-bit entry point is expected to be
+ * at @target.
+ *
+ * @setup_base: Pointer to the setup.bin information for the kernel
+ * @target: Pointer to the start of the kernel image
+ */
+int cpu_jump_to_64bit(ulong setup_base, ulong target);
+
+#endif
#define MSR_IA32_PERFCTR0 0x000000c1
#define MSR_IA32_PERFCTR1 0x000000c2
#define MSR_FSB_FREQ 0x000000cd
+#define MSR_NHM_PLATFORM_INFO 0x000000ce
#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25)
#define NHM_C1_AUTO_DEMOTE (1UL << 26)
#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
+#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
+#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
+#define MSR_PLATFORM_INFO 0x000000ce
#define MSR_MTRRcap 0x000000fe
#define MSR_IA32_BBL_CR_CTL 0x00000119
#define MSR_IA32_BBL_CR_CTL3 0x0000011e
#define MSR_OFFCORE_RSP_0 0x000001a6
#define MSR_OFFCORE_RSP_1 0x000001a7
+#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad
+#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae
+
+#define MSR_LBR_SELECT 0x000001c8
+#define MSR_LBR_TOS 0x000001c9
+#define MSR_LBR_NHM_FROM 0x00000680
+#define MSR_LBR_NHM_TO 0x000006c0
+#define MSR_LBR_CORE_FROM 0x00000040
+#define MSR_LBR_CORE_TO 0x00000060
#define MSR_IA32_PEBS_ENABLE 0x000003f1
#define MSR_IA32_DS_AREA 0x00000600
#define MSR_IA32_PERF_CAPABILITIES 0x00000345
+#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6
#define MSR_MTRRfix64K_00000 0x00000250
#define MSR_MTRRfix16K_80000 0x00000258
#define MSR_IA32_LASTINTTOIP 0x000001de
/* DEBUGCTLMSR bits (others vary by model): */
-#define DEBUGCTLMSR_LBR (1UL << 0)
+#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
+/* single-step on branches */
#define DEBUGCTLMSR_BTF (1UL << 1)
#define DEBUGCTLMSR_TR (1UL << 6)
#define DEBUGCTLMSR_BTS (1UL << 7)
#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
+#define MSR_IA32_POWER_CTL 0x000001fc
+
#define MSR_IA32_MC0_CTL 0x00000400
#define MSR_IA32_MC0_STATUS 0x00000401
#define MSR_IA32_MC0_ADDR 0x00000402
#define MSR_IA32_MC0_MISC 0x00000403
+/* C-state Residency Counters */
+#define MSR_PKG_C3_RESIDENCY 0x000003f8
+#define MSR_PKG_C6_RESIDENCY 0x000003f9
+#define MSR_PKG_C7_RESIDENCY 0x000003fa
+#define MSR_CORE_C3_RESIDENCY 0x000003fc
+#define MSR_CORE_C6_RESIDENCY 0x000003fd
+#define MSR_CORE_C7_RESIDENCY 0x000003fe
+#define MSR_PKG_C2_RESIDENCY 0x0000060d
+#define MSR_PKG_C8_RESIDENCY 0x00000630
+#define MSR_PKG_C9_RESIDENCY 0x00000631
+#define MSR_PKG_C10_RESIDENCY 0x00000632
+
+/* Run Time Average Power Limiting (RAPL) Interface */
+
+#define MSR_RAPL_POWER_UNIT 0x00000606
+
+#define MSR_PKG_POWER_LIMIT 0x00000610
+#define MSR_PKG_ENERGY_STATUS 0x00000611
+#define MSR_PKG_PERF_STATUS 0x00000613
+#define MSR_PKG_POWER_INFO 0x00000614
+
+#define MSR_DRAM_POWER_LIMIT 0x00000618
+#define MSR_DRAM_ENERGY_STATUS 0x00000619
+#define MSR_DRAM_PERF_STATUS 0x0000061b
+#define MSR_DRAM_POWER_INFO 0x0000061c
+
+#define MSR_PP0_POWER_LIMIT 0x00000638
+#define MSR_PP0_ENERGY_STATUS 0x00000639
+#define MSR_PP0_POLICY 0x0000063a
+#define MSR_PP0_PERF_STATUS 0x0000063b
+
+#define MSR_PP1_POWER_LIMIT 0x00000640
+#define MSR_PP1_ENERGY_STATUS 0x00000641
+#define MSR_PP1_POLICY 0x00000642
+
+#define MSR_CORE_C1_RES 0x00000660
+
#define MSR_AMD64_MC0_MASK 0xc0010044
#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
#define MSR_P6_EVNTSEL0 0x00000186
#define MSR_P6_EVNTSEL1 0x00000187
+#define MSR_KNC_PERFCTR0 0x00000020
+#define MSR_KNC_PERFCTR1 0x00000021
+#define MSR_KNC_EVNTSEL0 0x00000028
+#define MSR_KNC_EVNTSEL1 0x00000029
+
+/* Alternative perfctr range with full access. */
+#define MSR_IA32_PMC0 0x000004c1
+
/* AMD64 MSRs. Not complete. See the architecture manual for a more
complete list. */
#define MSR_AMD64_PATCH_LEVEL 0x0000008b
+#define MSR_AMD64_TSC_RATIO 0xc0000104
#define MSR_AMD64_NB_CFG 0xc001001f
#define MSR_AMD64_PATCH_LOADER 0xc0010020
#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
#define MSR_AMD64_OSVW_STATUS 0xc0010141
+#define MSR_AMD64_LS_CFG 0xc0011020
#define MSR_AMD64_DC_CFG 0xc0011022
+#define MSR_AMD64_BU_CFG2 0xc001102a
#define MSR_AMD64_IBSFETCHCTL 0xc0011030
#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
+#define MSR_AMD64_IBSFETCH_REG_COUNT 3
+#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
#define MSR_AMD64_IBSOPCTL 0xc0011033
#define MSR_AMD64_IBSOPRIP 0xc0011034
#define MSR_AMD64_IBSOPDATA 0xc0011035
#define MSR_AMD64_IBSOPDATA3 0xc0011037
#define MSR_AMD64_IBSDCLINAD 0xc0011038
#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
+#define MSR_AMD64_IBSOP_REG_COUNT 7
+#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
#define MSR_AMD64_IBSCTL 0xc001103a
#define MSR_AMD64_IBSBRTARGET 0xc001103b
+#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */
+
+/* Fam 16h MSRs */
+#define MSR_F16H_L2I_PERF_CTL 0xc0010230
+#define MSR_F16H_L2I_PERF_CTR 0xc0010231
/* Fam 15h MSRs */
#define MSR_F15H_PERF_CTL 0xc0010200
#define MSR_F15H_PERF_CTR 0xc0010201
+#define MSR_F15H_NB_PERF_CTL 0xc0010240
+#define MSR_F15H_NB_PERF_CTR 0xc0010241
/* Fam 10h MSRs */
#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
#define MSR_IA32_PLATFORM_ID 0x00000017
#define MSR_IA32_EBL_CR_POWERON 0x0000002a
#define MSR_EBC_FREQUENCY_ID 0x0000002c
+#define MSR_SMI_COUNT 0x00000034
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
+#define MSR_IA32_TSC_ADJUST 0x0000003b
#define FEATURE_CONTROL_LOCKED (1<<0)
#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
+#define MSR_IA32_TSCDEADLINE 0x000006e0
+
#define MSR_IA32_UCODE_WRITE 0x00000079
#define MSR_IA32_UCODE_REV 0x0000008b
#define MSR_IA32_PERF_STATUS 0x00000198
#define MSR_IA32_PERF_CTL 0x00000199
+#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
+#define MSR_AMD_PERF_STATUS 0xc0010063
+#define MSR_AMD_PERF_CTL 0xc0010062
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
+#define ENERGY_PERF_BIAS_PERFORMANCE 0
+#define ENERGY_PERF_BIAS_NORMAL 6
+#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
+#define MSR_IA32_TSC_DEADLINE 0x000006E0
+
/* P4/Xeon+ specific */
#define MSR_IA32_MCG_EAX 0x00000180
#define MSR_IA32_MCG_EBX 0x00000181
#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
-
+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
+#define MSR_IA32_VMX_VMFUNC 0x00000491
+
+/* VMX_BASIC bits and bitmasks */
+#define VMX_BASIC_VMCS_SIZE_SHIFT 32
+#define VMX_BASIC_64 0x0001000000000000LLU
+#define VMX_BASIC_MEM_TYPE_SHIFT 50
+#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU
+#define VMX_BASIC_MEM_TYPE_WB 6LLU
+#define VMX_BASIC_INOUT 0x0040000000000000LLU
+
+/* MSR_IA32_VMX_MISC bits */
+#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
+#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F
/* AMD-V MSRs */
#define MSR_VM_CR 0xc0010114
unsigned install_e820_map(unsigned max_entries, struct e820entry *);
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
- void **load_address);
+ ulong *load_addressp);
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
unsigned long initrd_addr, unsigned long initrd_size);
-void boot_zimage(void *setup_base, void *load_address);
-
#endif
#include <common.h>
#include <command.h>
+#include <errno.h>
#include <fdt_support.h>
#include <image.h>
#include <u-boot/zlib.h>
#include <asm/bootparam.h>
+#include <asm/cpu.h>
#include <asm/byteorder.h>
#include <asm/zimage.h>
#ifdef CONFIG_SYS_COREBOOT
}
if (is_zimage) {
- void *load_address;
+ ulong load_address;
char *base_ptr;
base_ptr = (char *)load_zimage(data, len, &load_address);
- images->os.load = (ulong)load_address;
+ images->os.load = load_address;
cmd_line_dest = base_ptr + COMMAND_LINE_OFFSET;
images->ep = (ulong)base_ptr;
} else if (images->ep) {
cmd_line_dest = (void *)images->ep + COMMAND_LINE_OFFSET;
} else {
- printf("## Kernel loading failed (no setup) ...\n");
+ printf("## Kernel loading failed (missing x86 kernel setup) ...\n");
goto error;
}
return 1;
}
+int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit)
+{
+ bootm_announce_and_cleanup();
+
+#ifdef CONFIG_SYS_COREBOOT
+ timestamp_add_now(TS_U_BOOT_START_KERNEL);
+#endif
+ if (image_64bit) {
+ if (!cpu_has_64bit()) {
+ puts("Cannot boot 64-bit kernel on 32-bit machine\n");
+ return -EFAULT;
+ }
+ return cpu_jump_to_64bit(setup_base, load_address);
+ } else {
+ /*
+ * Set %ebx, %ebp, and %edi to 0, %esi to point to the
+ * boot_params structure, and then jump to the kernel. We
+ * assume that %cs is 0x10, 4GB flat, and read/execute, and
+ * the data segments are 0x18, 4GB flat, and read/write.
+ * U-boot is setting them up that way for itself in
+ * arch/i386/cpu/cpu.c.
+ */
+ __asm__ __volatile__ (
+ "movl $0, %%ebp\n"
+ "cli\n"
+ "jmp *%[kernel_entry]\n"
+ :: [kernel_entry]"a"(load_address),
+ [boot_params] "S"(setup_base),
+ "b"(0), "D"(0)
+ );
+ }
+
+ /* We can't get to here */
+ return -EFAULT;
+}
+
/* Subcommand: GO */
static int boot_jump_linux(bootm_headers_t *images)
{
debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n",
images->ep, images->os.load);
- boot_zimage((struct boot_params *)images->ep, (void *)images->os.load);
- /* does not return */
-
- return 1;
+ return boot_linux_kernel(images->ep, images->os.load,
+ images->os.arch == IH_ARCH_X86_64);
}
int do_bootm_linux(int flag, int argc, char * const argv[],
if (flag & BOOTM_STATE_OS_PREP)
return boot_prep_linux(images);
- if (flag & BOOTM_STATE_OS_GO) {
- boot_jump_linux(images);
- return 0;
- }
+ if (flag & BOOTM_STATE_OS_GO)
+ return boot_jump_linux(images);
return boot_jump_linux(images);
}
#include <common.h>
#include <physmem.h>
+#include <asm/cpu.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
x86_phys_map_page(page_addr, page_addr, 0);
}
- /* Turn on paging */
- __asm__ __volatile__(
- /* Load the page table address */
- "movl %0, %%cr3\n\t"
- /* Enable pae */
- "movl %%cr4, %%eax\n\t"
- "orl $0x00000020, %%eax\n\t"
- "movl %%eax, %%cr4\n\t"
- /* Enable paging */
- "movl %%cr0, %%eax\n\t"
- "orl $0x80000000, %%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- :
- : "r" (pdpt)
- : "eax"
- );
+ cpu_enable_paging_pae((ulong)pdpt);
}
/* Disable paging and PAE mode. */
static void x86_phys_exit_paging(void)
{
- /* Turn off paging */
- __asm__ __volatile__ (
- /* Disable paging */
- "movl %%cr0, %%eax\n\t"
- "andl $0x7fffffff, %%eax\n\t"
- "movl %%eax, %%cr0\n\t"
- /* Disable pae */
- "movl %%cr4, %%eax\n\t"
- "andl $0xffffffdf, %%eax\n\t"
- "movl %%eax, %%cr4\n\t"
- :
- :
- : "eax"
- );
+ cpu_disable_paging_pae();
}
/*
}
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
- void **load_address)
+ ulong *load_addressp)
{
struct boot_params *setup_base;
int setup_size;
/* Determine load address */
if (big_image)
- *load_address = (void *)BZIMAGE_LOAD_ADDR;
+ *load_addressp = BZIMAGE_LOAD_ADDR;
else
- *load_address = (void *)ZIMAGE_LOAD_ADDR;
+ *load_addressp = ZIMAGE_LOAD_ADDR;
printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base);
memset(setup_base, 0, sizeof(*setup_base));
return 0;
}
- printf("Loading %s at address %p (%ld bytes)\n",
- big_image ? "bzImage" : "zImage", *load_address, kernel_size);
+ printf("Loading %s at address %lx (%ld bytes)\n",
+ big_image ? "bzImage" : "zImage", *load_addressp, kernel_size);
- memmove(*load_address, image + setup_size, kernel_size);
+ memmove((void *)*load_addressp, image + setup_size, kernel_size);
return setup_base;
}
return 0;
}
-void boot_zimage(void *setup_base, void *load_address)
-{
- bootm_announce_and_cleanup();
-
-#ifdef CONFIG_SYS_COREBOOT
- timestamp_add_now(TS_U_BOOT_START_KERNEL);
-#endif
- /*
- * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params
- * structure, and then jump to the kernel. We assume that %cs is
- * 0x10, 4GB flat, and read/execute, and the data segments are 0x18,
- * 4GB flat, and read/write. U-boot is setting them up that way for
- * itself in arch/i386/cpu/cpu.c.
- */
- __asm__ __volatile__ (
- "movl $0, %%ebp\n"
- "cli\n"
- "jmp *%[kernel_entry]\n"
- :: [kernel_entry]"a"(load_address),
- [boot_params] "S"(setup_base),
- "b"(0), "D"(0)
- );
-}
-
void setup_pcat_compatibility(void)
__attribute__((weak, alias("__setup_pcat_compatibility")));
{
struct boot_params *base_ptr;
void *bzImage_addr = NULL;
- void *load_address;
+ ulong load_address;
char *s;
ulong bzImage_size = 0;
ulong initrd_addr = 0;
base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address);
if (!base_ptr) {
- printf("## Kernel loading failed ...\n");
+ puts("## Kernel loading failed ...\n");
return -1;
}
if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET,
0, initrd_addr, initrd_size)) {
- printf("Setting up boot parameters failed ...\n");
+ puts("Setting up boot parameters failed ...\n");
return -1;
}
/* we assume that the kernel is in place */
- boot_zimage(base_ptr, load_address);
- /* does not return */
-
- return -1;
+ return boot_linux_kernel((ulong)base_ptr, load_address, false);
}
U_BOOT_CMD(
if TARGET_DB_MV784MP_GP
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
- string
default "db-mv784mp-gp"
config SYS_VENDOR
- string
default "Marvell"
config SYS_SOC
- string
default "armada-xp"
config SYS_CONFIG_NAME
- string
default "db-mv784mp-gp"
endif
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
+
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
return 0;
}
+
+#ifdef CONFIG_USB_GADGET
+struct s3c_plat_otg_data socfpga_otg_data = {
+ .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
+ .usb_gusbcfg = 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return s3c_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+ return 1;
+}
+#endif
MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? (IMX_GPIO_NR(3, 20)) : -1;
+}
+
static void setup_spi(void)
{
int i;
return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
}
+static iomux_v3_cfg_t const feature_pads[] = {
+ /* SD card detect */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
+
+ /* eMMC soldered? */
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
+};
+
+static void setup_iomux_features(void)
+{
+ imx_iomux_v3_setup_multiple_pads(feature_pads,
+ ARRAY_SIZE(feature_pads));
+}
+
int board_early_init_f(void)
{
setup_iomux_uart();
setup_iomux_spi();
+ setup_iomux_features();
return 0;
}
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
+iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
int board_mmc_getcd(struct mmc *mmc)
{
- return 1;
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret;
+
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+ gpio_direction_input(IMX_GPIO_NR(4, 5));
+ ret = gpio_get_value(IMX_GPIO_NR(4, 5));
+ } else {
+ gpio_direction_input(IMX_GPIO_NR(1, 5));
+ ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
+ }
+
+ return ret;
}
-struct fsl_esdhc_cfg usdhc_cfg[] = {
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
};
int board_mmc_init(bd_t *bis)
{
+ s32 status = 0;
+ u32 index = 0;
+
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
- usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].max_bus_width = 8;
+ usdhc_cfg[1].max_bus_width = 4;
+
+ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+ switch (index) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ }
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ return status;
}
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
void board_show_activity (ulong timestamp)
{
#ifdef CONFIG_STATUS_LED
- if ((timestamp % (CONFIG_SYS_HZ / 2) == 0)
+ if ((timestamp % (CONFIG_SYS_HZ / 2)) == 0)
lcd_heartbeat ();
#endif
}
#ifdef CONFIG_DWC_AHSATA
static int cm_fx6_issd_gpios[] = {
/* The order of the GPIOs in the array is important! */
+ CM_FX6_SATA_LDO_EN,
CM_FX6_SATA_PHY_SLP,
CM_FX6_SATA_NRSTDLY,
CM_FX6_SATA_PWREN,
CM_FX6_SATA_NSTANDBY1,
CM_FX6_SATA_NSTANDBY2,
- CM_FX6_SATA_LDO_EN,
};
static void cm_fx6_sata_power(int on)
spl_mx6s_dram_init(DDR_32BIT_1GB, false);
bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
- if (bank1_size == 0x40000000)
- return 0;
-
+ bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
if (bank1_size == 0x20000000) {
+ if (bank2_size == 0x20000000)
+ return 0;
+
spl_mx6s_dram_init(DDR_32BIT_512MB, true);
return 0;
}
#include <i2c.h>
#include <usb.h>
#include <mmc.h>
-#include <nand.h>
#include <twl4030.h>
-#include <bmp_layout.h>
#include <linux/compiler.h>
#include <asm/io.h>
+#include <asm/errno.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/ehci-omap.h>
#include <asm/gpio.h>
+#include "../common/common.h"
#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
"NAND",
};
-static u32 gpmc_net_config[GPMC_MAX_REG] = {
- NET_GPMC_CONFIG1,
- NET_GPMC_CONFIG2,
- NET_GPMC_CONFIG3,
- NET_GPMC_CONFIG4,
- NET_GPMC_CONFIG5,
- NET_GPMC_CONFIG6,
- 0
-};
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_CMD_NAND
-static int splash_load_from_nand(u32 bmp_load_addr)
-{
- struct bmp_header *bmp_hdr;
- int res, splash_screen_nand_offset = 0x100000;
- size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
-
- if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
- goto splash_address_too_high;
-
- res = nand_read_skip_bad(&nand_info[nand_curr_device],
- splash_screen_nand_offset, &bmp_header_size,
- NULL, nand_info[nand_curr_device].size,
- (u_char *)bmp_load_addr);
- if (res < 0)
- return res;
-
- bmp_hdr = (struct bmp_header *)bmp_load_addr;
- bmp_size = le32_to_cpu(bmp_hdr->file_size);
-
- if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
- goto splash_address_too_high;
-
- return nand_read_skip_bad(&nand_info[nand_curr_device],
- splash_screen_nand_offset, &bmp_size,
- NULL, nand_info[nand_curr_device].size,
- (u_char *)bmp_load_addr);
-
-splash_address_too_high:
- printf("Error: splashimage address too high. Data overwrites U-Boot "
- "and/or placed beyond DRAM boundaries.\n");
-
- return -1;
-}
-#else
-static inline int splash_load_from_nand(void)
-{
- return -1;
-}
-#endif /* CONFIG_CMD_NAND */
-
#ifdef CONFIG_SPL_BUILD
/*
* Routine: get_board_mem_timings
}
#endif
+#define CM_T35_SPLASH_NAND_OFFSET 0x100000
+
int splash_screen_prepare(void)
{
- char *env_splashimage_value;
- u32 bmp_load_addr;
-
- env_splashimage_value = getenv("splashimage");
- if (env_splashimage_value == NULL)
- return -1;
-
- bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
- if (bmp_load_addr == 0) {
- printf("Error: bad splashimage address specified\n");
- return -1;
- }
-
- return splash_load_from_nand(bmp_load_addr);
+ return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
}
-#endif /* CONFIG_LCD */
/*
* Routine: board_init
return 0;
}
-static u32 cm_t3x_rev;
-
/*
* Routine: get_board_rev
* Description: read system revision
*/
u32 get_board_rev(void)
{
- if (!cm_t3x_rev)
- cm_t3x_rev = cl_eeprom_get_board_rev();
-
- return cm_t3x_rev;
+ return cl_eeprom_get_board_rev();
};
-/*
- * Routine: misc_init_r
- * Description: display die ID
- */
int misc_init_r(void)
{
- u32 board_rev = get_board_rev();
- u32 rev_major = board_rev / 100;
- u32 rev_minor = board_rev - (rev_major * 100);
-
- if ((rev_minor / 10) * 10 == rev_minor)
- rev_minor = rev_minor / 10;
-
- printf("PCB: %u.%u\n", rev_major, rev_minor);
+ cl_print_pcb_info();
dieid_num_r();
return 0;
}
#endif
-/*
- * Routine: setup_net_chip_gmpc
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip_gmpc(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
- CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
- SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-}
-
#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
* Description: reset the Ethernet controller via TPS65930 GPIO
*/
-static void reset_net_chip(void)
+static int cm_t3x_reset_net_chip(int gpio)
{
/* Set GPIO1 of TPS65930 as output */
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
0x02);
mdelay(1);
+ return 0;
}
#else
-static inline void reset_net_chip(void) {}
+static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
#endif
#ifdef CONFIG_SMC911X
return eth_setenv_enetaddr("ethaddr", enetaddr);
}
-
/*
* Routine: board_eth_init
* Description: initialize module and base-board Ethernet chips
{
int rc = 0, rc1 = 0;
- setup_net_chip_gmpc();
- reset_net_chip();
-
rc1 = handle_mac_address();
if (rc1)
printf("No MAC address found! ");
- rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
+ rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE,
+ cm_t3x_reset_net_chip, -EINVAL);
if (rc1 > 0)
rc++;
- rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
+ rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
if (rc1 > 0)
rc++;
}
#endif
-void __weak get_board_serial(struct tag_serialnr *serialnr)
-{
- /*
- * This corresponds to what happens when we can communicate with the
- * eeprom but don't get a valid board serial value.
- */
- serialnr->low = 0;
- serialnr->high = 0;
-};
-
#ifdef CONFIG_USB_EHCI_OMAP
struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
#define SB_T35_USB_HUB_RESET_GPIO 167
int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u8 val;
int offset;
- if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
- printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
- SB_T35_USB_HUB_RESET_GPIO);
- return -1;
- }
-
- gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
- udelay(10);
- gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
- udelay(1000);
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
int ehci_hcd_stop(void)
{
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI_OMAP */
--- /dev/null
+if TARGET_CM_T3517
+
+config SYS_BOARD
+ default "cm_t3517"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "cm_t3517"
+
+endif
--- /dev/null
+CM_T3517 BOARD
+M: Igor Grinberg <grinberg@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_t3517/
+F: include/configs/cm_t3517.h
+F: configs/cm_t3517_defconfig
--- /dev/null
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cm_t3517.o mux.o
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <mmc.h>
+#include <linux/compiler.h>
+#include <linux/usb/musb.h>
+
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/am35x_def.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/ehci-omap.h>
+
+#include "../common/common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CM-T3517 board",
+ "NAND 128/512M",
+};
+
+#ifdef CONFIG_USB_MUSB_AM35X
+static struct musb_hdrc_config cm_t3517_musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct omap_musb_board_data cm_t3517_musb_board_data = {
+ .set_phy_power = am35x_musb_phy_power,
+ .clear_irq = am35x_musb_clear_irq,
+ .reset = am35x_musb_reset,
+};
+
+static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+ .mode = MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+ .config = &cm_t3517_musb_config,
+ .power = 250,
+ .platform_ops = &am35x_ops,
+ .board_data = &cm_t3517_musb_board_data,
+};
+
+static void cm_t3517_musb_init(void)
+{
+ /*
+ * Set up USB clock/mode in the DEVCONF2 register.
+ * USB2.0 PHY reference clock is 13 MHz
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
+ CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
+ CONF2_VBDTCTEN | CONF2_DATPOL);
+
+ if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
+ (void *)AM35XX_IPSS_USBOTGSS_BASE))
+ printf("Failed initializing AM35x MUSB!\n");
+}
+#else
+static inline void am3517_evm_musb_init(void) {}
+#endif
+
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+ cm_t3517_musb_init();
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ cl_print_pcb_info();
+ dieid_num_r();
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_CD_GPIO 144
+#define SB_T35_WP_GPIO 59
+
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONTROL_EFUSE_EMAC_LSB 0x48002380
+#define CONTROL_EFUSE_EMAC_MSB 0x48002384
+
+static int am3517_get_efuse_enetaddr(u8 *enetaddr)
+{
+ u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
+ u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
+
+ enetaddr[0] = (u8)((msb >> 16) & 0xff);
+ enetaddr[1] = (u8)((msb >> 8) & 0xff);
+ enetaddr[2] = (u8)(msb & 0xff);
+ enetaddr[3] = (u8)((lsb >> 16) & 0xff);
+ enetaddr[4] = (u8)((lsb >> 8) & 0xff);
+ enetaddr[5] = (u8)(lsb & 0xff);
+
+ return is_valid_ether_addr(enetaddr);
+}
+
+static inline int cm_t3517_init_emac(bd_t *bis)
+{
+ int ret = cpu_eth_init(bis);
+
+ if (ret > 0)
+ return ret;
+
+ printf("Failed initializing EMAC! ");
+ return 0;
+}
+#else /* !CONFIG_DRIVER_TI_EMAC */
+static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
+static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int cm_t3517_handle_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int ret;
+
+ ret = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return 0;
+
+ ret = cl_eeprom_read_mac_addr(enetaddr);
+ if (ret) {
+ ret = am3517_get_efuse_enetaddr(enetaddr);
+ if (ret)
+ return ret;
+ }
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define SB_T35_ETH_RST_GPIO 164
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0, rc1 = 0;
+
+ rc1 = cm_t3517_handle_mac_address();
+ if (rc1)
+ printf("No MAC address found! ");
+
+ rc1 = cm_t3517_init_emac(bis);
+ if (rc1 > 0)
+ rc++;
+
+ rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
+ NULL, SB_T35_ETH_RST_GPIO);
+ if (rc1 > 0)
+ rc++;
+
+ return rc;
+}
+
+#ifdef CONFIG_USB_EHCI_OMAP
+static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define CM_T3517_USB_HUB_RESET_GPIO 152
+#define SB_T35_USB_HUB_RESET_GPIO 98
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
+
+ return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+ cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
+
+ return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI_OMAP */
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+void set_muxconf_regs(void)
+{
+ /* SDRC */
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
+
+ /* GPMC */
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+
+ /* SB-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
+ /* DVI enable */
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
+ /* DataImage backlight */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
+
+ /* SB-T35 SD/MMC WP GPIO59 */
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ /* SB-T35 Audio Enable GPIO61 */
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
+ /* SB-T35 Ethernet IRQ GPIO65 */
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
+
+ /* UART3 Console */
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
+ /* RTC V3020 nCS GPIO163 */
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
+ /* SB-T35 Ethernet nRESET GPIO164 */
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
+
+ /* SB-T35 SD/MMC CD GPIO144 */
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
+ /* WIFI nRESET GPIO145 */
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
+ /* USB1 PHY Reset GPIO 146 */
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
+ /* USB2 PHY Reset GPIO 147 */
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
+
+ /* MMC1 */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+
+ /* DSS */
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
+
+ /* I2C */
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+
+ /* SB-T35 USB HUB Reset GPIO98 */
+ MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
+ /* CM-T3517 USB HUB Reset GPIO152 */
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
+
+ /* RMII */
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0));
+ MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
+ MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
+ MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
+
+ /* Green LED GPIO186 */
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
+
+ /* SPI */
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
+ /* LCD reset GPIO157 */
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
+
+ /* RTC V3020 CS Enable GPIO160 */
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
+ /* SB-T35 LVDS Transmitter SHDN GPIO162 */
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
+
+ /* USB0 - mUSB */
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
+ /* USB1 EHCI */
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+ /* USB2 EHCI */
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
+ /* SYS_BOOT */
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
+}
#define SB_T54_CD_GPIO 228
#define SB_T54_WP_GPIO 229
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !gpio_get_value(SB_T54_CD_GPIO);
-}
-
int board_mmc_init(bd_t *bis)
{
int ret0, ret1;
- ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO);
+ ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO);
if (ret0)
printf("cm_t54: failed to initialize mmc0\n");
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SYS_I2C) += eeprom.o
-obj-$(CONFIG_LCD) += omap3_display.o
+obj-y += common.o
+obj-$(CONFIG_SYS_I2C) += eeprom.o
+obj-$(CONFIG_LCD) += omap3_display.o
+obj-$(CONFIG_SPLASH_SCREEN) += splash.o
+obj-$(CONFIG_SMC911X) += omap3_smc911x.o
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+#include "eeprom.h"
+
+void cl_print_pcb_info(void)
+{
+ u32 board_rev = get_board_rev();
+ u32 rev_major = board_rev / 100;
+ u32 rev_minor = board_rev - (rev_major * 100);
+
+ if ((rev_minor / 10) * 10 == rev_minor)
+ rev_minor = rev_minor / 10;
+
+ printf("PCB: %u.%u\n", rev_major, rev_minor);
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void __weak get_board_serial(struct tag_serialnr *serialnr)
+{
+ /*
+ * This corresponds to what happens when we can communicate with the
+ * eeprom but don't get a valid board serial value.
+ */
+ serialnr->low = 0;
+ serialnr->high = 0;
+};
+#endif
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label)
+{
+ if (gpio_request(gpio, label)) {
+ printf("Error: can't obtain GPIO%d for %s", gpio, label);
+ return -1;
+ }
+
+ gpio_direction_output(gpio, 0);
+ udelay(10);
+ gpio_set_value(gpio, 1);
+ udelay(1000);
+ return 0;
+}
+
+void cl_usb_hub_deinit(int gpio)
+{
+ gpio_free(gpio);
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CL_COMMON_
+#define _CL_COMMON_
+
+#include <asm/errno.h>
+
+void cl_print_pcb_info(void);
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label);
+void cl_usb_hub_deinit(int gpio);
+#else /* !CONFIG_CMD_USB */
+static inline int cl_usb_hub_init(int gpio, const char *label)
+{
+ return -ENOSYS;
+}
+static inline void cl_usb_hub_deinit(int gpio) {}
+#endif /* CONFIG_CMD_USB */
+
+#ifdef CONFIG_SPLASH_SCREEN
+int cl_splash_screen_prepare(int nand_offset);
+#else /* !CONFIG_SPLASH_SCREEN */
+static inline int cl_splash_screen_prepare(int nand_offset)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#ifdef CONFIG_SMC911X
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio);
+#else /* !CONFIG_SMC911X */
+static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_SMC911X */
+
+#endif /* _CL_COMMON_ */
return cl_eeprom_read(offset, buf, 6);
}
+static u32 board_rev;
+
/*
* Routine: cl_eeprom_get_board_rev
* Description: read system revision from eeprom
*/
u32 cl_eeprom_get_board_rev(void)
{
- u32 rev = 0;
char str[5]; /* Legacy representation can contain at most 4 digits */
uint offset = BOARD_REV_OFFSET_LEGACY;
+ if (board_rev)
+ return board_rev;
+
if (cl_eeprom_setup_layout())
return 0;
if (cl_eeprom_layout != LAYOUT_LEGACY)
offset = BOARD_REV_OFFSET;
- if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
+ if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE))
return 0;
/*
* representation. i.e. for rev 1.00: 0x100 --> 0x64
*/
if (cl_eeprom_layout == LAYOUT_LEGACY) {
- sprintf(str, "%x", rev);
- rev = simple_strtoul(str, NULL, 10);
+ sprintf(str, "%x", board_rev);
+ board_rev = simple_strtoul(str, NULL, 10);
}
- return rev;
+ return board_rev;
};
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+
+static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = {
+ NET_GPMC_CONFIG1,
+ NET_GPMC_CONFIG2,
+ NET_GPMC_CONFIG3,
+ NET_GPMC_CONFIG4,
+ NET_GPMC_CONFIG5,
+ NET_GPMC_CONFIG6,
+ 0
+};
+
+static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config,
+ &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_OMAP_GPIO
+static int cl_omap3_smc911x_reset_net_chip(int gpio)
+{
+ int err;
+
+ if (!gpio_is_valid(gpio))
+ return -EINVAL;
+
+ err = gpio_request(gpio, "eth rst");
+ if (err)
+ return err;
+
+ /* Set gpio as output and send a pulse */
+ gpio_direction_output(gpio, 1);
+ udelay(1);
+ gpio_set_value(gpio, 0);
+ mdelay(40);
+ gpio_set_value(gpio, 1);
+ mdelay(1);
+
+ return 0;
+}
+#else /* !CONFIG_OMAP_GPIO */
+static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; }
+#endif /* CONFIG_OMAP_GPIO */
+
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio)
+{
+ int ret;
+
+ cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr);
+
+ if (reset)
+ reset(rst_gpio);
+ else
+ cl_omap3_smc911x_reset_net_chip(rst_gpio);
+
+ ret = smc911x_initialize(id, base_addr);
+ if (ret > 0)
+ return ret;
+
+ printf("Failed initializing SMC911x! ");
+ return 0;
+}
--- /dev/null
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <bmp_layout.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+ struct bmp_header *bmp_hdr;
+ int res;
+ size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
+
+ if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
+ goto splash_address_too_high;
+
+ res = nand_read_skip_bad(&nand_info[nand_curr_device],
+ nand_offset, &bmp_header_size,
+ NULL, nand_info[nand_curr_device].size,
+ (u_char *)bmp_load_addr);
+ if (res < 0)
+ return res;
+
+ bmp_hdr = (struct bmp_header *)bmp_load_addr;
+ bmp_size = le32_to_cpu(bmp_hdr->file_size);
+
+ if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
+ goto splash_address_too_high;
+
+ return nand_read_skip_bad(&nand_info[nand_curr_device],
+ nand_offset, &bmp_size,
+ NULL, nand_info[nand_curr_device].size,
+ (u_char *)bmp_load_addr);
+
+splash_address_too_high:
+ printf("Error: splashimage address too high. Data overwrites U-Boot "
+ "and/or placed beyond DRAM boundaries.\n");
+
+ return -1;
+}
+#else
+static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+ return -1;
+}
+#endif /* CONFIG_CMD_NAND */
+
+int cl_splash_screen_prepare(int nand_offset)
+{
+ char *env_splashimage_value;
+ u32 bmp_load_addr;
+
+ env_splashimage_value = getenv("splashimage");
+ if (env_splashimage_value == NULL)
+ return -1;
+
+ bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
+ if (bmp_load_addr == 0) {
+ printf("Error: bad splashimage address specified\n");
+ return -1;
+ }
+
+ return splash_load_from_nand(bmp_load_addr, nand_offset);
+}
if TARGET_DBAU1X00
-config SYS_CPU
- default "mips32"
-
config SYS_BOARD
default "dbau1x00"
config SYS_CONFIG_NAME
default "dbau1x00"
+menu "dbau1x00 board options"
+
+choice
+ prompt "Select au1x00 SoC type"
+
+config DBAU1100
+ bool "Select AU1100"
+
+config DBAU1500
+ bool "Select AU1500"
+
+config DBAU1550
+ bool "Select AU1550"
+
+endchoice
+
+endmenu
+
endif
{
block_dev_desc_t *stor_dev = NULL;
long sz;
- int i, res, cnt, old_ctrlc;
+ int i, res, old_ctrlc;
char buffer[32];
char str[80];
int n;
clear_ctrlc ();
break;
}
- cnt++;
} while (res < 0);
}
*/
int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned int *ptr = 0;
+ unsigned int *ptr;
int count = 0;
int count2 = 0;
int i;
* Mark sync address
*/
ptr = 0;
+ /* cppcheck-suppress nullPointer */
*ptr = 0xffffffff;
puts("\nWaiting for image from pci host -");
/*
* Wait for host to write the start address
*/
+ /* cppcheck-suppress nullPointer */
while (*ptr == 0xffffffff) {
count++;
if (!(count % 100)) {
FREESCALE MX28EVK
==================
-Supported hardware: only MX28EVK rev D is supported in U-boot.
+Supported hardware: MX28EVK rev C and D are supported in U-boot.
Files of the MX28EVK port
--------------------------
if (!p)
return -ENODEV;
+ setenv("fdt_file", "imx53-qsb.dtb");
+
/* Set VDDA to 1.25V */
val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
if (!p)
return -ENODEV;
+ setenv("fdt_file", "imx53-qsrb.dtb");
+
/* Set VDDGP to 1.25V for 1GHz on SW1 */
pmic_reg_read(p, REG_SW_0, &val);
val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
#include <asm/arch/mxc_hdmi.h>
#include <asm/imx-common/video.h>
#include <asm/arch/crm_regs.h>
+#include <pca953x.h>
DECLARE_GLOBAL_DATA_PTR;
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
int dram_init(void)
MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+/*Define for building port exp gpio, pin starts from 0*/
+#define PORTEXP_IO_NR(chip, pin) \
+ ((chip << 5) + pin)
+
+/*Get the chip addr from a ioexp gpio*/
+#define PORTEXP_IO_TO_CHIP(gpio_nr) \
+ (gpio_nr >> 5)
+
+/*Get the pin number from a ioexp gpio*/
+#define PORTEXP_IO_TO_PIN(gpio_nr) \
+ (gpio_nr & 0x1f)
+
+static int port_exp_direction_output(unsigned gpio, int value)
+{
+ int ret;
+
+ i2c_set_bus_num(2);
+ ret = i2c_probe(PORTEXP_IO_TO_CHIP(gpio));
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_dir(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (PCA953X_DIR_OUT << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ ret = pca953x_set_val(PORTEXP_IO_TO_CHIP(gpio),
+ (1 << PORTEXP_IO_TO_PIN(gpio)),
+ (value << PORTEXP_IO_TO_PIN(gpio)));
+
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
}
#endif
+#ifdef CONFIG_NAND_MXS
+static iomux_v3_cfg_t gpmi_pads[] = {
+ MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
+ MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+ MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
+
+ /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+ clrbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable ENFC_CLK_ROOT clock */
+ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
int mx6_rgmii_rework(struct phy_device *phydev)
{
unsigned short val;
#ifdef CONFIG_VIDEO_IPUV3
setup_display();
#endif
+
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
return 0;
}
return 0;
}
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_HOST1_PWR PORTEXP_IO_NR(0x32, 7)
+#define USB_OTG_PWR PORTEXP_IO_NR(0x34, 1)
+
+iomux_v3_cfg_t const usb_otg_pads[] = {
+ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ ARRAY_SIZE(usb_otg_pads));
+
+ /*
+ * Set daisy chain for otg_pin_id on 6q.
+ * For 6dl, this bit is reserved.
+ */
+ imx_iomux_set_gpr_register(1, 13, 1, 0);
+ break;
+ case 1:
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ switch (port) {
+ case 0:
+ if (on)
+ port_exp_direction_output(USB_OTG_PWR, 1);
+ else
+ port_exp_direction_output(USB_OTG_PWR, 0);
+ break;
+ case 1:
+ if (on)
+ port_exp_direction_output(USB_HOST1_PWR, 1);
+ else
+ port_exp_direction_output(USB_HOST1_PWR, 0);
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#endif
#include <i2c.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
+#include <asm/arch/mx6-ddr.h>
+
DECLARE_GLOBAL_DATA_PTR;
+#define BOOT_CFG 0x020D8004
+
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
+
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
+ gd->ram_size = imx_ddr_size();
return 0;
}
-iomux_v3_cfg_t const uart1_pads[] = {
+static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-iomux_v3_cfg_t const enet_pads[] = {
+static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}
-iomux_v3_cfg_t const usdhc2_pads[] = {
+static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
-iomux_v3_cfg_t const usdhc3_pads[] = {
+static iomux_v3_cfg_t const usdhc3_pads[] = {
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
-iomux_v3_cfg_t const usdhc4_pads[] = {
+static iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-iomux_v3_cfg_t const ecspi1_pads[] = {
+static iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+static iomux_v3_cfg_t const rgb_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void enable_rgb(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
+ gpio_direction_output(DISP0_PWR_EN, 1);
+}
+
static struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
int board_mmc_init(bd_t *bis)
{
- s32 status = 0;
+#ifndef CONFIG_SPL_BUILD
+ int ret;
int i;
/*
printf("Warning: you configured more USDHC controllers"
"(%d) then supported by the board (%d)\n",
i + 1, CONFIG_SYS_FSL_USDHC_NUM);
- return status;
+ return -EINVAL;
}
- status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+#else
+ unsigned reg = readl(BOOT_CFG) >> 11;
+ /*
+ * Upon reading BOOT_CFG register the following map is done:
+ * Bit 11 and 12 of BOOT_CFG register can determine the current
+ * mmc port
+ * 0x1 SD1
+ * 0x2 SD2
+ * 0x3 SD4
+ */
+
+ switch (reg & 0x3) {
+ case 0x1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
+ case 0x3:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+ break;
}
- return status;
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
}
#endif
.vsync_len = 10,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = 0,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_rgb,
+ .mode = {
+ .name = "SEIKO-WVGA",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = 29850,
+ .left_margin = 89,
+ .right_margin = 164,
+ .upper_margin = 23,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);
puts("Board: MX6-SabreSD\n");
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+
+const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
+ .dram_sdclk_0 = 0x00020030,
+ .dram_sdclk_1 = 0x00020030,
+ .dram_cas = 0x00020030,
+ .dram_ras = 0x00020030,
+ .dram_reset = 0x00020030,
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+ .dram_dqm0 = 0x00020030,
+ .dram_dqm1 = 0x00020030,
+ .dram_dqm2 = 0x00020030,
+ .dram_dqm3 = 0x00020030,
+ .dram_dqm4 = 0x00020030,
+ .dram_dqm5 = 0x00020030,
+ .dram_dqm6 = 0x00020030,
+ .dram_dqm7 = 0x00020030,
+};
+
+const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
+ .grp_ddr_type = 0x000C0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = 0x00000030,
+ .grp_ctlds = 0x00000030,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_b4ds = 0x00000030,
+ .grp_b5ds = 0x00000030,
+ .grp_b6ds = 0x00000030,
+ .grp_b7ds = 0x00000030,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+ .p0_mpwldectrl0 = 0x001F001F,
+ .p0_mpwldectrl1 = 0x001F001F,
+ .p1_mpwldectrl0 = 0x00440044,
+ .p1_mpwldectrl1 = 0x00440044,
+ .p0_mpdgctrl0 = 0x434B0350,
+ .p0_mpdgctrl1 = 0x034C0359,
+ .p1_mpdgctrl0 = 0x434B0350,
+ .p1_mpdgctrl1 = 0x03650348,
+ .p0_mprddlctl = 0x4436383B,
+ .p1_mprddlctl = 0x39393341,
+ .p0_mpwrdlctl = 0x35373933,
+ .p1_mpwrdlctl = 0x48254A36,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 64,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/*
+ * This section require the differentiation
+ * between iMX6 Sabre Families.
+ * But for now, it will configure only for
+ * SabreSD.
+ */
+static void spl_dram_init(void)
+{
+ struct mx6_ddr_sysinfo sysinfo = {
+ /* width of data bus:0=16,1=32,2=64 */
+ .dsize = mem_ddr.width/32,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
+#ifdef RTT_NOM_120OHM
+ .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
+#else
+ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
+#endif
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ /* 8 bit SD */
+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ /*CD pin*/
+ MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const fec_pads[] = {
gpio_set_value(ETH_PHY_RESET, 1);
}
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
- {USDHC2_BASE_ADDR},
+#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
+#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC1_BASE_ADDR},
+ {USDHC2_BASE_ADDR, 0, 4},
+ {USDHC3_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
- return 1; /* Assume boot SD always present */
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = !gpio_get_value(USDHC1_CD_GPIO);
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ }
+
+ return ret;
}
int board_mmc_init(bd_t *bis)
{
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ int i, ret;
+
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ * mmc2 USDHC3
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_direction_input(USDHC1_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret) {
+ printf("Warning: failed to initialize "
+ "mmc dev %d\n", i);
+ return ret;
+ }
+ }
- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+ return 0;
}
#ifdef CONFIG_FEC_MXC
if TARGET_GR_CPCI_AX2000
-config SYS_CPU
- default "leon3"
-
config SYS_BOARD
default "gr_cpci_ax2000"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "gr_cpci_ax2000"
+++ /dev/null
-#
-# (C) Copyright 2008
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# GR-CPCI-AX2000 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM or SDRAM with -nosram flag set when starting GRMON
-#CONFIG_SYS_TEXT_BASE = 0x40000000
-
-# U-BOOT IN SDRAM
-#CONFIG_SYS_TEXT_BASE = 0x60000000
if TARGET_GR_EP2S60
-config SYS_CPU
- default "leon3"
-
config SYS_BOARD
default "gr_ep2s60"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "gr_ep2s60"
+++ /dev/null
-#
-# (C) Copyright 2008
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# Altera NIOS delopment board Stratix II edition, FPGA device EP2S60,
-# with GRLIB Template design (GPL Open Source SPARC/LEON3)
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN SDRAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
if TARGET_GR_XC3S_1500
-config SYS_CPU
- default "leon3"
-
config SYS_BOARD
default "gr_xc3s_1500"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "gr_xc3s_1500"
+++ /dev/null
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# GR-XC3S-1500 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
if TARGET_GRSIM
-config SYS_CPU
- default "leon3"
-
config SYS_BOARD
default "grsim"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "grsim"
+++ /dev/null
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# GRSIM simulating a LEON3 GR-XC3S-1500 board
-#
-
-# U-BOOT IN FLASH
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# U-BOOT IN RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
if TARGET_GRSIM_LEON2
-config SYS_CPU
- default "leon2"
-
config SYS_BOARD
default "grsim_leon2"
-config SYS_VENDOR
- default "gaisler"
-
config SYS_CONFIG_NAME
default "grsim_leon2"
+++ /dev/null
-#
-# (C) Copyright 2007
-# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# GRSIM simulating a LEON2 board
-#
-
-# RUN U-BOOT FROM PROM
-CONFIG_SYS_TEXT_BASE = 0x00000000
-
-# RUN U-BOOT FROM RAM
-#CONFIG_SYS_TEXT_BASE = 0x40000000
if TARGET_MALTA
-config SYS_CPU
- default "mips32"
-
config SYS_BOARD
default "malta"
testboot = (testpin != 0) && (s);
if (verbose) {
printf("testpin = %d\n", testpin);
+ /* cppcheck-suppress nullPointer */
printf("test_bank = %s\n", s ? s : "not set");
printf("boot test app : %s\n", (testboot) ? "yes" : "no");
}
--- /dev/null
+if TARGET_KOSAGI_NOVENA
+
+config SYS_BOARD
+ default "novena"
+
+config SYS_VENDOR
+ default "kosagi"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "novena"
+
+endif
--- /dev/null
+NOVENA BOARD
+M: Marek Vasut <marex@denx.de>
+S: Maintained
+F: board/kosagi/novena/
+F: include/configs/novena.h
+F: configs/novena_defconfig
--- /dev/null
+#
+# Copyright (C) 2014 Marek Vasut <marex@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y := novena_spl.o
+else
+obj-y := novena.o
+endif
--- /dev/null
+/*
+ * Novena board support
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/video.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <input.h>
+#include <ipu_pixfmt.h>
+#include <linux/fb.h>
+#include <linux/input.h>
+#include <malloc.h>
+#include <micrel.h>
+#include <miiphy.h>
+#include <mmc.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <stdio_dev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define NOVENA_BUTTON_GPIO IMX_GPIO_NR(4, 14)
+#define NOVENA_SD_WP IMX_GPIO_NR(1, 2)
+#define NOVENA_SD_CD IMX_GPIO_NR(1, 4)
+
+/*
+ * GPIO button
+ */
+#ifdef CONFIG_KEYBOARD
+static struct input_config button_input;
+
+static int novena_gpio_button_read_keys(struct input_config *input)
+{
+ int key = KEY_ENTER;
+ if (gpio_get_value(NOVENA_BUTTON_GPIO))
+ return 0;
+ input_send_keycodes(&button_input, &key, 1);
+ return 1;
+}
+
+static int novena_gpio_button_getc(struct stdio_dev *dev)
+{
+ return input_getc(&button_input);
+}
+
+static int novena_gpio_button_tstc(struct stdio_dev *dev)
+{
+ return input_tstc(&button_input);
+}
+
+static int novena_gpio_button_init(struct stdio_dev *dev)
+{
+ gpio_direction_input(NOVENA_BUTTON_GPIO);
+ input_set_delays(&button_input, 250, 250);
+ return 0;
+}
+
+int drv_keyboard_init(void)
+{
+ int error;
+ struct stdio_dev dev = {
+ .name = "button",
+ .flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM,
+ .start = novena_gpio_button_init,
+ .getc = novena_gpio_button_getc,
+ .tstc = novena_gpio_button_tstc,
+ };
+
+ error = input_init(&button_input, 0);
+ if (error) {
+ debug("%s: Cannot set up input\n", __func__);
+ return -1;
+ }
+ button_input.read_keys = novena_gpio_button_read_keys;
+
+ error = input_stdio_register(&dev);
+ if (error)
+ return error;
+
+ return 0;
+}
+#endif
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+ { USDHC3_BASE_ADDR, 0, 4 }, /* Micro SD */
+ { USDHC2_BASE_ADDR, 0, 4 }, /* Big SD */
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ /* There is no CD for a microSD card, assume always present. */
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ return 1;
+ else
+ return !gpio_get_value(NOVENA_SD_CD);
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ /* There is no WP for a microSD card, assume always read-write. */
+ if (cfg->esdhc_base == USDHC3_BASE_ADDR)
+ return 0;
+ else
+ return gpio_get_value(NOVENA_SD_WP);
+}
+
+
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+ int index;
+
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+ /* Big SD write-protect and card-detect */
+ gpio_direction_input(NOVENA_SD_WP);
+ gpio_direction_input(NOVENA_SD_CD);
+
+ for (index = 0; index < ARRAY_SIZE(usdhc_cfg); index++) {
+ status = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+ if (status)
+ return status;
+ }
+
+ return status;
+}
+#endif
+
+/*
+ * Video over HDMI
+ */
+#if defined(CONFIG_VIDEO_IPUV3)
+static void enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {
+ {
+ /* HDMI Output */
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin = 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ }
+};
+
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* Turn on LDB0,IPU,IPU DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ /* set LDB0, LDB1 clk select to 011/011 */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
+ MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
+ (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
+ (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
+
+ setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+
+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
+ IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+ IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_CMD_SATA
+ setup_sata();
+#endif
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: Novena 4x\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+/* setup board specific PMIC */
+int power_init_board(void)
+{
+ struct pmic *p;
+ u32 reg;
+ int ret;
+
+ power_pfuze100_init(1);
+ p = pmic_get("PFUZE100");
+ if (!p)
+ return -EINVAL;
+
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Set SWBST to 5.0V and enable (for USB) */
+ pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
+ reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
+ reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
+ pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
+
+ return 0;
+}
+
+/* EEPROM configuration data */
+struct novena_eeprom_data {
+ uint8_t signature[6];
+ uint8_t version;
+ uint8_t reserved;
+ uint32_t serial;
+ uint8_t mac[6];
+ uint16_t features;
+};
+
+int misc_init_r(void)
+{
+ struct novena_eeprom_data data;
+ uchar *datap = (uchar *)&data;
+ const char *signature = "Novena";
+ int ret;
+
+ /* If 'ethaddr' is already set, do nothing. */
+ if (getenv("ethaddr"))
+ return 0;
+
+ /* EEPROM is at bus 2. */
+ ret = i2c_set_bus_num(2);
+ if (ret) {
+ puts("Cannot select EEPROM I2C bus.\n");
+ return 0;
+ }
+
+ /* EEPROM is at address 0x56. */
+ ret = eeprom_read(0x56, 0, datap, sizeof(data));
+ if (ret) {
+ puts("Cannot read I2C EEPROM.\n");
+ return 0;
+ }
+
+ /* Check EEPROM signature. */
+ if (memcmp(data.signature, signature, 6)) {
+ puts("Invalid I2C EEPROM signature.\n");
+ return 0;
+ }
+
+ /* Set ethernet address from EEPROM. */
+ eth_setenv_enetaddr("ethaddr", data.mac);
+
+ return ret;
+}
--- /dev/null
+/*
+ * Novena SPL
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spl.h>
+
+#include <asm/arch/mx6-ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define ENET_PHY_CFG_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
+
+#define RGMII_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL \
+ (PAD_CTL_HYS | \
+ PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE)
+
+#define BUTTON_PAD_CTRL \
+ (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#define NOVENA_AUDIO_PWRON IMX_GPIO_NR(5, 17)
+#define NOVENA_FPGA_RESET_N_GPIO IMX_GPIO_NR(5, 7)
+#define NOVENA_HDMI_GHOST_HPD IMX_GPIO_NR(5, 4)
+#define NOVENA_PCIE_RESET_GPIO IMX_GPIO_NR(3, 29)
+#define NOVENA_PCIE_POWER_ON_GPIO IMX_GPIO_NR(7, 12)
+#define NOVENA_PCIE_WAKE_UP_GPIO IMX_GPIO_NR(3, 22)
+#define NOVENA_PCIE_DISABLE_GPIO IMX_GPIO_NR(2, 16)
+
+/*
+ * Audio
+ */
+static iomux_v3_cfg_t audio_pads[] = {
+ /* AUD_PWRON */
+ MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_audio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
+ gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
+}
+
+/*
+ * ENET
+ */
+static iomux_v3_cfg_t enet_pads1[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+ /* pin 35, PHY_AD2 */
+ MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 32, MODE0 */
+ MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 31, MODE1 */
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 28, MODE2 */
+ MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 27, MODE3 */
+ MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+ /* pin 33, CLK125_EN */
+ MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
+
+ /* pin 42 PHY nRST */
+ MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t enet_pads2[] = {
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+
+ /* Assert Ethernet PHY nRST */
+ gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+
+ /*
+ * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
+ * de-assertion. The intention is to use weak signal drivers (pull-ups)
+ * to prevent the conflict between PHY pins becoming outputs after
+ * reset and imx6 still driving the pins. The issue is described in PHY
+ * datasheet, p.14
+ */
+ gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
+ gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
+
+ /* Following reset timing (p.53, fig.8 from the PHY datasheet) */
+ mdelay(10);
+
+ /* De-assert Ethernet PHY nRST */
+ gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+
+ /* PHY is now configured, connect FEC to the pads */
+ imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+
+ /*
+ * PHY datasheet recommends on p.53 to wait at least 100us after reset
+ * before using MII, so we enforce the delay here
+ */
+ udelay(100);
+}
+
+/*
+ * FPGA
+ */
+static iomux_v3_cfg_t fpga_pads[] = {
+ /* FPGA_RESET_N */
+ MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_fpga(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
+ gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
+}
+
+/*
+ * GPIO Button
+ */
+static iomux_v3_cfg_t button_pads[] = {
+ /* Debug */
+ MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_buttons(void)
+{
+ imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
+}
+
+/*
+ * I2C
+ */
+/*
+ * I2C1:
+ * 0x1d ... MMA7455L
+ * 0x30 ... SO-DIMM temp sensor
+ * 0x44 ... STMPE610
+ * 0x50 ... SO-DIMM ID
+ */
+struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+/*
+ * I2C2:
+ * 0x08 ... PMIC
+ * 0x3a ... HDMI DCC
+ * 0x50 ... HDMI DCC
+ */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
+ .gp = IMX_GPIO_NR(2, 30)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
+ .gp = IMX_GPIO_NR(3, 16)
+ }
+};
+
+/*
+ * I2C3:
+ * 0x11 ... ES8283
+ * 0x50 ... LCD EDID
+ * 0x56 ... EEPROM
+ */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+static void novena_spl_setup_iomux_i2c(void)
+{
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+}
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+static iomux_v3_cfg_t pcie_pads[] = {
+ /* "Reset" pin */
+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Power on" pin */
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Wake up" pin (input) */
+ MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* "Disable endpoint" (rfkill) pin */
+ MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+
+ /* Ensure PCIe is powered down */
+ gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
+
+ /* Put the card into reset */
+ gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
+
+ /* Input signal to wake system from mPCIe card */
+ gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
+
+ /* Drive RFKILL high, to ensure the radio is turned on */
+ gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
+}
+#else
+static inline void novena_spl_setup_iomux_pcie(void) {}
+#endif
+
+/*
+ * SDHC
+ */
+static iomux_v3_cfg_t usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_sdhc(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ /* Big SD write-protect and card-detect */
+ gpio_direction_input(IMX_GPIO_NR(1, 2));
+ gpio_direction_input(IMX_GPIO_NR(1, 4));
+}
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_MXC_SPI
+static iomux_v3_cfg_t ecspi3_pads[] = {
+ /* SS1 */
+ MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_spi(void)
+{
+ imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+ /* De-assert the nCS */
+ gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
+ gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
+ gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
+}
+#else
+static void novena_spl_setup_iomux_spi(void) {}
+#endif
+
+/*
+ * UART
+ */
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart3_pads[] = {
+ MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+
+};
+
+static void novena_spl_setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+/*
+ * Video
+ */
+#ifdef CONFIG_VIDEO
+static iomux_v3_cfg_t hdmi_pads[] = {
+ /* "Ghost HPD" pin */
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void novena_spl_setup_iomux_video(void)
+{
+ imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
+ gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
+}
+#else
+static inline void novena_spl_setup_iomux_video(void) {}
+#endif
+
+/*
+ * SPL boots from uSDHC card
+ */
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg = {
+ USDHC3_BASE_ADDR, 0, 4
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ /* There is no CD for a microSD card, assume always present. */
+ return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+#endif
+
+/* Configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = 0x00020038,
+ .dram_sdclk_1 = 0x00020038,
+ .dram_cas = 0x00000038,
+ .dram_ras = 0x00000038,
+ .dram_reset = 0x00000038,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00000038,
+ .dram_sdodt1 = 0x00000038,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = 0x00000038,
+ .dram_sdqs1 = 0x00000038,
+ .dram_sdqs2 = 0x00000038,
+ .dram_sdqs3 = 0x00000038,
+ .dram_sdqs4 = 0x00000038,
+ .dram_sdqs5 = 0x00000038,
+ .dram_sdqs6 = 0x00000038,
+ .dram_sdqs7 = 0x00000038,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = 0x00000038,
+ .dram_dqm1 = 0x00000038,
+ .dram_dqm2 = 0x00000038,
+ .dram_dqm3 = 0x00000038,
+ .dram_dqm4 = 0x00000038,
+ .dram_dqm5 = 0x00000038,
+ .dram_dqm6 = 0x00000038,
+ .dram_dqm7 = 0x00000038,
+};
+
+/* Configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ /* Disable DDR pullups */
+ .grp_ddrpke = 0x00000000,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = 0x00000038,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = 0x00000038,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000038,
+ .grp_b1ds = 0x00000038,
+ .grp_b2ds = 0x00000038,
+ .grp_b3ds = 0x00000038,
+ .grp_b4ds = 0x00000038,
+ .grp_b5ds = 0x00000038,
+ .grp_b6ds = 0x00000038,
+ .grp_b7ds = 0x00000038,
+};
+
+static struct mx6_mmdc_calibration novena_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00420048,
+ .p0_mpwldectrl1 = 0x006f0059,
+ .p1_mpwldectrl0 = 0x005a0104,
+ .p1_mpwldectrl1 = 0x01070113,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x437c040b,
+ .p0_mpdgctrl1 = 0x0413040e,
+ .p1_mpdgctrl0 = 0x444f0446,
+ .p1_mpdgctrl1 = 0x044d0422,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x4c424249,
+ .p1_mprddlctl = 0x4e48414f,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x42414641,
+ .p1_mpwrdlctl = 0x46374b43,
+};
+
+static struct mx6_ddr_sysinfo novena_ddr_info = {
+ /* Width of data bus: 0=16, 1=32, 2=64 */
+ .dsize = 2,
+ /* Config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* Single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1, /* RTT_Wr = RZQ/4 */
+ .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
+ .walat = 3, /* Write additional latency */
+ .ralat = 7, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+};
+
+static struct mx6_ddr3_cfg elpida_4gib_1600 = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 64,
+ .banks = 8,
+ .rowaddr = 16,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1300,
+ .trcmin = 4900,
+ .trasmin = 3590,
+};
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* setup GP timer */
+ timer_init();
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+ board_postclk_init();
+#endif
+#ifdef CONFIG_FSL_ESDHC
+ get_clocks();
+#endif
+
+ /* Setup IOMUX and configure basics. */
+ novena_spl_setup_iomux_audio();
+ novena_spl_setup_iomux_buttons();
+ novena_spl_setup_iomux_enet();
+ novena_spl_setup_iomux_fpga();
+ novena_spl_setup_iomux_i2c();
+ novena_spl_setup_iomux_pcie();
+ novena_spl_setup_iomux_sdhc();
+ novena_spl_setup_iomux_spi();
+ novena_spl_setup_iomux_uart();
+ novena_spl_setup_iomux_video();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* Start the DDR DRAM */
+ mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
+ mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
--- /dev/null
+/*
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/* Boot Device : sd */
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00C03F3F
+DATA 4, CCM_CCGR1, 0x0030FC03
+DATA 4, CCM_CCGR2, 0x0FFFC000
+DATA 4, CCM_CCGR3, 0x3FF00000
+DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
+DATA 4, CCM_CCGR5, 0x0F0000C3
+DATA 4, CCM_CCGR6, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en = 1 --> CKO1 enabled
+ * cko1_div = 111 --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4, CCM_CCOSR, 0x000000fb
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = mv_common.o
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <environment.h>
-#include <fpga.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_ENV_IS_NOWHERE
-static char* entries_to_keep[] = {
- "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
- "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
- "static_ipaddr", "static_netmask", "static_gateway",
- "syslog", "watchdog", "netboot", "evo8serialnumber" };
-
-#define MV_MAX_ENV_ENTRY_LENGTH 64
-#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
-
-void mv_reset_environment(void)
-{
- int i;
- char *s[MV_KEEP_ENTRIES];
- char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH];
-
- printf("\n*** RESET ENVIRONMENT ***\n");
-
- memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH);
- for (i = 0; i < MV_KEEP_ENTRIES; i++) {
- s[i] = getenv(entries_to_keep[i]);
- if (s[i]) {
- printf("save '%s' : %s\n", entries_to_keep[i], s[i]);
- strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH);
- }
- }
-
- gd->env_valid = 0;
- env_relocate();
-
- for (i = 0; i < MV_KEEP_ENTRIES; i++) {
- if (s[i]) {
- printf("restore '%s' : %s\n", entries_to_keep[i], s[i]);
- setenv(entries_to_keep[i], s[i]);
- }
- }
-
- saveenv();
-}
-#endif
-
-int mv_load_fpga(void)
-{
- int result;
- size_t data_size = 0;
- void *fpga_data = NULL;
- char *datastr = getenv("fpgadata");
- char *sizestr = getenv("fpgadatasize");
-
- if (getenv("skip_fpga")) {
- printf("found 'skip_fpga' -> FPGA _not_ loaded !\n");
- return -1;
- }
- printf("loading FPGA\n");
-
- if (datastr)
- fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
- if (sizestr)
- data_size = (size_t)simple_strtoul(sizestr, NULL, 16);
- if (!data_size) {
- printf("fpgadatasize invalid -> FPGA _not_ loaded !\n");
- return -1;
- }
-
- result = fpga_load(0, fpga_data, data_size, BIT_FULL);
- if (!result)
- bootstage_mark(BOOTSTAGE_ID_START);
-
- return result;
-}
-
-u8 *dhcp_vendorex_prep(u8 *e)
-{
- char *ptr;
-
- /* DHCP vendor-class-identifier = 60 */
- if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
- *e++ = 60;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
- /* DHCP_CLIENT_IDENTIFIER = 61 */
- if ((ptr = getenv("dhcp_client_id"))) {
- *e++ = 61;
- *e++ = strlen(ptr);
- while (*ptr)
- *e++ = *ptr++;
- }
-
- return e;
-}
-
-u8 *dhcp_vendorex_proc(u8 *popt)
-{
- return NULL;
-}
+++ /dev/null
-/*
- * Copyright 2008 Matrix Vision GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-
-extern int mv_load_fpga(void);
-extern void mv_reset_environment(void);
if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
- char ethaddr[9];
+ char ethaddr[18];
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
e.mac[0],
if TARGET_MAXBCM
-config SYS_CPU
- string
- default "armv7"
-
config SYS_BOARD
- string
default "maxbcm"
config SYS_SOC
- string
default "armada-xp"
config SYS_CONFIG_NAME
- string
default "maxbcm"
endif
+++ /dev/null
-if TARGET_MCC200
-
-config SYS_BOARD
- default "mcc200"
-
-config SYS_CONFIG_NAME
- default "mcc200"
-
-endif
+++ /dev/null
-MCC200 BOARD
-#M: -
-S: Maintained
-F: board/mcc200/
-F: include/configs/mcc200.h
-F: configs/mcc200_defconfig
-F: configs/mcc200_COM12_defconfig
-F: configs/mcc200_COM12_highboot_defconfig
-F: configs/mcc200_COM12_highboot_SDRAM_defconfig
-F: configs/mcc200_COM12_SDRAM_defconfig
-F: configs/mcc200_highboot_defconfig
-F: configs/mcc200_highboot_SDRAM_defconfig
-F: configs/mcc200_SDRAM_defconfig
-F: configs/prs200_defconfig
-F: configs/prs200_DDR_defconfig
-F: configs/prs200_highboot_defconfig
-F: configs/prs200_highboot_DDR_defconfig
+++ /dev/null
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mcc200.o lcd.o auto_update.o
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <image.h>
-#include <asm/byteorder.h>
-#include <usb.h>
-#include <part.h>
-
-#ifdef CONFIG_AUTO_UPDATE
-
-#ifndef CONFIG_USB_OHCI
-#error "must define CONFIG_USB_OHCI"
-#endif
-
-#ifndef CONFIG_USB_STORAGE
-#error "must define CONFIG_USB_STORAGE"
-#endif
-
-#ifndef CONFIG_SYS_HUSH_PARSER
-#error "must define CONFIG_SYS_HUSH_PARSER"
-#endif
-
-#if !defined(CONFIG_CMD_FAT)
-#error "must define CONFIG_CMD_FAT"
-#endif
-
-#undef AU_DEBUG
-
-#undef debug
-#ifdef AU_DEBUG
-#define debug(fmt,args...) printf (fmt ,##args)
-#else
-#define debug(fmt,args...)
-#endif /* AU_DEBUG */
-
-/* possible names of files on the USB stick. */
-#define AU_FIRMWARE "u-boot.img"
-#define AU_KERNEL "kernel.img"
-#define AU_ROOTFS "rootfs.img"
-
-struct flash_layout {
- long start;
- long end;
-};
-
-/* layout of the FLASH. ST = start address, ND = end address. */
-#define AU_FL_FIRMWARE_ST 0xfC000000
-#define AU_FL_FIRMWARE_ND 0xfC03FFFF
-#define AU_FL_KERNEL_ST 0xfC0C0000
-#define AU_FL_KERNEL_ND 0xfC1BFFFF
-#define AU_FL_ROOTFS_ST 0xFC1C0000
-#define AU_FL_ROOTFS_ND 0xFCFBFFFF
-
-static int au_usb_stor_curr_dev; /* current device */
-
-/* index of each file in the following arrays */
-#define IDX_FIRMWARE 0
-#define IDX_KERNEL 1
-#define IDX_ROOTFS 2
-
-/* max. number of files which could interest us */
-#define AU_MAXFILES 3
-
-/* pointers to file names */
-char *aufile[AU_MAXFILES] = {
- AU_FIRMWARE,
- AU_KERNEL,
- AU_ROOTFS
-};
-
-/* sizes of flash areas for each file */
-long ausize[AU_MAXFILES] = {
- (AU_FL_FIRMWARE_ND + 1) - AU_FL_FIRMWARE_ST,
- (AU_FL_KERNEL_ND + 1) - AU_FL_KERNEL_ST,
- (AU_FL_ROOTFS_ND + 1) - AU_FL_ROOTFS_ST,
-};
-
-/* array of flash areas start and end addresses */
-struct flash_layout aufl_layout[AU_MAXFILES] = {
- { AU_FL_FIRMWARE_ST, AU_FL_FIRMWARE_ND, },
- { AU_FL_KERNEL_ST, AU_FL_KERNEL_ND, },
- { AU_FL_ROOTFS_ST, AU_FL_ROOTFS_ND, },
-};
-
-ulong totsize;
-
-/* where to load files into memory */
-#define LOAD_ADDR ((unsigned char *)0x00200000)
-
-/* the root file system is the largest image */
-#define MAX_LOADSZ ausize[IDX_ROOTFS]
-
-/*i2c address of the keypad status*/
-#define I2C_PSOC_KEYPAD_ADDR 0x53
-
-/* keypad mask */
-#define KEYPAD_ROW 2
-#define KEYPAD_COL 2
-#define KEYPAD_MASK_LO ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))&0xFF)
-#define KEYPAD_MASK_HI ((1<<(KEYPAD_COL-1+(KEYPAD_ROW*3-3)))>>8)
-
-/* externals */
-extern int fat_register_device(block_dev_desc_t *, int);
-extern int file_fat_detectfs(void);
-extern long file_fat_read(const char *, void *, unsigned long);
-extern int i2c_read (unsigned char, unsigned int, int , unsigned char* , int);
-extern int flash_sect_erase(ulong, ulong);
-extern int flash_sect_protect (int, ulong, ulong);
-extern int flash_write (char *, ulong, ulong);
-extern int u_boot_hush_start(void);
-#ifdef CONFIG_PROGRESSBAR
-extern void show_progress(int, int);
-extern void lcd_puts (char *);
-extern void lcd_enable(void);
-#endif
-
-int au_check_cksum_valid(int idx, long nbytes)
-{
- image_header_t *hdr;
-
- hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- if (nbytes != image_get_image_size (hdr)) {
- printf ("Image %s bad total SIZE\n", aufile[idx]);
- return -1;
- }
- /* check the data CRC */
- if (!image_check_dcrc (hdr)) {
- printf ("Image %s bad data checksum\n", aufile[idx]);
- return -1;
- }
- return 0;
-}
-
-int au_check_header_valid(int idx, long nbytes)
-{
- image_header_t *hdr;
- unsigned long checksum, fsize;
-
- hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- /* check the easy ones first */
-#undef CHECK_VALID_DEBUG
-#ifdef CHECK_VALID_DEBUG
- printf("magic %#x %#x ", image_get_magic (hdr), IH_MAGIC);
- printf("arch %#x %#x ", image_get_arch (hdr), IH_ARCH_ARM);
- printf("size %#x %#lx ", image_get_data_size (hdr), nbytes);
- printf("type %#x %#x ", image_get_type (hdr), IH_TYPE_KERNEL);
-#endif
- if (nbytes < image_get_header_size ()) {
- printf ("Image %s bad header SIZE\n", aufile[idx]);
- ausize[idx] = 0;
- return -1;
- }
- if (!image_check_magic (hdr) || !image_check_arch (hdr, IH_ARCH_PPC)) {
- printf ("Image %s bad MAGIC or ARCH\n", aufile[idx]);
- ausize[idx] = 0;
- return -1;
- }
- /* check the hdr CRC */
- if (!image_check_hcrc (hdr)) {
- printf ("Image %s bad header checksum\n", aufile[idx]);
- ausize[idx] = 0;
- return -1;
- }
- /* check the type - could do this all in one gigantic if() */
- if ((idx == IDX_FIRMWARE) && !image_check_type (hdr, IH_TYPE_FIRMWARE)) {
- printf ("Image %s wrong type\n", aufile[idx]);
- ausize[idx] = 0;
- return -1;
- }
- if ((idx == IDX_KERNEL) && !image_check_type (hdr, IH_TYPE_KERNEL)) {
- printf ("Image %s wrong type\n", aufile[idx]);
- ausize[idx] = 0;
- return -1;
- }
- if ((idx == IDX_ROOTFS) &&
- (!image_check_type (hdr, IH_TYPE_RAMDISK) &&
- !image_check_type (hdr, IH_TYPE_FILESYSTEM))) {
- printf ("Image %s wrong type\n", aufile[idx]);
- ausize[idx] = 0;
- return -1;
- }
- /* recycle checksum */
- checksum = image_get_data_size (hdr);
-
- fsize = checksum + image_get_header_size ();
- /* for kernel and ramdisk the image header must also fit into flash */
- if (idx == IDX_KERNEL || image_check_type (hdr, IH_TYPE_RAMDISK))
- checksum += image_get_header_size ();
-
- /* check the size does not exceed space in flash. HUSH scripts */
- if ((ausize[idx] != 0) && (ausize[idx] < checksum)) {
- printf ("Image %s is bigger than FLASH\n", aufile[idx]);
- ausize[idx] = 0;
- return -1;
- }
- /* Update with the real filesize */
- ausize[idx] = fsize;
-
- return checksum; /* return size to be written to flash */
-}
-
-int au_do_update(int idx, long sz)
-{
- image_header_t *hdr;
- char *addr;
- long start, end;
- int off, rc;
- uint nbytes;
-
- hdr = (image_header_t *)LOAD_ADDR;
-#if defined(CONFIG_FIT)
- if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
- puts ("Non legacy image format not supported\n");
- return -1;
- }
-#endif
-
- /* execute a script */
- if (image_check_type (hdr, IH_TYPE_SCRIPT)) {
- addr = (char *)((char *)hdr + image_get_header_size ());
- /* stick a NULL at the end of the script, otherwise */
- /* parse_string_outer() runs off the end. */
- addr[image_get_data_size (hdr)] = 0;
- addr += 8;
- run_command_list(addr, -1, 0);
- return 0;
- }
-
- start = aufl_layout[idx].start;
- end = aufl_layout[idx].end;
-
- /* unprotect the address range */
- /* this assumes that ONLY the firmware is protected! */
- if (idx == IDX_FIRMWARE) {
-#undef AU_UPDATE_TEST
-#ifdef AU_UPDATE_TEST
- /* erase it where Linux goes */
- start = aufl_layout[1].start;
- end = aufl_layout[1].end;
-#endif
- flash_sect_protect(0, start, end);
- }
-
- /*
- * erase the address range.
- */
- debug ("flash_sect_erase(%lx, %lx);\n", start, end);
- flash_sect_erase(start, end);
- mdelay(100);
-#ifdef CONFIG_PROGRESSBAR
- show_progress(end - start, totsize);
-#endif
-
- /* strip the header - except for the kernel and ramdisk */
- if (image_check_type (hdr, IH_TYPE_KERNEL) ||
- image_check_type (hdr, IH_TYPE_RAMDISK)) {
- addr = (char *)hdr;
- off = image_get_header_size ();
- nbytes = image_get_image_size (hdr);
- } else {
- addr = (char *)((char *)hdr + image_get_header_size ());
-#ifdef AU_UPDATE_TEST
- /* copy it to where Linux goes */
- if (idx == IDX_FIRMWARE)
- start = aufl_layout[1].start;
-#endif
- off = 0;
- nbytes = image_get_data_size (hdr);
- }
-
- /* copy the data from RAM to FLASH */
- debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
- rc = flash_write(addr, start, nbytes);
- if (rc != 0) {
- printf("Flashing failed due to error %d\n", rc);
- return -1;
- }
-
-#ifdef CONFIG_PROGRESSBAR
- show_progress(nbytes, totsize);
-#endif
-
- /* check the data CRC of the copy */
- if (crc32 (0, (uchar *)(start + off), image_get_data_size (hdr)) !=
- image_get_dcrc (hdr)) {
- printf ("Image %s Bad Data Checksum after COPY\n", aufile[idx]);
- return -1;
- }
-
- /* protect the address range */
- /* this assumes that ONLY the firmware is protected! */
- if (idx == IDX_FIRMWARE)
- flash_sect_protect(1, start, end);
- return 0;
-}
-
-/*
- * this is called from board_init() after the hardware has been set up
- * and is usable. That seems like a good time to do this.
- * Right now the return value is ignored.
- */
-int do_auto_update(void)
-{
- block_dev_desc_t *stor_dev;
- long sz;
- int i, res = 0, cnt, old_ctrlc;
- char *env;
- long start, end;
-
-#if 0 /* disable key-press detection to speed up boot-up time */
- uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
-
- /*
- * Read keypad status
- */
- i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status1, 2);
- mdelay(500);
- i2c_read(I2C_PSOC_KEYPAD_ADDR, 0, 0, keypad_status2, 2);
-
- /*
- * Check keypad
- */
- if ( !(keypad_status1[1] & KEYPAD_MASK_LO) ||
- (keypad_status1[1] != keypad_status2[1])) {
- return 0;
- }
-
-#endif
- au_usb_stor_curr_dev = -1;
- /* start USB */
- if (usb_stop() < 0) {
- debug ("usb_stop failed\n");
- return -1;
- }
- if (usb_init() < 0) {
- debug ("usb_init failed\n");
- return -1;
- }
- /*
- * check whether a storage device is attached (assume that it's
- * a USB memory stick, since nothing else should be attached).
- */
- au_usb_stor_curr_dev = usb_stor_scan(0);
- if (au_usb_stor_curr_dev == -1) {
- debug ("No device found. Not initialized?\n");
- res = -1;
- goto xit;
- }
- /* check whether it has a partition table */
- stor_dev = get_dev("usb", 0);
- if (stor_dev == NULL) {
- debug ("uknown device type\n");
- res = -1;
- goto xit;
- }
- if (fat_register_device(stor_dev, 1) != 0) {
- debug ("Unable to use USB %d:%d for fatls\n",
- au_usb_stor_curr_dev, 1);
- res = -1;
- goto xit;
- }
- if (file_fat_detectfs() != 0) {
- debug ("file_fat_detectfs failed\n");
- }
-
- /*
- * now check whether start and end are defined using environment
- * variables.
- */
- start = -1;
- end = 0;
- env = getenv("firmware_st");
- if (env != NULL)
- start = simple_strtoul(env, NULL, 16);
- env = getenv("firmware_nd");
- if (env != NULL)
- end = simple_strtoul(env, NULL, 16);
- if (start >= 0 && end && end > start) {
- ausize[IDX_FIRMWARE] = (end + 1) - start;
- aufl_layout[IDX_FIRMWARE].start = start;
- aufl_layout[IDX_FIRMWARE].end = end;
- }
- start = -1;
- end = 0;
- env = getenv("kernel_st");
- if (env != NULL)
- start = simple_strtoul(env, NULL, 16);
- env = getenv("kernel_nd");
- if (env != NULL)
- end = simple_strtoul(env, NULL, 16);
- if (start >= 0 && end && end > start) {
- ausize[IDX_KERNEL] = (end + 1) - start;
- aufl_layout[IDX_KERNEL].start = start;
- aufl_layout[IDX_KERNEL].end = end;
- }
- start = -1;
- end = 0;
- env = getenv("rootfs_st");
- if (env != NULL)
- start = simple_strtoul(env, NULL, 16);
- env = getenv("rootfs_nd");
- if (env != NULL)
- end = simple_strtoul(env, NULL, 16);
- if (start >= 0 && end && end > start) {
- ausize[IDX_ROOTFS] = (end + 1) - start;
- aufl_layout[IDX_ROOTFS].start = start;
- aufl_layout[IDX_ROOTFS].end = end;
- }
-
- /* make certain that HUSH is runnable */
- u_boot_hush_start();
- /* make sure that we see CTRL-C and save the old state */
- old_ctrlc = disable_ctrlc(0);
-
- /* validate the images first */
- for (i = 0; i < AU_MAXFILES; i++) {
- ulong imsize;
- /* just read the header */
- sz = file_fat_read(aufile[i], LOAD_ADDR, image_get_header_size ());
- debug ("read %s sz %ld hdr %d\n",
- aufile[i], sz, image_get_header_size ());
- if (sz <= 0 || sz < image_get_header_size ()) {
- debug ("%s not found\n", aufile[i]);
- ausize[i] = 0;
- continue;
- }
- /* au_check_header_valid() updates ausize[] */
- if ((imsize = au_check_header_valid(i, sz)) < 0) {
- debug ("%s header not valid\n", aufile[i]);
- continue;
- }
- /* totsize accounts for image size and flash erase size */
- totsize += (imsize + (aufl_layout[i].end - aufl_layout[i].start));
- }
-
-#ifdef CONFIG_PROGRESSBAR
- if (totsize) {
- lcd_puts(" Update in progress\n");
- lcd_enable();
- }
-#endif
-
- /* just loop thru all the possible files */
- for (i = 0; i < AU_MAXFILES && totsize; i++) {
- if (!ausize[i]) {
- continue;
- }
- sz = file_fat_read(aufile[i], LOAD_ADDR, ausize[i]);
-
- debug ("read %s sz %ld hdr %d\n",
- aufile[i], sz, image_get_header_size ());
-
- if (sz != ausize[i]) {
- printf ("%s: size %ld read %ld?\n", aufile[i], ausize[i], sz);
- continue;
- }
-
- if (sz <= 0 || sz <= image_get_header_size ()) {
- debug ("%s not found\n", aufile[i]);
- continue;
- }
- if (au_check_cksum_valid(i, sz) < 0) {
- debug ("%s checksum not valid\n", aufile[i]);
- continue;
- }
- /* this is really not a good idea, but it's what the */
- /* customer wants. */
- cnt = 0;
- do {
- res = au_do_update(i, sz);
- /* let the user break out of the loop */
- if (ctrlc() || had_ctrlc()) {
- clear_ctrlc();
- break;
- }
- cnt++;
-#ifdef AU_TEST_ONLY
- } while (res < 0 && cnt < (AU_MAXFILES + 1));
- if (cnt < (AU_MAXFILES + 1))
-#else
- } while (res < 0);
-#endif
- }
-
- /* restore the old state */
- disable_ctrlc(old_ctrlc);
-#ifdef CONFIG_PROGRESSBAR
- if (totsize) {
- if (!res) {
- lcd_puts("\n Update completed\n");
- } else {
- lcd_puts("\n Update error\n");
- }
- lcd_enable();
- }
-#endif
- xit:
- usb_stop();
- return res;
-}
-#endif /* CONFIG_AUTO_UPDATE */
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <lcd.h>
-#include <mpc5xxx.h>
-#include <malloc.h>
-
-#ifdef CONFIG_LCD
-
-#undef SWAPPED_LCD /* For the previous h/w version */
-/*
- * The name of the device used for communication
- * with the PSoC.
- */
-#define PSOC_PSC MPC5XXX_PSC2
-#define PSOC_BAUD 230400UL
-
-#define RTS_ASSERT 1
-#define RTS_NEGATE 0
-#define CTS_ASSERT 1
-#define CTS_NEGATE 0
-
-/*
- * Dimensions in pixels
- */
-#define LCD_WIDTH 160
-#define LCD_HEIGHT 100
-
-/*
- * Dimensions in bytes
- */
-#define LCD_BUF_SIZE ((LCD_WIDTH*LCD_HEIGHT)>>3)
-
-#if LCD_BPP != LCD_MONOCHROME
-#error "MCC200 support only monochrome displays (1 bpp)!"
-#endif
-
-#define PSOC_RETRIES 10 /* each of PSOC_WAIT_TIME */
-#define PSOC_WAIT_TIME 10 /* usec */
-
-#include <video_font.h>
-#define FONT_WIDTH VIDEO_FONT_WIDTH
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * LCD information
- */
-vidinfo_t panel_info = {
- LCD_WIDTH, LCD_HEIGHT, LCD_BPP
-};
-
-
-/*
- * The device we use to communicate with PSoC
- */
-int serial_inited = 0;
-
-/*
- * Imported functions to support the PSoC protocol
- */
-extern int serial_init_dev (unsigned long dev_base);
-extern void serial_setrts_dev (unsigned long dev_base, int s);
-extern int serial_getcts_dev (unsigned long dev_base);
-extern void serial_putc_raw_dev(unsigned long dev_base, const char c);
-
-/*
- * Just stubs for our driver, needed for compiling compabilty with
- * the common LCD driver code.
- */
-void lcd_initcolregs (void)
-{
-}
-
-void lcd_ctrl_init (void *lcdbase)
-{
-}
-
-/*
- * Function sends the contents of the frame-buffer to the LCD
- */
-void lcd_enable (void)
-{
- int i, retries, fb_size;
-
- if (!serial_inited) {
- unsigned long baud;
-
- baud = gd->baudrate;
- gd->baudrate = PSOC_BAUD;
- serial_init_dev(PSOC_PSC);
- gd->baudrate = baud;
- serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
- serial_inited = 1;
- }
-
- /*
- * Implement PSoC communication protocol:
- * 1. Assert RTS, wait CTS assertion
- * 2. Transmit data
- * 3. Negate RTS, wait CTS negation
- */
-
- /* 1 */
- serial_setrts_dev (PSOC_PSC, RTS_ASSERT);
- for (retries = PSOC_RETRIES; retries; retries--) {
- if (serial_getcts_dev(PSOC_PSC) == CTS_ASSERT)
- break;
- udelay (PSOC_WAIT_TIME);
- }
- if (!retries) {
- printf ("%s Error: PSoC doesn't respond on "
- "RTS ASSERT\n", __FUNCTION__);
- }
-
- /* 2 */
- fb_size = panel_info.vl_row * (panel_info.vl_col >> 3);
-
-#if !defined(SWAPPED_LCD)
- for (i=0; i<fb_size; i++) {
- serial_putc_raw_dev(PSOC_PSC, ((char *)gd->fb_base)[i]);
- }
-#else
- {
- int x, y, pwidth;
- char *p = (char *)gd->fb_base;
-
- pwidth = ((panel_info.vl_col+7) >> 3);
- for (y=0; y<panel_info.vl_row; y++) {
- i = y * pwidth;
- for (x=0; x<pwidth; x+=5) {
- serial_putc_raw_dev (PSOC_PSC, (p[i+x+2]<<4 & 0xF0) | (p[i+x+3]>>4 & 0x0F));
- serial_putc_raw_dev (PSOC_PSC, (p[i+x+3]<<4 & 0xF0) | (p[i+x+4]>>4 & 0x0F));
- serial_putc_raw_dev (PSOC_PSC, (p[i+x+4]<<4 & 0xF0) | (p[i+x]>>4 & 0x0F));
- serial_putc_raw_dev (PSOC_PSC, (p[i+x]<<4 & 0xF0) | (p[i+x+1]>>4 & 0x0F));
- serial_putc_raw_dev (PSOC_PSC, (p[i+x+1]<<4 & 0xF0) | (p[i+x+2]>>4 & 0x0F));
- }
- }
- }
-#endif
-
- /* 3 */
- serial_setrts_dev (PSOC_PSC, RTS_NEGATE);
- for (retries = PSOC_RETRIES; retries; retries--) {
- if (serial_getcts_dev(PSOC_PSC) == CTS_NEGATE)
- break;
- udelay (PSOC_WAIT_TIME);
- }
-
- return;
-}
-#ifdef CONFIG_PROGRESSBAR
-
-void show_progress (int size, int tot)
-{
- int cnt;
- int i;
- static int rc = 0;
-
- rc += size;
-
- cnt = ((LCD_WIDTH/FONT_WIDTH) * rc) / tot;
-
- rc -= (cnt * tot) / (LCD_WIDTH/FONT_WIDTH);
-
- for (i = 0; i < cnt; i++) {
- lcd_putc(0xdc);
- }
-
- if (cnt) {
- lcd_enable(); /* MCC200-specific - send the framebuffer to PSoC */
- }
-}
-
-#endif
-
-int bmp_display(ulong addr, int x, int y)
-{
- int ret;
- bmp_image_t *bmp = (bmp_image_t *)addr;
-
- if (!bmp) {
- printf("There is no valid bmp file at the given address\n");
- return 1;
- }
-
- ret = lcd_display_bitmap((ulong)bmp, x, y);
-
- if ((unsigned long)bmp != addr)
- free(bmp);
-
- return ret;
-}
-
-#endif /* CONFIG_LCD */
+++ /dev/null
-/*
- * (C) Copyright 2003-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/processor.h>
-
-/* Two MT48LC8M32B2 for 32 MB */
-/* #include "mt48lc8m32b2-6-7.h" */
-
-/* One MT48LC16M32S2 for 64 MB */
-/* #include "mt48lc16m32s2-75.h" */
-#if defined (CONFIG_MCC200_SDRAM)
-#include "mt48lc16m16a2-75.h"
-#else
-#include "mt46v16m16-75.h"
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[]; /* FLASH chips info */
-
-extern int do_auto_update(void);
-ulong flash_get_size (ulong base, int banknum);
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start (int hi_addr)
-{
- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
- /* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
-
- /* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
-#endif
-
- /* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
-
- /* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
-
- /* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
-
- udelay(10);
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
- * is something else than 0x00000000.
- */
-
-phys_size_t initdram (int board_type)
-{
- ulong dramsize = 0;
- ulong dramsize2 = 0;
- uint svr, pvr;
-#ifndef CONFIG_SYS_RAMBOOT
- ulong test1, test2;
-
- /* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
- __asm__ volatile ("sync");
-
- /* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
-
-#if SDRAM_DDR
- /* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
-#endif
-
- /* find RAM size using SDRAM CS0 only */
- sdram_start(0);
- test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- sdram_start(1);
- test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
- if (test1 > test2) {
- sdram_start(0);
- dramsize = test1;
- } else {
- dramsize = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize < (1 << 20)) {
- dramsize = 0;
- }
-
- /* set SDRAM CS0 size according to the amount of RAM found */
- if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
- }
-
- /* let SDRAM CS1 start right after CS0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
-
- /* find RAM size using SDRAM CS1 only */
- if (!dramsize)
- sdram_start(0);
- test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- if (!dramsize) {
- sdram_start(1);
- test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
- }
- if (test1 > test2) {
- sdram_start(0);
- dramsize2 = test1;
- } else {
- dramsize2 = test2;
- }
-
- /* memory smaller than 1MB is impossible */
- if (dramsize2 < (1 << 20)) {
- dramsize2 = 0;
- }
-
- /* set SDRAM CS1 size according to the amount of RAM found */
- if (dramsize2 > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
- | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
- } else {
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
- }
-
-#else /* CONFIG_SYS_RAMBOOT */
-
- /* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
- if (dramsize >= 0x13) {
- dramsize = (1 << (dramsize - 0x13)) << 20;
- } else {
- dramsize = 0;
- }
-
- /* retrieve size of memory connected to SDRAM CS1 */
- dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
- if (dramsize2 >= 0x13) {
- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
- } else {
- dramsize2 = 0;
- }
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
- *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
- __asm__ volatile ("sync");
- }
-
- return dramsize + dramsize2;
-}
-
-int checkboard (void)
-{
-#if defined(CONFIG_PRS200)
- puts ("Board: PRS200\n");
-#else
- puts ("Board: MCC200\n");
-#endif
- return 0;
-}
-
-int misc_init_r (void)
-{
- ulong flash_sup_end, snum;
-
- /*
- * Adjust flash start and offset to detected values
- */
- gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
- gd->bd->bi_flashoffset = 0;
-
- /*
- * Check if boot FLASH isn't max size
- */
- if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
- /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
- START_REG(gd->bd->bi_flashstart);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
- STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize);
-
- /*
- * Re-check to get correct base address
- */
- flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
-
- /*
- * Re-do flash protection upon new addresses
- */
- flash_protect (FLAG_PROTECT_CLEAR,
- gd->bd->bi_flashstart, 0xffffffff,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
- /* Monitor protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
- /* Environment protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
- /* Redundant environment protection ON by default */
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
- }
-
- if (gd->bd->bi_flashsize > (32 << 20)) {
- /* Unprotect the upper bank of the Flash */
- *(volatile int*)MPC5XXX_CS0_CFG |= (1 << 6);
- flash_protect (FLAG_PROTECT_CLEAR,
- flash_info[0].start[0] + flash_info[0].size / 2,
- (flash_info[0].start[0] - 1) + flash_info[0].size,
- &flash_info[0]);
- *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6);
- printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n");
- flash_info[0].size = 32 << 20;
- for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20);
- flash_info[0].start[snum] < flash_sup_end;
- snum++);
- flash_info[0].sector_count = snum;
- }
-
-#ifdef CONFIG_AUTO_UPDATE
- do_auto_update();
-#endif
- return (0);
-}
-
-#ifdef CONFIG_PCI
-static struct pci_controller hose;
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc5xxx_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
- debug ("init_ide_reset\n");
-
-}
-
-void ide_set_reset (int idereset)
-{
- debug ("ide_reset(%d)\n", idereset);
-
-}
-#endif
-
-#if defined(CONFIG_CMD_DOC)
-void doc_init (void)
-{
- doc_probe (CONFIG_SYS_DOC_BASE);
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 1 /* is DDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x018D0000
-#define SDRAM_EMODE 0x40090000
-#define SDRAM_CONTROL 0x714f0f00
-#define SDRAM_CONFIG1 0x73722930
-#define SDRAM_CONFIG2 0x47770000
-#define SDRAM_TAPDELAY 0x10000000
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-#define SDRAM_MODE 0x00CD0000
-#define SDRAM_CONTROL 0x504F0000
-#define SDRAM_CONFIG1 0xD2322800
-#define SDRAM_CONFIG2 0x8AD70000
+++ /dev/null
-/*
- * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform
- */
-
-#define SDRAM_DDR 0 /* is SDR */
-
-/* Settings for XLB = 132 MHz */
-
-#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */
-#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */
-#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */
-#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */
if TARGET_VCT
-config SYS_CPU
- default "mips32"
-
config SYS_BOARD
default "vct"
config SYS_CONFIG_NAME
default "vct"
+menu "vct board options"
+
+choice
+ prompt "Board variant"
+
+config VCT_PLATINUM
+ bool "Enable VCT_PLATINUM"
+
+config VCT_PLATINUMAVC
+ bool "Enable VCT_PLATINUMAVC"
+
+config VCT_PREMIUM
+ bool "Enable VCT_PLATINUMAVC"
+
+endchoice
+
+config VCT_ONENAND
+ bool "Enable VCT_ONENAND"
+
+config VCT_SMALL_IMAGE
+ bool "Enable VCT_SMALL_IMAGE"
+
+endmenu
+
endif
if TARGET_PB1X00
-config SYS_CPU
- default "mips32"
-
config SYS_BOARD
default "pb1x00"
if TARGET_QEMU_MIPS
-config SYS_CPU
- default "mips32"
-
-config SYS_BOARD
- default "qemu-mips"
-
-config SYS_CONFIG_NAME
- default "qemu-mips"
-
-endif
-
-if TARGET_QEMU_MIPS64
-
-config SYS_CPU
- default "mips64"
-
config SYS_BOARD
default "qemu-mips"
config SYS_CONFIG_NAME
- default "qemu-mips64"
+ default "qemu-mips" if 32BIT
+ default "qemu-mips64" if 64BIT
endif
#define MSTPSR7 0xE61501C4
#define SMSTPCR7 0xE615014C
-#define SCIF0_MSTP719 (1 << 19)
+#define SCIF2_MSTP719 (1 << 19)
#define MSTPSR8 0xE61509A0
#define SMSTPCR8 0xE6150990
/* TMU */
mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
- /* SCIF0 */
- mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
+ /* SCIF2 */
+ mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719);
/* ETHER */
mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
int dram_init(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
#include <asm/io.h>
#include <asm/arch/rmobile.h>
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
/* QoS version 0.11 */
enum {
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
int dram_init(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
#include <asm/arch/rmobile.h>
/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
-
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
writel(0x00000001, &axi_qos->qosthres2);
writel(0x00000001, &axi_qos->qosqon);
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+ u32 stat = 0;
u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
<< PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ do {
+ stat = readl(PLLECR) & PLL0ST;
+ } while (stat == 0x0);
}
/* QoS(Quality-of-Service) Init */
int dram_init(void)
{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
#include <asm/arch/rmobile.h>
/* QoS version 0.955 for ES1 and version 0.963 for ES2 */
-
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
else
qos_init_es1();
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
static void board_gpio_init(void)
{
/* eMMC Reset Pin */
+ gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
+
gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
/* Enable FAN (Odroid U3) */
+ gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
+
gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
/* OTG Vbus output (Odroid U3+) */
+ gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
+
gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
/* OTG INT (Odroid U3+) */
+ gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
+
gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
gpio_direction_input(EXYNOS4X12_GPIO_X31);
int exynos_early_init_f(void)
{
board_clock_init();
- board_gpio_init();
return 0;
}
gd->ram_size -= SZ_1M;
gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M;
+ board_gpio_init();
+
return 0;
}
FLASH_BUS *addr = (FLASH_BUS *) 0;
+ /* cppcheck-suppress nullPointer */
*addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
+ /* cppcheck-suppress nullPointer */
return *addr;
}
#endif /* #ifdef CONFIG_FACTORYSET */
/* Set rgmii mode and enable rmii clock to be sourced from chip */
- writel(RGMII_MODE_ENABLE , &cdev->miisel);
+ writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I
+if ARCH_SUNXI
+
+choice
+ prompt "Sunxi SoC Variant"
+
+config MACH_SUN4I
+ bool "sun4i (Allwinner A10)"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config MACH_SUN5I
+ bool "sun5i (Allwinner A13)"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config MACH_SUN6I
+ bool "sun6i (Allwinner A31)"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config MACH_SUN7I
+ bool "sun7i (Allwinner A20)"
+ select CPU_V7
+ select SUPPORT_SPL
+
+config MACH_SUN8I
+ bool "sun8i (Allwinner A23)"
+ select CPU_V7
+
+endchoice
config SYS_CONFIG_NAME
string
- default "sun4i" if TARGET_SUN4I
- default "sun5i" if TARGET_SUN5I
- default "sun6i" if TARGET_SUN6I
- default "sun7i" if TARGET_SUN7I
- default "sun8i" if TARGET_SUN8I
+ default "sun4i" if MACH_SUN4I
+ default "sun5i" if MACH_SUN5I
+ default "sun6i" if MACH_SUN6I
+ default "sun7i" if MACH_SUN7I
+ default "sun8i" if MACH_SUN8I
+
+choice
+ prompt "Board"
+
+config TARGET_A10_OLINUXINO_L
+ bool "A10_OLINUXINO_L"
+ depends on MACH_SUN4I
+
+config TARGET_A10S_OLINUXINO_M
+ bool "A10S_OLINUXINO_M"
+ depends on MACH_SUN5I
+
+config TARGET_A13_OLINUXINOM
+ bool "A13_OLINUXINOM"
+ depends on MACH_SUN5I
+
+config TARGET_A13_OLINUXINO
+ bool "A13_OLINUXINO"
+ depends on MACH_SUN5I
+
+config TARGET_A20_OLINUXINO_L2
+ bool "A20_OLINUXINO_L2"
+ depends on MACH_SUN7I
+
+config TARGET_A20_OLINUXINO_L
+ bool "A20_OLINUXINO_L"
+ depends on MACH_SUN7I
+
+config TARGET_A20_OLINUXINO_M
+ bool "A20_OLINUXINO_M"
+ depends on MACH_SUN7I
+
+config TARGET_AUXTEK_T004
+ bool "AUXTEK_T004"
+ depends on MACH_SUN5I
+
+config TARGET_BANANAPI
+ bool "BANANAPI"
+ depends on MACH_SUN7I
+
+config TARGET_COLOMBUS
+ bool "COLOMBUS"
+ depends on MACH_SUN6I
+
+config TARGET_CUBIEBOARD2
+ bool "CUBIEBOARD2"
+ depends on MACH_SUN7I
+
+config TARGET_CUBIEBOARD
+ bool "CUBIEBOARD"
+ depends on MACH_SUN4I
+
+config TARGET_CUBIETRUCK
+ bool "CUBIETRUCK"
+ depends on MACH_SUN7I
+
+config TARGET_IPPO_Q8H_V5
+ bool "IPPO_Q8H_V5"
+ depends on MACH_SUN8I
+
+config TARGET_PCDUINO3
+ bool "PCDUINO3"
+ depends on MACH_SUN7I
+
+config TARGET_MELE_A1000G
+ bool "MELE_A1000G"
+ depends on MACH_SUN4I
+
+config TARGET_MELE_A1000
+ bool "MELE_A1000"
+ depends on MACH_SUN4I
+
+config TARGET_MELE_M3
+ bool "MELE_M3"
+ depends on MACH_SUN7I
+
+config TARGET_MELE_M9
+ bool "MELE_M9"
+ depends on MACH_SUN6I
+
+config TARGET_MINI_X_1GB
+ bool "MINI_X_1GB"
+ depends on MACH_SUN4I
+
+config TARGET_MINI_X
+ bool "MINI_X"
+ depends on MACH_SUN4I
+
+config TARGET_BA10_TV_BOX
+ bool "BA10_TV_BOX"
+ depends on MACH_SUN4I
+
+config TARGET_I12_TVBOX
+ bool "I12_TVBOX"
+ depends on MACH_SUN7I
+
+config TARGET_QT840A
+ bool "QT840A"
+ depends on MACH_SUN7I
+
+config TARGET_R7DONGLE
+ bool "R7DONGLE"
+ depends on MACH_SUN5I
+
+endchoice
config SYS_BOARD
default "sunxi"
config SYS_SOC
default "sunxi"
+config SPL_FEL
+ bool "SPL/FEL mode support"
+ depends on SPL
+ default n
+
config FDTFILE
string "Default fdtfile env setting for this board"
slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
support for this.
+config USB1_VBUS_PIN
+ string "Vbus enable pin for usb1 (ehci0)"
+ default "PH6" if MACH_SUN4I || MACH_SUN7I
+ default "PH27" if MACH_SUN6I
+ ---help---
+ Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
+ a string in the format understood by sunxi_name_to_gpio, e.g.
+ PH1 for pin 1 of port H.
+
+config USB2_VBUS_PIN
+ string "Vbus enable pin for usb2 (ehci1)"
+ default "PH3" if MACH_SUN4I || MACH_SUN7I
+ default "PH24" if MACH_SUN6I
+ ---help---
+ See USB1_VBUS_PIN help text.
+
endif
F: configs/Mele_A1000_defconfig
F: configs/Mele_A1000G_defconfig
F: configs/Mele_M3_defconfig
+F: configs/Mele_M9_defconfig
F: configs/Mini-X_defconfig
F: configs/Mini-X-1Gb_defconfig
F: include/configs/sun5i.h
F: configs/Bananapi_defconfig
F: configs/i12-tvbox_defconfig
F: configs/Linksprite_pcDuino3_defconfig
+F: configs/Linksprite_pcDuino3_fdt_defconfig
F: configs/qt840a_defconfig
CUBIEBOARD2 BOARD
F: configs/Colombus_defconfig
IPPO-Q8H-V5 BOARD
-M: CHen-Yu Tsai <wens@csie.org>
+M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
F: configs/Ippo_q8h_v5_defconfig
obj-y += board.o
obj-$(CONFIG_SUNXI_GMAC) += gmac.o
obj-$(CONFIG_SUNXI_AHCI) += ahci.o
-obj-$(CONFIG_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
-obj-$(CONFIG_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o
-obj-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o
-obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
-obj-$(CONFIG_A20_OLINUXINO_L) += dram_a20_olinuxino_l.o
-obj-$(CONFIG_A20_OLINUXINO_L2) += dram_a20_olinuxino_l2.o
-obj-$(CONFIG_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
+obj-$(CONFIG_TARGET_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o
+obj-$(CONFIG_TARGET_A13_OLINUXINO) += dram_a13_olinuxino.o
+obj-$(CONFIG_TARGET_A13_OLINUXINOM) += dram_a13_oli_micro.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_L) += dram_a20_olinuxino_l.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_L2) += dram_a20_olinuxino_l2.o
+obj-$(CONFIG_TARGET_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o
# This is not a typo, uses the same mem settings as the a10s-olinuxino-m
-obj-$(CONFIG_AUXTEK_T004) += dram_a10s_olinuxino_m.o
-obj-$(CONFIG_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
-obj-$(CONFIG_BANANAPI) += dram_bananapi.o
-obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
-obj-$(CONFIG_CUBIEBOARD2) += dram_cubieboard2.o
-obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
-obj-$(CONFIG_I12_TVBOX) += dram_sun7i_384_1024_iow16.o
-obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o
-obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
-obj-$(CONFIG_MELE_M3) += dram_sun7i_384_1024_iow16.o
-obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o
-obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
-obj-$(CONFIG_PCDUINO3) += dram_linksprite_pcduino3.o
-obj-$(CONFIG_QT840A) += dram_sun7i_384_512_busw16_iow16.o
-obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
+obj-$(CONFIG_TARGET_AUXTEK_T004) += dram_a10s_olinuxino_m.o
+obj-$(CONFIG_TARGET_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
+obj-$(CONFIG_TARGET_BANANAPI) += dram_bananapi.o
+obj-$(CONFIG_TARGET_CUBIEBOARD) += dram_cubieboard.o
+obj-$(CONFIG_TARGET_CUBIEBOARD2) += dram_cubieboard2.o
+obj-$(CONFIG_TARGET_CUBIETRUCK) += dram_cubietruck.o
+obj-$(CONFIG_TARGET_I12_TVBOX) += dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_MELE_A1000) += dram_sun4i_360_512.o
+obj-$(CONFIG_TARGET_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
+obj-$(CONFIG_TARGET_MELE_M3) += dram_sun7i_384_1024_iow16.o
+obj-$(CONFIG_TARGET_MINI_X) += dram_sun4i_360_512.o
+obj-$(CONFIG_TARGET_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
+obj-$(CONFIG_TARGET_PCDUINO3) += dram_linksprite_pcduino3.o
+obj-$(CONFIG_TARGET_QT840A) += dram_sun7i_384_512_busw16_iow16.o
+obj-$(CONFIG_TARGET_R7DONGLE) += dram_r7dongle.o
{
printf("SUNXI SCSI INIT\n");
#ifdef CONFIG_SATAPWR
+ gpio_request(CONFIG_SATAPWR, "satapwr");
gpio_direction_output(CONFIG_SATAPWR, 1);
#endif
#ifdef CONFIG_AXP209_POWER
#include <axp209.h>
#endif
+#ifdef CONFIG_AXP221_POWER
+#include <axp221.h>
+#endif
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/dram.h>
power_failed |= axp209_set_ldo2(3000);
power_failed |= axp209_set_ldo3(2800);
power_failed |= axp209_set_ldo4(2800);
+#endif
+#ifdef CONFIG_AXP221_POWER
+ power_failed = axp221_init();
+ power_failed |= axp221_set_dcdc1(3000);
+ power_failed |= axp221_set_dcdc2(1200);
+ power_failed |= axp221_set_dcdc3(1200);
+ power_failed |= axp221_set_dcdc4(1200);
+ power_failed |= axp221_set_dcdc5(1500);
+#if CONFIG_AXP221_DLDO1_VOLT != -1
+ power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
+#endif
+#if CONFIG_AXP221_DLDO4_VOLT != -1
+ power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO1_VOLT != -1
+ power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO2_VOLT != -1
+ power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO3_VOLT != -1
+ power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
+#endif
#endif
printf("DRAM:");
* need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain"
* of the GMAC clk register to 3.
*/
-#ifdef CONFIG_BANANAPI
+#ifdef CONFIG_TARGET_BANANAPI
setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10);
#endif
--- /dev/null
+if TARGET_TBS2910
+
+config SYS_CPU
+ string
+ default "armv7"
+
+config SYS_BOARD
+ string
+ default "tbs2910"
+
+config SYS_VENDOR
+ string
+ default "tbs"
+
+config SYS_SOC
+ string
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ string
+ default "tbs2910"
+
+endif
--- /dev/null
+TBS2910 BOARD
+M: Soeren Moch <smoch@web.de>
+S: Maintained
+F: board/tbs/tbs2910/
+F: configs/tbs2910_defconfig
+F: include/configs/tbs2910.h
--- /dev/null
+#
+# Copyright (C) 2014 Soeren Moch <smoch@web.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := tbs2910.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Soeren Moch <smoch@web.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sata.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_SRE_SLOW)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+#ifdef CONFIG_SYS_I2C
+/* I2C1, SGTL5000 */
+static struct i2c_pads_info i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
+ .gp = IMX_GPIO_NR(5, 27)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
+ .gp = IMX_GPIO_NR(5, 26)
+ }
+};
+
+/* I2C2 HDMI */
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+/* I2C3, CON11, DS1307, PCIe_SMB */
+static struct i2c_pads_info i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+#endif /* CONFIG_SYS_I2C */
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8035 PHY Reset */
+ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pcie_pads[] = {
+ /* W_DISABLE# */
+ MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
+ /* PERST# */
+ MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int dram_init(void)
+{
+ gd->ram_size = 2048ul * 1024 * 1024;
+ return 0;
+}
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8035 PHY */
+ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+}
+
+static void setup_pcie(void)
+{
+ imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC2_BASE_ADDR},
+ {USDHC3_BASE_ADDR},
+ {USDHC4_BASE_ADDR},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
+#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC2_BASE_ADDR:
+ ret = !gpio_get_value(USDHC2_CD_GPIO);
+ break;
+ case USDHC3_BASE_ADDR:
+ ret = !gpio_get_value(USDHC3_CD_GPIO);
+ break;
+ case USDHC4_BASE_ADDR:
+ ret = 1; /* eMMC/uSDHC4 is always present */
+ break;
+ }
+ return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
+ int i;
+
+ /*
+ * (U-boot device node) (Physical Port)
+ * mmc0 SD2
+ * mmc1 SD3
+ * mmc2 eMMC
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ gpio_direction_input(USDHC2_CD_GPIO);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+ break;
+ case 1:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ gpio_direction_input(USDHC3_CD_GPIO);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+ break;
+ case 2:
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) then supported by the board (%d)\n",
+ i + 1, CONFIG_SYS_FSL_USDHC_NUM);
+ return status;
+ }
+
+ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ }
+ return status;
+}
+#endif /* CONFIG_FSL_ESDHC */
+
+#ifdef CONFIG_VIDEO_IPUV3
+static void do_enable_hdmi(struct display_info_t const *dev)
+{
+ imx_enable_hdmi_phy();
+}
+
+struct display_info_t const displays[] = {{
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_hdmi,
+ .enable = do_enable_hdmi,
+ .mode = {
+ .name = "HDMI",
+ /* 1024x768@60Hz (VESA)*/
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15384,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} } };
+size_t display_count = ARRAY_SIZE(displays);
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+ s32 timeout = 100000;
+
+ enable_ipu_clock();
+ imx_setup_hdmi();
+
+ /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
+ reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
+ writel(reg, &ccm->analog_pll_video);
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+ reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+ reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+ writel(reg, &ccm->analog_pll_video);
+
+ /* select video pll for ldb_di0_clk */
+ reg = readl(&ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+ writel(reg, &ccm->cs2cdr);
+
+ /* select ldb_di0_clk / 7 for ldb_di0_ipu_clk */
+ reg = readl(&ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &ccm->cscmr2);
+
+ /* select ldb_di0_ipu_clk for ipu1_di0_clk -> 65MHz pixclock */
+ reg = readl(&ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &ccm->chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+ setup_pcie();
+ return cpu_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+static const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+ {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ /* 8 bit bus width */
+ {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_VIDEO_IPUV3
+ setup_display();
+#endif
+#ifdef CONFIG_SYS_I2C
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+#endif
+#ifdef CONFIG_DWC_AHSATA
+ setup_sata();
+#endif
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: TBS2910 Matrix ARM mini PC\n");
+ return 0;
+}
board you may want something other than UART0 as for example the IDK
uses UART3 so enter 4 here.
+config NOR
+ bool "Support for NOR flash"
+ help
+ The AM335x SoC supports having a NOR flash connected to the GPMC.
+ In practice this is seen as a NOR flash module connected to the
+ "memory cape" for the BeagleBone family.
+
+config NOR_BOOT
+ bool "Support for booting from NOR flash"
+ depends on NOR
+ help
+ Enabling this will make a U-Boot binary that is capable of being
+ booted via NOR. In this case we will enable certain pinmux early
+ as the ROM only partially sets up pinmux. We also default to using
+ NOR for environment.
endif
if TARGET_K2L_EVM
config SYS_BOARD
- string
default "ks2_evm"
config SYS_VENDOR
- string
default "ti"
config SYS_CONFIG_NAME
- string
default "k2l_evm"
endif
Author: Murali Karicheri <m-karicheri2@ti.com>
-This README has information on the u-boot port for K2HK, K2E boards.
+This README has information on the u-boot port for K2HK, K2E, and K2L EVM boards.
Documentation for this board can be found at
http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx
https://www.einfochips.com/index.php/partnerships/texas-instruments/k2e-evm.html
+https://www.einfochips.com/index.php/partnerships/texas-instruments/k2l-evm.html
The K2HK board is based on Texas Instruments Keystone2 family of SoCs: K2H, K2K.
More details on these SoCs are available at company websites
K2H: http://www.ti.com/product/tci6638k2h
The K2E SoC details are available at
- K2E http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+ http://www.ti.com/lit/ds/symlink/66ak2e05.pdf
+
+The K2L SoC details are available at
+ http://www.ti.com/lit/ds/symlink/tci6630k2l.pdf
Board configuration:
====================
+------+-------+-------+-----------+-----------+-------+-------+----+
|K2HK |2 |512MB |6MB |4(2) |2 |3 |3 |
|K2E |4 |512MB |2MB |8(2) |2 |3 |3 |
+|K2L |2 |512MB |2MB |4(2) |4 |3 |3 |
+------+-------+-------+-----------+-----------+-------+-------+----+
There are only 2 eth port installed on the boards.
Board configuration files:
include/configs/k2hk_evm.h
include/configs/k2e_evm.h
+include/configs/k2l_evm.h
+include/configs/k2l_evm.h
As u-boot is migrating to Kconfig there is also board defconfig files
configs/k2e_evm_defconfig
configs/k2hk_evm_defconfig
+configs/k2l_evm_defconfig
Supported boot modes:
- SPI NOR boot
Build instructions:
===================
-Examples for k2hk, for k2e just replace k2hk prefix accordingly.
+Examples for k2hk, for k2e and k2l just replace k2hk prefix accordingly.
Don't forget to add ARCH=arm and CROSS_COMPILE.
To build u-boot.bin
on EVM. Follow instructions at
K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
+K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
+
to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
and Power ON the EVM. Follow instructions to connect serial port of EVM to
PC and start TeraTerm or Hyper Terminal.
2. Suspend Target. Select Run -> Suspend from top level menu
CortexA15_1 (Free Running)"
3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000
- through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E EVM
- using CCS", but using address 0x87000000.
+ through CCS as described in step 2 of "Load and Run U-Boot on K2HK/K2E/K2L
+ EVM using CCS", but using address 0x87000000.
4. Free Run the target as described earlier (step 4) to get u-boot prompt
5. At the U-Boot console type following to setup u-boot environment variables.
setenv addr_uboot 0x87000000
int nbanks;
u64 size[2];
u64 start[2];
- char name[32];
int nodeoffset;
u32 ddr3a_size;
int unitrd_fixup = 0;
}
/* reserve memory at start of bank */
- sprintf(name, "mem_reserve_head");
- env = getenv(name);
+ env = getenv("mem_reserve_head");
if (env) {
start[0] += ustrtoul(env, &endp, 0);
size[0] -= ustrtoul(env, &endp, 0);
}
- sprintf(name, "mem_reserve");
- env = getenv(name);
+ env = getenv("mem_reserve");
if (env)
size[0] -= ustrtoul(env, &endp, 0);
#include <common.h>
#include <asm/arch/ddr3.h>
#include <asm/arch/hardware.h>
-#include <asm/ti-common/ti-aemif.h>
+#include <asm/ti-common/keystone_net.h>
DECLARE_GLOBAL_DATA_PTR;
static struct pll_init_data pa_pll_config =
PASS_PLL_983;
+#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
+struct eth_priv_t eth_priv_cfg[] = {
+ {
+ .int_name = "K2L_EMAC",
+ .rx_flow = 0,
+ .phy_addr = 0,
+ .slave_port = 1,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2L_EMAC1",
+ .rx_flow = 8,
+ .phy_addr = 1,
+ .slave_port = 2,
+ .sgmii_link_type = SGMII_LINK_MAC_PHY,
+ },
+ {
+ .int_name = "K2L_EMAC2",
+ .rx_flow = 16,
+ .phy_addr = 2,
+ .slave_port = 3,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+ {
+ .int_name = "K2L_EMAC3",
+ .rx_flow = 32,
+ .phy_addr = 3,
+ .slave_port = 4,
+ .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
+ },
+};
+
+int get_num_eth_ports(void)
+{
+ return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
+}
+#endif
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
};
+#define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
+
static unsigned const tqma6_ecspi1_cs[] = {
- IMX_GPIO_NR(3, 19),
+ TQMA6_SF_CS_GPIO,
};
static void tqma6_iomuxc_spi(void)
ARRAY_SIZE(tqma6_ecspi1_pads));
}
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return ((bus == CONFIG_SF_DEFAULT_BUS) &&
+ (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
+}
+
static struct i2c_pads_info tqma6_i2c3_pads = {
/* I2C3: on board LM75, M24C64, */
.scl = {
*/
#ifndef __TQMA6_BB__
-#define __TQMA6_BB
+#define __TQMA6_BB__
#include <common.h>
ps7_init.[ch]
+ps7_init_gpl.[ch]
obj-y := board.o
-# Please copy ps7_init.c/h from hw project to this directory
+# Please copy ps7_init_gpl.c/h from hw project to this directory
obj-$(CONFIG_SPL_BUILD) += \
- $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o)
+ $(if $(wildcard $(srctree)/$(src)/ps7_init_gpl.c), ps7_init_gpl.o, \
+ $(if $(wildcard $(srctree)/$(src)/ps7_init.c), ps7_init.o legacy.o))
# Suppress "warning: function declaration isn't a prototype"
+CFLAGS_REMOVE_ps7_init_gpl.o := -Wstrict-prototypes
CFLAGS_REMOVE_ps7_init.o := -Wstrict-prototypes
--- /dev/null
+
+#warning usage of ps7_init files is deprecated please use ps7_init_gpl
#define XIL_IO_H
/*
- * This empty file is here because ps7_init.c exported by hw project
+ * This empty file is here because ps7_init_gpl.c exported by hw project
* has #include "xil_io.h" line.
*/
}
/* If we have a valid setup.bin, we will use that for entry (x86) */
- if (images.os.arch == IH_ARCH_I386) {
+ if (images.os.arch == IH_ARCH_I386 ||
+ images.os.arch == IH_ARCH_X86_64) {
ulong len;
ret = boot_get_setup(&images, IH_ARCH_I386, &images.ep, &len);
o_string temp=NULL_O_STRING;
int rcode;
#ifdef __U_BOOT__
- int code = 0;
+ int code = 1;
#endif
do {
ctx.type = flag;
}
b_free(&temp);
/* loop on syntax errors, return on EOF */
- } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP) &&
+ } while (rcode != 1 && !(flag & FLAG_EXIT_FROM_LOOP) &&
(inp->peek != static_peek || b_peek(inp)));
#ifndef __U_BOOT__
return 0;
#ifdef __U_BOOT__
char *p = NULL;
int rcode;
- if ( !s || !*s)
+ if (!s)
return 1;
+ if (!*s)
+ return 0;
if (!(p = strchr(s, '\n')) || *++p) {
p = xmalloc(strlen(s) + 2);
strcpy(p, s);
-de <net.h>
-
-#if !defined(CONFIG_UPDATE_TFTP)
-#error "CONFIG_UPDATE_TFTP required"
-#endif
-
-static int do_fitupd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- ulong addr = 0Un the root directory of the source tree for details.
+/*
+ * (C) Copyright 2011
+ * Andreas Pretzsch, carpe noctem engineering, apr@cn-eng.de
+ *
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
mem_malloc_end = start + size;
mem_malloc_brk = start;
+ debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start,
+ mem_malloc_end);
+
memset((void *)mem_malloc_start, 0, size);
malloc_bin_reloc();
INTERNAL_SIZE_T nb;
#ifdef CONFIG_SYS_MALLOC_F_LEN
- if (!(gd->flags & GD_FLG_RELOC)) {
+ if (gd && !(gd->flags & GD_FLG_RELOC)) {
ulong new_ptr;
void *ptr;
}
} else {
debug("## No Flattened Device Tree\n");
- return 0;
+ goto error;
}
} else {
debug("## No Flattened Device Tree\n");
- return 0;
+ goto error;
}
*of_flat_tree = fdt_blob;
if (fit_image_get_arch(fit, noffset, &image_arch))
return 0;
- return (arch == image_arch);
+ return (arch == image_arch) ||
+ (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64);
}
/**
{ IH_ARCH_SANDBOX, "sandbox", "Sandbox", },
{ IH_ARCH_ARM64, "arm64", "AArch64", },
{ IH_ARCH_ARC, "arc", "ARC", },
+ { IH_ARCH_X86_64, "x86_64", "AMD x86_64", },
{ -1, "", "", },
};
}
#endif
-#if defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
+#if defined(CONFIG_MPC823)
#define FB_PUT_BYTE(fb, from) *(fb)++ = (255 - *(from)++)
#else
#define FB_PUT_BYTE(fb, from) *(fb)++ = *(from)++
int lcd_display_bitmap(ulong bmp_image, int x, int y)
{
-#if !defined(CONFIG_MCC200)
ushort *cmap = NULL;
-#endif
ushort *cmap_base = NULL;
ushort i, j;
uchar *fb;
debug("Display-bmp: %d x %d with %d colors\n",
(int)width, (int)height, (int)colors);
-#if !defined(CONFIG_MCC200)
- /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
if (bmp_bpix == 8) {
cmap = configuration_get_cmap();
cmap_base = cmap;
#endif
}
}
-#endif
- /*
- * BMP format for Monochrome assumes that the state of a
- * pixel is described on a per Bit basis, not per Byte.
- * So, in case of Monochrome BMP we should align widths
- * on a byte boundary and convert them from Bit to Byte
- * units.
- * Probably, PXA250 and MPC823 process 1bpp BMP images in
- * their own ways, so make the converting to be MCC200
- * specific.
- */
-#if defined(CONFIG_MCC200)
- if (bpix == 1) {
- width = ((width + 7) & ~7) >> 3;
- x = ((x + 7) & ~7) >> 3;
- pwidth= ((pwidth + 7) & ~7) >> 3;
- }
-#endif
padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width);
}
list_del(&(dev->list));
+ free(dev);
/* reassign Device list */
list_for_each(pos, &(devs.list)) {
* thread_id=5729457&forum_id=5398
*/
__maybe_unused struct usb_device_descriptor *desc;
- int port = -1;
struct usb_device *parent = dev->parent;
unsigned short portstatus;
#endif
if (parent) {
- int j;
-
- /* find the port number we're at */
- for (j = 0; j < parent->maxchild; j++) {
- if (parent->children[j] == dev) {
- port = j;
- break;
- }
- }
- if (port < 0) {
- printf("usb_new_device:cannot locate device's port.\n");
- return 1;
- }
-
/* reset the port for the second time */
- err = hub_port_reset(dev->parent, port, &portstatus);
+ err = hub_port_reset(dev->parent, dev->portnr - 1, &portstatus);
if (err < 0) {
- printf("\n Couldn't reset port %i\n", port);
+ printf("\n Couldn't reset port %i\n", dev->portnr);
return 1;
}
}
int i;
struct usb_device *dev;
unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2;
- ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
- unsigned short portstatus;
- int ret;
dev = hub->pusb_dev;
- /*
- * Enable power to the ports:
- * Here we Power-cycle the ports: aka,
- * turning them off and turning on again.
- */
debug("enabling power on all ports\n");
- for (i = 0; i < dev->maxchild; i++) {
- usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
- debug("port %d returns %lX\n", i + 1, dev->status);
- }
-
- /* Wait at least 2*bPwrOn2PwrGood for PP to change */
- mdelay(pgood_delay);
-
- for (i = 0; i < dev->maxchild; i++) {
- ret = usb_get_port_status(dev, i + 1, portsts);
- if (ret < 0) {
- debug("port %d: get_port_status failed\n", i + 1);
- continue;
- }
-
- /*
- * Check to confirm the state of Port Power:
- * xHCI says "After modifying PP, s/w shall read
- * PP and confirm that it has reached the desired state
- * before modifying it again, undefined behavior may occur
- * if this procedure is not followed".
- * EHCI doesn't say anything like this, but no harm in keeping
- * this.
- */
- portstatus = le16_to_cpu(portsts->wPortStatus);
- if (portstatus & (USB_PORT_STAT_POWER << 1)) {
- debug("port %d: Port power change failed\n", i + 1);
- continue;
- }
- }
-
for (i = 0; i < dev->maxchild; i++) {
usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
debug("port %d returns %lX\n", i + 1, dev->status);
#define USB_KBD_BOOT_REPORT_SIZE 8
struct usb_kbd_pdata {
+ unsigned long intpipe;
+ int intpktsize;
+ int intinterval;
+ struct int_queue *intq;
+
uint32_t repeat_delay;
uint32_t usb_in_pointer;
/* The period of time between two calls of usb_kbd_testc(). */
static unsigned long __maybe_unused kbd_testc_tms;
-/* Generic keyboard event polling. */
-void usb_kbd_generic_poll(void)
-{
- struct stdio_dev *dev;
- struct usb_device *usb_kbd_dev;
- struct usb_kbd_pdata *data;
- struct usb_interface *iface;
- struct usb_endpoint_descriptor *ep;
- int pipe;
- int maxp;
-
- /* Get the pointer to USB Keyboard device pointer */
- dev = stdio_get_by_name(DEVNAME);
- usb_kbd_dev = (struct usb_device *)dev->priv;
- data = usb_kbd_dev->privptr;
- iface = &usb_kbd_dev->config.if_desc[0];
- ep = &iface->ep_desc[0];
- pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress);
-
- /* Submit a interrupt transfer request */
- maxp = usb_maxpacket(usb_kbd_dev, pipe);
- usb_submit_int_msg(usb_kbd_dev, pipe, data->new,
- min(maxp, USB_KBD_BOOT_REPORT_SIZE),
- ep->bInterval);
-}
-
/* Puts character in the queue and sets up the in and out pointer. */
static void usb_kbd_put_queue(struct usb_kbd_pdata *data, char c)
{
static inline void usb_kbd_poll_for_event(struct usb_device *dev)
{
#if defined(CONFIG_SYS_USB_EVENT_POLL)
- struct usb_interface *iface;
- struct usb_endpoint_descriptor *ep;
- struct usb_kbd_pdata *data;
- int pipe;
- int maxp;
-
- /* Get the pointer to USB Keyboard device pointer */
- data = dev->privptr;
- iface = &dev->config.if_desc[0];
- ep = &iface->ep_desc[0];
- pipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
+ struct usb_kbd_pdata *data = dev->privptr;
/* Submit a interrupt transfer request */
- maxp = usb_maxpacket(dev, pipe);
- usb_submit_int_msg(dev, pipe, &data->new[0],
- min(maxp, USB_KBD_BOOT_REPORT_SIZE),
- ep->bInterval);
+ usb_submit_int_msg(dev, data->intpipe, &data->new[0], data->intpktsize,
+ data->intinterval);
usb_kbd_irq_worker(dev);
#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP)
1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE);
if (memcmp(data->old, data->new, USB_KBD_BOOT_REPORT_SIZE))
usb_kbd_irq_worker(dev);
+#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE)
+ struct usb_kbd_pdata *data = dev->privptr;
+ if (poll_int_queue(dev, data->intq)) {
+ usb_kbd_irq_worker(dev);
+ /* We've consumed all queued int packets, create new */
+ destroy_int_queue(dev, data->intq);
+ data->intq = create_int_queue(dev, data->intpipe, 1,
+ USB_KBD_BOOT_REPORT_SIZE, data->new);
+ }
#endif
}
struct usb_interface *iface;
struct usb_endpoint_descriptor *ep;
struct usb_kbd_pdata *data;
- int pipe, maxp;
if (dev->descriptor.bNumConfigurations != 1)
return 0;
/* Set IRQ handler */
dev->irq_handle = usb_kbd_irq;
- pipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
- maxp = usb_maxpacket(dev, pipe);
+ data->intpipe = usb_rcvintpipe(dev, ep->bEndpointAddress);
+ data->intpktsize = min(usb_maxpacket(dev, data->intpipe),
+ USB_KBD_BOOT_REPORT_SIZE);
+ data->intinterval = ep->bInterval;
/* We found a USB Keyboard, install it. */
usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0);
usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0);
debug("USB KBD: enable interrupt pipe...\n");
- if (usb_submit_int_msg(dev, pipe, data->new,
- min(maxp, USB_KBD_BOOT_REPORT_SIZE),
- ep->bInterval) < 0) {
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+ data->intq = create_int_queue(dev, data->intpipe, 1,
+ USB_KBD_BOOT_REPORT_SIZE, data->new);
+ if (!data->intq) {
+#else
+ if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize,
+ data->intinterval) < 0) {
+#endif
printf("Failed to get keyboard state from device %04x:%04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
/* Abort, we don't want to use that non-functional keyboard. */
int usb_kbd_deregister(int force)
{
#ifdef CONFIG_SYS_STDIO_DEREGISTER
- int ret = stdio_deregister(DEVNAME, force);
- if (ret && ret != -ENODEV)
- return ret;
+ struct stdio_dev *dev;
+ struct usb_device *usb_kbd_dev;
+ struct usb_kbd_pdata *data;
+
+ dev = stdio_get_by_name(DEVNAME);
+ if (dev) {
+ usb_kbd_dev = (struct usb_device *)dev->priv;
+ data = usb_kbd_dev->privptr;
+ if (stdio_deregister_dev(dev, force) != 0)
+ return 1;
+#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
+ destroy_int_queue(usb_kbd_dev, data->intq);
+#endif
+ free(data->new);
+ free(data);
+ }
return 0;
#else
perq = usb_stor_buf[0];
modi = usb_stor_buf[1];
- if ((perq & 0x1f) == 0x1f) {
- /* skip unknown devices */
+ /*
+ * Skip unknown devices (0x1f) and enclosure service devices (0x0d),
+ * they would not respond to test_unit_ready .
+ */
+ if (((perq & 0x1f) == 0x1f) || ((perq & 0x1f) == 0x0d)) {
return 0;
}
if ((modi&0x80) == 0x80) {
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A10_OLINUXINO_L,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-olinuxino-lime.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_A10_OLINUXINO_L=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A10S_OLINUXINO_M,AXP152_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPB(10)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,SUNXI_EMAC,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=1
+CONFIG_USB1_VBUS_PIN="PB10"
+S:CONFIG_MMC0_CD_PIN="PG1"
+S:CONFIG_MMC1_CD_PIN="PG13"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A10S_OLINUXINO_M=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINOM,CONS_INDEX=2,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,USB_EHCI"
CONFIG_FDTFILE="sun5i-a13-olinuxino-micro.dtb"
+CONFIG_USB1_VBUS_PIN="PG11"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A13_OLINUXINOM=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A13_OLINUXINO,CONS_INDEX=2,AXP209_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(11)"
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a13-olinuxino.dtb"
+CONFIG_USB1_VBUS_PIN="PG11"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_A13_OLINUXINO=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A20_OLINUXINO_L2,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-lime2.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_L2=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A20_OLINUXINO_L,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-lime.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_L=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="A20_OLINUXINO_M,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-olinuxino-micro.dtb"
CONFIG_MMC_SUNXI_SLOT_EXTRA=3
+S:CONFIG_MMC0_CD_PIN="PH1"
+S:CONFIG_MMC3_CD_PIN="PH11"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_A20_OLINUXINO_M=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="AUXTEK_T004,AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-auxtek-t004.dtb"
+CONFIG_USB1_VBUS_PIN="PG13"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_AUXTEK_T004=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="BANANAPI,AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-bananapi.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_BANANAPI=y
-CONFIG_SYS_EXTRA_OPTIONS="COLOMBUS"
-CONFIG_ARM=y
-CONFIG_TARGET_SUN6I=y
+CONFIG_SPL=y
CONFIG_FDTFILE="sun6i-a31-colombus.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_TARGET_COLOMBUS=y
+++ /dev/null
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,SPL_FEL,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD2,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubieboard2.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_CUBIEBOARD2=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIEBOARD,AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,AHCI,SATAPWR=SUNXI_GPB(8),USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-cubieboard.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_CUBIEBOARD=y
+++ /dev/null
-CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,SPL_FEL,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
-CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
-+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="CUBIETRUCK,AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPH(12),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-cubietruck.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_CUBIETRUCK=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="IPPO_Q8H_V5,CONS_INDEX=5"
-CONFIG_ARM=y
-CONFIG_TARGET_SUN8I=y
-CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN8I=y
+CONFIG_TARGET_IPPO_Q8H_V5=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PCDUINO3,AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_PCDUINO3=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI"
+CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb"
+CONFIG_DM=y
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_PCDUINO3=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MELE_A1000G,AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MELE_A1000G=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MELE_A1000,AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),AHCI,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-a1000.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MELE_A1000=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MELE_M3,AXP209_POWER,SUNXI_GMAC,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-m3.dtb"
+S:CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+S:CONFIG_MMC0_CD_PIN="PH1"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_MELE_M3=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI"
+CONFIG_FDTFILE="sun6i-a31-m9.dtb"
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN6I=y
++S:CONFIG_TARGET_MELE_M9=y
+# Ethernet phy power
++S:CONFIG_AXP221_DLDO1_VOLT=3300
+# USB hub power
++S:CONFIG_AXP221_DLDO4_VOLT=3300
+# Wifi power
++S:CONFIG_AXP221_ALDO1_VOLT=3300
+# HDMI power ?
++S:CONFIG_AXP221_ALDO2_VOLT=1800
++S:CONFIG_AXP221_ALDO3_VOLT=3000
+# No Vbus gpio for usb1
++S:CONFIG_USB1_VBUS_PIN=""
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MINI_X_1GB,AXP209_POWER,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MINI_X_1GB=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="MINI_X,AXP209_POWER,USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-mini-xplus.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_MINI_X=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="NAND,NOR"
+CONFIG_SYS_EXTRA_OPTIONS="NAND"
CONFIG_CONS_INDEX=1
+S:CONFIG_ARM=y
+S:CONFIG_TARGET_AM335X_EVM=y
+CONFIG_NOR=y
-CONFIG_SYS_EXTRA_OPTIONS="NOR,NOR_BOOT"
CONFIG_CONS_INDEX=1
CONFIG_ARM=y
CONFIG_TARGET_AM335X_EVM=y
+CONFIG_NOR=y
+CONFIG_NOR_BOOT=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="BA10_TV_BOX,AXP209_POWER,SUNXI_EMAC,USB_EHCI,SUNXI_USB_VBUS1_GPIO=SUNXI_GPH(12)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC,USB_EHCI"
CONFIG_FDTFILE="sun4i-a10-ba10-tvbox.dtb"
+CONFIG_USB1_VBUS_PIN="PH12"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN4I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN4I=y
++S:CONFIG_TARGET_BA10_TV_BOX=y
--- /dev/null
+CONFIG_SPL=n
++S:CONFIG_ARM=y
++S:CONFIG_OMAP34XX=y
++S:CONFIG_TARGET_CM_T3517=y
CONFIG_SYS_EXTRA_OPTIONS="DBAU1000"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1100"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1100=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1500"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1500=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1550"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_DBAU1550=y
-CONFIG_SYS_EXTRA_OPTIONS="DBAU1550,SYS_LITTLE_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_DBAU1X00=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_DBAU1550=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GR_CPCI_AX2000=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GR_EP2S60=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GR_XC3S_1500=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GRSIM=y
+CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_SPARC=y
CONFIG_TARGET_GRSIM_LEON2=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="I12_TVBOX,AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_I12_TVBOX=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
+CONFIG_SYS_BIG_ENDIAN=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_MALTA=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_MX6SABRESD=y
+
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/kosagi/novena/setup.cfg,MX6Q"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_KOSAGI_NOVENA=y
CONFIG_SYS_EXTRA_OPTIONS="PB1000"
CONFIG_MIPS=y
CONFIG_TARGET_PB1X00=y
+CONFIG_SYS_LITTLE_ENDIAN=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_DM_SERIAL=y
CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
S:CONFIG_SPL_NAND_DENALI=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_DM_SERIAL=y
CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
S:CONFIG_SPL_NAND_DENALI=y
CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
CONFIG_DM_SERIAL=y
CONFIG_UNIPHIER_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
S:CONFIG_SPL_NAND_DENALI=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="PRS200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="PRS200,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
+++ /dev/null
-CONFIG_SYS_EXTRA_OPTIONS="PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MCC200=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
CONFIG_MIPS=y
-CONFIG_TARGET_QEMU_MIPS64=y
+CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_CPU_MIPS64_R1=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
CONFIG_MIPS=y
-CONFIG_TARGET_QEMU_MIPS64=y
+CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS64_R1=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_CPU_MIPS32_R2=y
-CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN"
CONFIG_MIPS=y
CONFIG_TARGET_QEMU_MIPS=y
+CONFIG_SYS_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32_R2=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="QT840A,AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
+CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,MACPWR=SUNXI_GPH(21),USB_EHCI"
CONFIG_FDTFILE="sun7i-a20-i12-tvbox.dtb"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN7I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN7I=y
++S:CONFIG_TARGET_QT840A=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="R7DONGLE,AXP152_POWER,USB_EHCI,SUNXI_USB_VBUS0_GPIO=SUNXI_GPG(13)"
+CONFIG_SYS_EXTRA_OPTIONS="AXP152_POWER,USB_EHCI"
CONFIG_FDTFILE="sun5i-a10s-r7-tv-dongle.dtb"
+CONFIG_USB1_VBUS_PIN="PG13"
+S:CONFIG_ARM=y
-+S:CONFIG_TARGET_SUN5I=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN5I=y
++S:CONFIG_TARGET_R7DONGLE=y
--- /dev/null
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q"
+CONFIG_ARM=y
+CONFIG_TARGET_TBS2910=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_ONENAND=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUM=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_ONENAND=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PLATINUMAVC=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_ONENAND=y
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_ONENAND=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
-CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_SMALL_IMAGE"
CONFIG_MIPS=y
CONFIG_TARGET_VCT=y
+CONFIG_SYS_BIG_ENDIAN=y
+CONFIG_VCT_PREMIUM=y
+CONFIG_VCT_SMALL_IMAGE=y
# CONFIG_CMD_CRC32 is not set
--- /dev/null
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_ZYNQ=y
++S:CONFIG_TARGET_ZYNQ_ZYBO=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-zybo"
image that can be flashed on the board NAND/SPI flash. The make target
which uses mkimage to produce such an image is "u-boot.kwb". For example:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
make distclean
make yourboard_config
- make $BUILD_DIR/u-boot.kwb
+ make u-boot.kwb
Board specific configuration file specifications:
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-TOP5200 powerpc mpc5200 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-TOP860 powerpc mpc860 - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
-TOP9000 arm at91sam9xeXXX - - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+PRS200 powerpc mpc5200 - -
+MCC200 powerpc mpc5200 - -
+TOP5200 powerpc mpc5200 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TOP860 powerpc mpc860 d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
+TOP9000 arm at91sam9xeXXX d58a945 2014-10-28 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
TQM8272 powerpc mpc8260 f06f9a1 2014-10-27 Wolfgang Denk <wd@denx.de>
TQM8260 powerpc mpc8260 ccc1950 2014-10-27 Wolfgang Denk <wd@denx.de>
IDS8247 powerpc mpc8260 6afb357 2014-10-27 Heiko Schocher <hs@denx.de>
--- /dev/null
+SoCFPGA EPCS/EPCQx1 mini howto:
+- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild
+- The controller base address is the "Base" in QSys + 0x400
+- Set MSEL[4:0]=10010 (AS Standard)
+- Load the bitstream into FPGA, enable bridges
+- Only then will the driver work
.TP
.BI "\-F"
Indicates that an existing FIT image should be modified. No dtc
-compilation is performed and the -f flag should not be given.
+compilation is performed and the \-f flag should not be given.
This can be used to sign images with additional keys after initial image
creation.
skipping those for which keys cannot be found. Also add a comment.
.nf
.B mkimage -f kernel.its -k /public/signing-keys -K u-boot.dtb \\\\
--c "Kernel 3.8 image for production devices" kernel.itb
+.br
+.B -c "Kernel 3.8 image for production devices" kernel.itb
.fi
.P
with unavailable keys are skipped.
.nf
.B mkimage -F -k /secret/signing-keys -K u-boot.dtb \\\\
--c "Kernel 3.8 image for production devices" kernel.itb
+.br
+.B -c "Kernel 3.8 image for production devices" kernel.itb
.fi
.SH HOMEPAGE
{
u32 j;
- if (qm_cfg == NULL)
- return;
-
queue_close(qm_cfg->qpool_num);
qm_cfg->mngr_cfg->link_ram_base0 = 0;
{
u32 regd;
- if (!qm_cfg)
- return;
-
cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
{
u32 uhd;
- if (!qm_cfg)
- return NULL;
-
uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
if (uhd)
cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
struct qm_host_desc *qm_pop_from_free_pool(void)
{
- if (!qm_cfg)
- return NULL;
-
return qm_pop(qm_cfg->qpool_num);
}
*/
#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
#include <asm/io.h>
#include <asm/gpio.h>
+#include <dm/device-internal.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SUNXI_GPIOS_PER_BANK SUNXI_GPIO_A_NR
+
+struct sunxi_gpio_platdata {
+ struct sunxi_gpio *regs;
+ const char *bank_name; /* Name of bank, e.g. "B" */
+ int gpio_count;
+};
+
+#ifndef CONFIG_DM_GPIO
static int sunxi_gpio_output(u32 pin, u32 val)
{
u32 dat;
return -1;
return group * 32 + pin;
}
+#endif
+
+#ifdef CONFIG_DM_GPIO
+static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+
+ sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT);
+
+ return 0;
+}
+
+static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ u32 num = GPIO_NUM(offset);
+
+ sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT);
+ clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
+
+ return 0;
+}
+
+static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ u32 num = GPIO_NUM(offset);
+ unsigned dat;
+
+ dat = readl(&plat->regs->dat);
+ dat >>= num;
+
+ return dat & 0x1;
+}
+
+static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ u32 num = GPIO_NUM(offset);
+
+ clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0);
+ return 0;
+}
+
+static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ int func;
+
+ func = sunxi_gpio_get_cfgbank(plat->regs, offset);
+ if (func == SUNXI_GPIO_OUTPUT)
+ return GPIOF_OUTPUT;
+ else if (func == SUNXI_GPIO_INPUT)
+ return GPIOF_INPUT;
+ else
+ return GPIOF_FUNC;
+}
+
+static const struct dm_gpio_ops gpio_sunxi_ops = {
+ .direction_input = sunxi_gpio_direction_input,
+ .direction_output = sunxi_gpio_direction_output,
+ .get_value = sunxi_gpio_get_value,
+ .set_value = sunxi_gpio_set_value,
+ .get_function = sunxi_gpio_get_function,
+};
+
+/**
+ * Returns the name of a GPIO bank
+ *
+ * GPIO banks are named A, B, C, ...
+ *
+ * @bank: Bank number (0, 1..n-1)
+ * @return allocated string containing the name
+ */
+static char *gpio_bank_name(int bank)
+{
+ char *name;
+
+ name = malloc(2);
+ if (name) {
+ name[0] = 'A' + bank;
+ name[1] = '\0';
+ }
+
+ return name;
+}
+
+static int gpio_sunxi_probe(struct udevice *dev)
+{
+ struct sunxi_gpio_platdata *plat = dev_get_platdata(dev);
+ struct gpio_dev_priv *uc_priv = dev->uclass_priv;
+
+ /* Tell the uclass how many GPIOs we have */
+ if (plat) {
+ uc_priv->gpio_count = plat->gpio_count;
+ uc_priv->bank_name = plat->bank_name;
+ }
+
+ return 0;
+}
+/**
+ * We have a top-level GPIO device with no actual GPIOs. It has a child
+ * device for each Sunxi bank.
+ */
+static int gpio_sunxi_bind(struct udevice *parent)
+{
+ struct sunxi_gpio_platdata *plat = parent->platdata;
+ struct sunxi_gpio_reg *ctlr;
+ int bank;
+ int ret;
+
+ /* If this is a child device, there is nothing to do here */
+ if (plat)
+ return 0;
+
+ ctlr = (struct sunxi_gpio_reg *)fdtdec_get_addr(gd->fdt_blob,
+ parent->of_offset, "reg");
+ for (bank = 0; bank < SUNXI_GPIO_BANKS; bank++) {
+ struct sunxi_gpio_platdata *plat;
+ struct udevice *dev;
+
+ plat = calloc(1, sizeof(*plat));
+ if (!plat)
+ return -ENOMEM;
+ plat->regs = &ctlr->gpio_bank[bank];
+ plat->bank_name = gpio_bank_name(bank);
+ plat->gpio_count = SUNXI_GPIOS_PER_BANK;
+
+ ret = device_bind(parent, parent->driver,
+ plat->bank_name, plat, -1, &dev);
+ if (ret)
+ return ret;
+ dev->of_offset = parent->of_offset;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id sunxi_gpio_ids[] = {
+ { .compatible = "allwinner,sun7i-a20-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(gpio_sunxi) = {
+ .name = "gpio_sunxi",
+ .id = UCLASS_GPIO,
+ .ops = &gpio_sunxi_ops,
+ .of_match = sunxi_gpio_ids,
+ .bind = gpio_sunxi_bind,
+ .probe = gpio_sunxi_probe,
+};
+#endif
* generic value.
*/
#ifndef CONFIG_I2C_TIMEOUT
-#define CONFIG_I2C_TIMEOUT 10000
+#define CONFIG_I2C_TIMEOUT 100000
#endif
#define I2C_READ_BIT 1
}
/* implement possible board specific board init */
-static void __def_i2c_init_board(void)
+__weak void i2c_init_board(void)
{
}
-void i2c_init_board(void)
- __attribute__((weak, alias("__def_i2c_init_board")));
/*
* i2c_init_all():
i2c_write(addr, reg, 1, &val, 1);
}
-void __i2c_init(int speed, int slaveaddr)
+__weak void i2c_init(int speed, int slaveaddr)
{
i2c_init_bus(i2c_get_bus_num(), speed, slaveaddr);
}
-void i2c_init(int speed, int slaveaddr)
- __attribute__((weak, alias("__i2c_init")));
*
* Typical case is a Write of an addr followd by a Read. The
* IBM FAQ does not cover this. On the last byte of the write
- * we don't set the creg CHT bit, and on the first bytes of the
- * read we set the RPST bit.
+ * we don't set the creg CHT bit but the RPST bit.
*
* It does not support address only transfers, there must be
* a data part. If you want to write the address yourself, put
if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
creg |= IIC_CNTL_CHT;
+ /* last part of address, prepare for repeated start on read */
+ if (cmd_type && (ptr == addr) && ((tran + bc) == cnt))
+ creg |= IIC_CNTL_RPST;
+
if (reading) {
creg |= IIC_CNTL_READ;
} else {
/* Transfer aborted? */
if (status & IIC_EXTSTS_XFRA)
result = IIC_NOK_XFRA;
+ /* Is bus free?
+ * If error happened during combined xfer
+ * IIC interface is usually stuck in some strange
+ * state without a valid stop condition.
+ * Brute, but working: generate stop, then soft reset.
+ */
+ if ((status & IIC_EXTSTS_BCS_MASK)
+ != IIC_EXTSTS_BCS_FREE){
+ u8 mdcntl = in_8(&i2c->mdcntl);
+
+ /* Generate valid stop condition */
+ out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
+ out_8(&i2c->directcntl, IIC_DIRCNTL_SCC);
+ udelay(10);
+ out_8(&i2c->directcntl,
+ IIC_DIRCNTL_SCC | IIC_DIRCNTL_SDAC);
+ out_8(&i2c->xtcntlss, 0);
+
+ ppc4xx_i2c_init(adap, (mdcntl & IIC_MDCNTL_FSM)
+ ? 400000 : 100000, 0);
+ }
} else if ( status & IIC_STS_PT) {
result = IIC_NOK_TOUT;
}
cnt = data_len;
tran = 0;
reading = cmd_type;
- if (reading)
- creg = IIC_CNTL_RPST;
}
}
return result;
/* set slave address, receive */
writel((chip << 1) | 1, &dev->icmar);
- /* clear status */
- writel(0, &dev->icmsr);
/* start master receive */
writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr);
+ /* clear status */
+ writel(0, &dev->icmsr);
while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR))
!= (MSR_MAT | MSR_MDR))
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
obj-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+obj-$(CONFIG_DWMMC) += dw_mmc.o
+obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o
obj-$(CONFIG_GENERIC_MMC) += mmc.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
+obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
obj-$(CONFIG_MMC_SPI) += mmc_spi.o
-obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
+obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_MV_SDHCI) += mv_sdhci.o
+obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
obj-$(CONFIG_MXC_MMC) += mxcmmc.o
obj-$(CONFIG_MXS_MMC) += mxsmmc.o
obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
-obj-$(CONFIG_SDHCI) += sdhci.o
-obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
-obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o
+obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
+obj-$(CONFIG_SDHCI) += sdhci.o
obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o
+obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o
obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
-obj-$(CONFIG_DWMMC) += dw_mmc.o
-obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
-obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
-obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
-obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
+
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
else
obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
endif
-obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
+
if (cd_gpio < 0)
return 1;
- return gpio_get_value(cd_gpio);
+ /* NOTE: assumes card detect signal is active-low */
+ return !gpio_get_value(cd_gpio);
}
static int omap_hsmmc_getwp(struct mmc *mmc)
if (wp_gpio < 0)
return 0;
+ /* NOTE: assumes write protect signal is active-high */
return gpio_get_value(wp_gpio);
}
#endif
/* support 4 mmc hosts */
struct sunxi_mmc_host mmc_host[4];
+static int sunxi_mmc_getcd_gpio(int sdc_no)
+{
+ switch (sdc_no) {
+ case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
+ case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
+ case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
+ case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
+ }
+ return -1;
+}
+
static int mmc_resource_init(int sdc_no)
{
struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int cd_pin, ret = 0;
debug("init mmc %d resource\n", sdc_no);
}
mmchost->mmc_no = sdc_no;
- return 0;
+ cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
+ if (cd_pin != -1)
+ ret = gpio_request(cd_pin, "mmc_cd");
+
+ return ret;
}
static int mmc_clk_io_on(int sdc_no)
/* config ahb clock */
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
/* unassert reset */
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
#endif
static int sunxi_mmc_getcd(struct mmc *mmc)
{
struct sunxi_mmc_host *mmchost = mmc->priv;
- int cd_pin = -1;
-
- switch (mmchost->mmc_no) {
- case 0: cd_pin = sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN); break;
- case 1: cd_pin = sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN); break;
- case 2: cd_pin = sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN); break;
- case 3: cd_pin = sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN); break;
- }
+ int cd_pin;
+ cd_pin = sunxi_mmc_getcd_gpio(mmchost->mmc_no);
if (cd_pin == -1)
return 1;
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
cfg->host_caps = MMC_MODE_4BIT;
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN7I) || defined(CONFIG_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
cfg->host_caps |= MMC_MODE_HC;
#endif
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
cfg->f_min = 400000;
cfg->f_max = 52000000;
- mmc_resource_init(sdc_no);
+ if (mmc_resource_init(sdc_no) != 0)
+ return NULL;
+
mmc_clk_io_on(sdc_no);
return mmc_create(cfg, &mmc_host[sdc_no]);
static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
uint32_t page_oob_size)
{
- if (page_data_size == 2048)
- return 8;
+ if (page_data_size == 2048) {
+ if (page_oob_size == 64)
+ return 8;
+
+ if (page_oob_size == 112)
+ return 14;
+ }
if (page_data_size == 4096) {
if (page_oob_size == 128)
writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
-#ifdef CONFIG_K2E_EVM
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
/* Map RX packet flow priority to 0 */
writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
#endif
keystone2_net_serdes_setup();
+ if (sys_has_mdio)
+ keystone2_mdio_reset(mdio_bus);
+
keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
eth_priv->sgmii_link_type);
&ks2_serdes_sgmii_156p25mhz,
CONFIG_KSNET_SERDES_LANES_PER_SGMII);
-#ifdef CONFIG_SOC_K2E
+#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
&ks2_serdes_sgmii_156p25mhz,
CONFIG_KSNET_SERDES_LANES_PER_SGMII);
return 0;
}
+/**
+ * m88e1518_phy_writebits - write bits to a register
+ */
+void m88e1518_phy_writebits(struct phy_device *phydev,
+ u8 reg_num, u16 offset, u16 len, u16 data)
+{
+ u16 reg, mask;
+
+ if ((len + offset) >= 16)
+ mask = 0 - (1 << offset);
+ else
+ mask = (1 << (len + offset)) - (1 << offset);
+
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
+
+ reg &= ~mask;
+ reg |= data << offset;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
+}
+
+static int m88e1518_config(struct phy_device *phydev)
+{
+ /*
+ * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
+ * /88E1514 Rev A0, Errata Section 3.1
+ */
+ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); /* page 0xff */
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
+ phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
+ phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); /* reg page 0 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); /* reg page 18 */
+ /* Write HWCFG_MODE = SGMII to Copper */
+ m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
+
+ /* Phy reset */
+ m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
+ phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); /* reg page 18 */
+ udelay(100);
+ }
+
+ return m88e1111s_config(phydev);
+}
+
/* Marvell 88E1118 */
static int m88e1118_config(struct phy_device *phydev)
{
.uid = 0x1410dd1,
.mask = 0xffffff0,
.features = PHY_GBIT_FEATURES,
- .config = &m88e1111s_config,
+ .config = &m88e1518_config,
.startup = &m88e1011s_startup,
.shutdown = &genphy_shutdown,
};
* sh_eth.c - Driver for Renesas ethernet controler.
*
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
- * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
+ * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
- * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013, 2014 Renesas Electronics Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
else
port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
+ flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
+
/* Restart the transmitter if disabled */
if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
sh_eth_write(eth, EDTRR_TRNS, EDTRR);
port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
else
port_info->rx_desc_cur->rd0 = RD_RACT;
+
+ flush_cache_wback(port_info->rx_desc_cur,
+ sizeof(struct rx_desc_s));
+
/* Point to the next descriptor */
port_info->rx_desc_cur++;
if (port_info->rx_desc_cur >=
static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
{
int port = eth->port, i, ret = 0;
- u32 tmp_addr;
+ u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
struct sh_eth_info *port_info = ð->port_info[port];
struct tx_desc_s *cur_tx_desc;
/*
- * Allocate tx descriptors. They must be TX_DESC_SIZE bytes aligned
+ * Allocate rx descriptors. They must be aligned to size of struct
+ * tx_desc_s.
*/
- port_info->tx_desc_malloc = malloc(NUM_TX_DESC *
- sizeof(struct tx_desc_s) +
- TX_DESC_SIZE - 1);
- if (!port_info->tx_desc_malloc) {
- printf(SHETHER_NAME ": malloc failed\n");
+ port_info->tx_desc_alloc =
+ memalign(sizeof(struct tx_desc_s), alloc_desc_size);
+ if (!port_info->tx_desc_alloc) {
+ printf(SHETHER_NAME ": memalign failed\n");
ret = -ENOMEM;
goto err;
}
- tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
- ~(TX_DESC_SIZE - 1));
- flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
+ flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
+
/* Make sure we use a P2 address (non-cacheable) */
- port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
+ port_info->tx_desc_base =
+ (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
port_info->tx_desc_cur = port_info->tx_desc_base;
/* Initialize all descriptors */
static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
{
int port = eth->port, i , ret = 0;
+ u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
struct sh_eth_info *port_info = ð->port_info[port];
struct rx_desc_s *cur_rx_desc;
- u32 tmp_addr;
u8 *rx_buf;
/*
- * Allocate rx descriptors. They must be RX_DESC_SIZE bytes aligned
+ * Allocate rx descriptors. They must be aligned to size of struct
+ * rx_desc_s.
*/
- port_info->rx_desc_malloc = malloc(NUM_RX_DESC *
- sizeof(struct rx_desc_s) +
- RX_DESC_SIZE - 1);
- if (!port_info->rx_desc_malloc) {
- printf(SHETHER_NAME ": malloc failed\n");
+ port_info->rx_desc_alloc =
+ memalign(sizeof(struct rx_desc_s), alloc_desc_size);
+ if (!port_info->rx_desc_alloc) {
+ printf(SHETHER_NAME ": memalign failed\n");
ret = -ENOMEM;
goto err;
}
- tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
- ~(RX_DESC_SIZE - 1));
- flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
+ flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
+
/* Make sure we use a P2 address (non-cacheable) */
- port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);
+ port_info->rx_desc_base =
+ (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
port_info->rx_desc_cur = port_info->rx_desc_base;
/*
- * Allocate rx data buffers. They must be 32 bytes aligned and in
- * P2 area
+ * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
+ * aligned and in P2 area.
*/
- port_info->rx_buf_malloc = malloc(
- NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
- if (!port_info->rx_buf_malloc) {
- printf(SHETHER_NAME ": malloc failed\n");
+ port_info->rx_buf_alloc =
+ memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
+ if (!port_info->rx_buf_alloc) {
+ printf(SHETHER_NAME ": alloc failed\n");
ret = -ENOMEM;
- goto err_buf_malloc;
+ goto err_buf_alloc;
}
- tmp_addr = (u32)(((int)port_info->rx_buf_malloc
- + (RX_BUF_ALIGNE_SIZE - 1)) &
- ~(RX_BUF_ALIGNE_SIZE - 1));
- port_info->rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
+ port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
/* Initialize all descriptors */
for (cur_rx_desc = port_info->rx_desc_base,
return ret;
-err_buf_malloc:
- free(port_info->rx_desc_malloc);
- port_info->rx_desc_malloc = NULL;
+err_buf_alloc:
+ free(port_info->rx_desc_alloc);
+ port_info->rx_desc_alloc = NULL;
err:
return ret;
int port = eth->port;
struct sh_eth_info *port_info = ð->port_info[port];
- if (port_info->tx_desc_malloc) {
- free(port_info->tx_desc_malloc);
- port_info->tx_desc_malloc = NULL;
+ if (port_info->tx_desc_alloc) {
+ free(port_info->tx_desc_alloc);
+ port_info->tx_desc_alloc = NULL;
}
}
int port = eth->port;
struct sh_eth_info *port_info = ð->port_info[port];
- if (port_info->rx_desc_malloc) {
- free(port_info->rx_desc_malloc);
- port_info->rx_desc_malloc = NULL;
+ if (port_info->rx_desc_alloc) {
+ free(port_info->rx_desc_alloc);
+ port_info->rx_desc_alloc = NULL;
}
- if (port_info->rx_buf_malloc) {
- free(port_info->rx_buf_malloc);
- port_info->rx_buf_malloc = NULL;
+ if (port_info->rx_buf_alloc) {
+ free(port_info->rx_buf_alloc);
+ port_info->rx_buf_alloc = NULL;
}
}
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
#endif
/* Configure phy */
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
- defined(CONFIG_R8A7791) || defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+ defined(CONFIG_R8A7794)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
-/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
-#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
/* aligned cache line size */
#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
};
struct sh_eth_info {
- struct tx_desc_s *tx_desc_malloc;
+ struct tx_desc_s *tx_desc_alloc;
struct tx_desc_s *tx_desc_base;
struct tx_desc_s *tx_desc_cur;
- struct rx_desc_s *rx_desc_malloc;
+ struct rx_desc_s *rx_desc_alloc;
struct rx_desc_s *rx_desc_base;
struct rx_desc_s *rx_desc_cur;
- u8 *rx_buf_malloc;
+ u8 *rx_buf_alloc;
u8 *rx_buf_base;
u8 mac_addr[6];
u8 phy_addr;
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
#elif defined(CONFIG_R7S72100)
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
ECMR_RTM = 0x00000004,
#endif
static void smc911x_halt(struct eth_device *dev)
{
smc911x_reset(dev);
+ smc911x_handle_mac_address(dev);
}
static int smc911x_rx(struct eth_device *dev)
rdes0 = le32_to_cpu(rxptr->rdes0);
#ifdef RX_DEBUG
- printf("%s(): rxptr->rdes0=%x:%x\n", __FUNCTION__, rxptr->rdes0);
+ printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0);
#endif
if (!(rdes0 & 0x80000000)) { /* packet owner check */
if ((rdes0 & 0x300) != 0x300) {
+config AXP221_POWER
+ boolean "axp221 pmic support"
+ depends on MACH_SUN6I
+ default y
+ ---help---
+ Say y here to enable support for the axp221 pmic found on most sun6i
+ (A31) boards.
+
+config AXP221_DLDO1_VOLT
+ int "axp221 dldo1 voltage"
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 dldo1 at, set to -1 to
+ disable dldo1.
+
+config AXP221_DLDO4_VOLT
+ int "axp221 dldo4 voltage"
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 dldo4 at, set to -1 to
+ disable dldo4.
+
+config AXP221_ALDO1_VOLT
+ int "axp221 aldo1 voltage"
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 aldo1 at, set to -1 to
+ disable aldo1.
+
+config AXP221_ALDO2_VOLT
+ int "axp221 aldo2 voltage"
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 aldo2 at, set to -1 to
+ disable aldo2.
+
+config AXP221_ALDO3_VOLT
+ int "axp221 aldo3 voltage"
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 aldo3 at, set to -1 to
+ disable aldo3.
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
+obj-$(CONFIG_AXP221_POWER) += axp221.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o
--- /dev/null
+/*
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/p2wi.h>
+#include <axp221.h>
+
+static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+ if (mvolt < min)
+ mvolt = min;
+ else if (mvolt > max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+static int axp221_setbits(u8 reg, u8 bits)
+{
+ int ret;
+ u8 val;
+
+ ret = p2wi_read(reg, &val);
+ if (ret)
+ return ret;
+
+ val |= bits;
+ return p2wi_write(reg, val);
+}
+
+int axp221_set_dcdc1(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100);
+
+ ret = p2wi_write(AXP221_DCDC1_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DCDC1_EN);
+}
+
+int axp221_set_dcdc2(unsigned int mvolt)
+{
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+ return p2wi_write(AXP221_DCDC2_CTRL, cfg);
+}
+
+int axp221_set_dcdc3(unsigned int mvolt)
+{
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1860, 20);
+
+ return p2wi_write(AXP221_DCDC3_CTRL, cfg);
+}
+
+int axp221_set_dcdc4(unsigned int mvolt)
+{
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 600, 1540, 20);
+
+ return p2wi_write(AXP221_DCDC4_CTRL, cfg);
+}
+
+int axp221_set_dcdc5(unsigned int mvolt)
+{
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 1000, 2550, 50);
+
+ return p2wi_write(AXP221_DCDC5_CTRL, cfg);
+}
+
+int axp221_set_dldo1(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+ ret = p2wi_write(AXP221_DLDO1_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO1_EN);
+}
+
+int axp221_set_dldo2(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+ ret = p2wi_write(AXP221_DLDO2_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO2_EN);
+}
+
+int axp221_set_dldo3(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+ ret = p2wi_write(AXP221_DLDO3_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO3_EN);
+}
+
+int axp221_set_dldo4(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+ ret = p2wi_write(AXP221_DLDO4_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL2,
+ AXP221_OUTPUT_CTRL2_DLDO4_EN);
+}
+
+int axp221_set_aldo1(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+ ret = p2wi_write(AXP221_ALDO1_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_ALDO1_EN);
+}
+
+int axp221_set_aldo2(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+ ret = p2wi_write(AXP221_ALDO2_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL1,
+ AXP221_OUTPUT_CTRL1_ALDO2_EN);
+}
+
+int axp221_set_aldo3(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 700, 3300, 100);
+
+ ret = p2wi_write(AXP221_ALDO3_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ return axp221_setbits(AXP221_OUTPUT_CTRL3,
+ AXP221_OUTPUT_CTRL3_ALDO3_EN);
+}
+
+int axp221_init(void)
+{
+ u8 axp_chip_id;
+ int ret;
+
+ p2wi_init();
+ ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
+ AXP221_INIT_DATA);
+ if (ret)
+ return ret;
+
+ ret = p2wi_read(AXP221_CHIP_ID, &axp_chip_id);
+ if (ret)
+ return ret;
+
+ if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17))
+ return -ENODEV;
+
+ return 0;
+}
static struct spi_slave *slave;
-void pmic_spi_free(struct spi_slave *slave)
-{
- if (slave)
- spi_free_slave(slave);
-}
-
-struct spi_slave *pmic_spi_probe(struct pmic *p)
-{
- return spi_setup_slave(p->bus,
- p->hw.spi.cs,
- p->hw.spi.clk,
- p->hw.spi.mode);
-}
-
static u32 pmic_reg(struct pmic *p, u32 reg, u32 *val, u32 write)
{
u32 pmic_tx, pmic_rx;
u32 tmp;
if (!slave) {
- slave = pmic_spi_probe(p);
+ slave = spi_setup_slave(p->bus, p->hw.spi.cs, p->hw.spi.clk,
+ p->hw.spi.mode);
if (!slave)
return -1;
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
- pmic_spi_flags)) {
- spi_release_bus(slave);
- return -1;
- }
+ pmic_spi_flags))
+ goto err;
if (write) {
pmic_tx = p->hw.spi.prepare_tx(reg, val, 0);
tmp = cpu_to_be32(pmic_tx);
if (spi_xfer(slave, pmic_spi_bitlen, &tmp, &pmic_rx,
- pmic_spi_flags)) {
- spi_release_bus(slave);
- return -1;
- }
+ pmic_spi_flags))
+ goto err;
}
spi_release_bus(slave);
*val = cpu_to_be32(pmic_rx);
return 0;
+
+err:
+ spi_release_bus(slave);
+ return -1;
}
int pmic_reg_write(struct pmic *p, u32 reg, u32 val)
TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ /* Set VMMC2 to 3.15 Volts */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
+ TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
+ TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
}
obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
+obj-$(CONFIG_DW_SERIAL) += serial_dw.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o
obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
void name(void) \
__attribute__((weak, alias("serial_null")));
-serial_initfunc(mpc8xx_serial_initialize);
-serial_initfunc(ns16550_serial_initialize);
-serial_initfunc(pxa_serial_initialize);
-serial_initfunc(s3c24xx_serial_initialize);
-serial_initfunc(s5p_serial_initialize);
-serial_initfunc(zynq_serial_initialize);
-serial_initfunc(bfin_serial_initialize);
-serial_initfunc(bfin_jtag_initialize);
-serial_initfunc(mpc512x_serial_initialize);
-serial_initfunc(uartlite_serial_initialize);
-serial_initfunc(au1x00_serial_initialize);
-serial_initfunc(asc_serial_initialize);
-serial_initfunc(jz_serial_initialize);
-serial_initfunc(mpc5xx_serial_initialize);
-serial_initfunc(mpc8260_scc_serial_initialize);
-serial_initfunc(mpc8260_smc_serial_initialize);
-serial_initfunc(mpc85xx_serial_initialize);
-serial_initfunc(iop480_serial_initialize);
-serial_initfunc(leon2_serial_initialize);
-serial_initfunc(leon3_serial_initialize);
-serial_initfunc(marvell_serial_initialize);
+serial_initfunc(altera_jtag_serial_initialize);
+serial_initfunc(altera_serial_initialize);
serial_initfunc(amirix_serial_initialize);
+serial_initfunc(arc_serial_initialize);
+serial_initfunc(arm_dcc_initialize);
+serial_initfunc(asc_serial_initialize);
+serial_initfunc(atmel_serial_initialize);
+serial_initfunc(au1x00_serial_initialize);
+serial_initfunc(bfin_jtag_initialize);
+serial_initfunc(bfin_serial_initialize);
serial_initfunc(bmw_serial_initialize);
+serial_initfunc(clps7111_serial_initialize);
serial_initfunc(cogent_serial_initialize);
serial_initfunc(cpci750_serial_initialize);
serial_initfunc(evb64260_serial_initialize);
-serial_initfunc(ml2_serial_initialize);
-serial_initfunc(sconsole_serial_initialize);
-serial_initfunc(p3mx_serial_initialize);
-serial_initfunc(altera_jtag_serial_initialize);
-serial_initfunc(altera_serial_initialize);
-serial_initfunc(atmel_serial_initialize);
-serial_initfunc(lpc32xx_serial_initialize);
-serial_initfunc(mcf_serial_initialize);
-serial_initfunc(oc_serial_initialize);
-serial_initfunc(sandbox_serial_initialize);
-serial_initfunc(clps7111_serial_initialize);
serial_initfunc(imx_serial_initialize);
+serial_initfunc(iop480_serial_initialize);
+serial_initfunc(jz_serial_initialize);
serial_initfunc(ks8695_serial_initialize);
+serial_initfunc(leon2_serial_initialize);
+serial_initfunc(leon3_serial_initialize);
serial_initfunc(lh7a40x_serial_initialize);
+serial_initfunc(lpc32xx_serial_initialize);
+serial_initfunc(marvell_serial_initialize);
serial_initfunc(max3100_serial_initialize);
+serial_initfunc(mcf_serial_initialize);
+serial_initfunc(ml2_serial_initialize);
+serial_initfunc(mpc512x_serial_initialize);
+serial_initfunc(mpc5xx_serial_initialize);
+serial_initfunc(mpc8260_scc_serial_initialize);
+serial_initfunc(mpc8260_smc_serial_initialize);
+serial_initfunc(mpc85xx_serial_initialize);
+serial_initfunc(mpc8xx_serial_initialize);
serial_initfunc(mxc_serial_initialize);
+serial_initfunc(mxs_auart_initialize);
+serial_initfunc(ns16550_serial_initialize);
+serial_initfunc(oc_serial_initialize);
+serial_initfunc(p3mx_serial_initialize);
serial_initfunc(pl01x_serial_initialize);
+serial_initfunc(pxa_serial_initialize);
+serial_initfunc(s3c24xx_serial_initialize);
+serial_initfunc(s5p_serial_initialize);
serial_initfunc(sa1100_serial_initialize);
+serial_initfunc(sandbox_serial_initialize);
+serial_initfunc(sconsole_serial_initialize);
serial_initfunc(sh_serial_initialize);
-serial_initfunc(arm_dcc_initialize);
-serial_initfunc(mxs_auart_initialize);
-serial_initfunc(arc_serial_initialize);
+serial_initfunc(uartlite_serial_initialize);
+serial_initfunc(zynq_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
*/
void serial_initialize(void)
{
- mpc8xx_serial_initialize();
- ns16550_serial_initialize();
- pxa_serial_initialize();
- s3c24xx_serial_initialize();
- s5p_serial_initialize();
- mpc512x_serial_initialize();
- bfin_serial_initialize();
- bfin_jtag_initialize();
- uartlite_serial_initialize();
- zynq_serial_initialize();
- au1x00_serial_initialize();
- asc_serial_initialize();
- jz_serial_initialize();
- mpc5xx_serial_initialize();
- mpc8260_scc_serial_initialize();
- mpc8260_smc_serial_initialize();
- mpc85xx_serial_initialize();
- iop480_serial_initialize();
- leon2_serial_initialize();
- leon3_serial_initialize();
- marvell_serial_initialize();
+ altera_jtag_serial_initialize();
+ altera_serial_initialize();
amirix_serial_initialize();
+ arc_serial_initialize();
+ arm_dcc_initialize();
+ asc_serial_initialize();
+ atmel_serial_initialize();
+ au1x00_serial_initialize();
+ bfin_jtag_initialize();
+ bfin_serial_initialize();
bmw_serial_initialize();
+ clps7111_serial_initialize();
cogent_serial_initialize();
cpci750_serial_initialize();
evb64260_serial_initialize();
- ml2_serial_initialize();
- sconsole_serial_initialize();
- p3mx_serial_initialize();
- altera_jtag_serial_initialize();
- altera_serial_initialize();
- atmel_serial_initialize();
- lpc32xx_serial_initialize();
- mcf_serial_initialize();
- oc_serial_initialize();
- sandbox_serial_initialize();
- clps7111_serial_initialize();
imx_serial_initialize();
+ iop480_serial_initialize();
+ jz_serial_initialize();
ks8695_serial_initialize();
+ leon2_serial_initialize();
+ leon3_serial_initialize();
lh7a40x_serial_initialize();
+ lpc32xx_serial_initialize();
+ marvell_serial_initialize();
max3100_serial_initialize();
+ mcf_serial_initialize();
+ ml2_serial_initialize();
+ mpc512x_serial_initialize();
+ mpc5xx_serial_initialize();
+ mpc8260_scc_serial_initialize();
+ mpc8260_smc_serial_initialize();
+ mpc85xx_serial_initialize();
+ mpc8xx_serial_initialize();
mxc_serial_initialize();
+ mxs_auart_initialize();
+ ns16550_serial_initialize();
+ oc_serial_initialize();
+ p3mx_serial_initialize();
pl01x_serial_initialize();
+ pxa_serial_initialize();
+ s3c24xx_serial_initialize();
+ s5p_serial_initialize();
sa1100_serial_initialize();
+ sandbox_serial_initialize();
+ sconsole_serial_initialize();
sh_serial_initialize();
- arm_dcc_initialize();
- mxs_auart_initialize();
- arc_serial_initialize();
+ uartlite_serial_initialize();
+ zynq_serial_initialize();
serial_assign(default_serial_console()->name);
}
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id dw_serial_ids[] = {
+ { .compatible = "snps,dw-apb-uart" },
+ { }
+};
+
+static int dw_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = ns16550_serial_ofdata_to_platdata(dev);
+ if (ret)
+ return ret;
+ plat->clock = CONFIG_SYS_NS16550_CLK;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+ .name = "serial_dw",
+ .id = UCLASS_SERIAL,
+ .of_match = dw_serial_ids,
+ .ofdata_to_platdata = dw_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops = &ns16550_serial_ops,
+};
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ORER 0x0001
# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x003f
#else
SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
#endif
#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
- defined(CONFIG_R8A7794)
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
SCIF_FNS(DL, 0, 0, 0x30, 16)
SCIF_FNS(CKS, 0, 0, 0x34, 16)
#endif
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
#define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) /* Internal Clock */
#else /* Generic SH */
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
+#include <linux/serial_reg.h>
#include <asm/io.h>
#include <asm/errno.h>
#include <dm/device.h>
#define thr rbr
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_DR 0x01 /* Data ready */
-#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
-
struct uniphier_serial_private_data {
struct uniphier_serial __iomem *membase;
};
#define uniphier_serial_port(dev) \
((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase
-int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
+static int uniphier_serial_setbrg(struct udevice *dev, int baudrate)
{
struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
const unsigned int mode_x_div = 16;
unsigned int divisor;
- writeb(UART_LCR_WLS_8, &port->lcr);
+ writeb(UART_LCR_WLEN8, &port->lcr);
divisor = DIV_ROUND_CLOSEST(plat->uartclk, mode_x_div * baudrate);
return 0;
}
-int uniphier_serial_probe(struct udevice *dev)
+static int uniphier_serial_pending(struct udevice *dev, bool input)
+{
+ struct uniphier_serial __iomem *port = uniphier_serial_port(dev);
+
+ if (input)
+ return readb(&port->lsr) & UART_LSR_DR;
+ else
+ return !(readb(&port->lsr) & UART_LSR_THRE);
+}
+
+static int uniphier_serial_probe(struct udevice *dev)
{
struct uniphier_serial_private_data *priv = dev_get_priv(dev);
struct uniphier_serial_platform_data *plat = dev_get_platdata(dev);
return 0;
}
-int uniphier_serial_remove(struct udevice *dev)
+static int uniphier_serial_remove(struct udevice *dev)
{
unmap_sysmem(uniphier_serial_port(dev));
.setbrg = uniphier_serial_setbrg,
.getc = uniphier_serial_getc,
.putc = uniphier_serial_putc,
+ .pending = uniphier_serial_pending,
};
U_BOOT_DRIVER(uniphier_serial) = {
#include <malloc.h>
#include <spi.h>
-#define ALTERA_SPI_RXDATA 0
-#define ALTERA_SPI_TXDATA 4
-#define ALTERA_SPI_STATUS 8
-#define ALTERA_SPI_CONTROL 12
-#define ALTERA_SPI_SLAVE_SEL 20
-
-#define ALTERA_SPI_STATUS_ROE_MSK (0x8)
-#define ALTERA_SPI_STATUS_TOE_MSK (0x10)
-#define ALTERA_SPI_STATUS_TMT_MSK (0x20)
-#define ALTERA_SPI_STATUS_TRDY_MSK (0x40)
-#define ALTERA_SPI_STATUS_RRDY_MSK (0x80)
-#define ALTERA_SPI_STATUS_E_MSK (0x100)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK (0x8)
-#define ALTERA_SPI_CONTROL_ITOE_MSK (0x10)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK (0x40)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK (0x80)
-#define ALTERA_SPI_CONTROL_IE_MSK (0x100)
-#define ALTERA_SPI_CONTROL_SSO_MSK (0x400)
+#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
+#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
+#endif
#ifndef CONFIG_SYS_ALTERA_SPI_LIST
#define CONFIG_SYS_ALTERA_SPI_LIST { CONFIG_SYS_SPI_BASE }
#endif
+struct altera_spi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 status;
+ u32 control;
+ u32 _reserved;
+ u32 slave_sel;
+};
+
+#define ALTERA_SPI_STATUS_ROE_MSK (1 << 3)
+#define ALTERA_SPI_STATUS_TOE_MSK (1 << 4)
+#define ALTERA_SPI_STATUS_TMT_MSK (1 << 5)
+#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6)
+#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7)
+#define ALTERA_SPI_STATUS_E_MSK (1 << 8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSK (1 << 3)
+#define ALTERA_SPI_CONTROL_ITOE_MSK (1 << 4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 << 6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 << 7)
+#define ALTERA_SPI_CONTROL_IE_MSK (1 << 8)
+#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10)
+
static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
struct altera_spi_slave {
- struct spi_slave slave;
- ulong base;
+ struct spi_slave slave;
+ struct altera_spi_regs *regs;
};
#define to_altera_spi_slave(s) container_of(s, struct altera_spi_slave, slave)
-__attribute__((weak))
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+__weak int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus < ARRAY_SIZE(altera_spi_base_list) && cs < 32;
}
-__attribute__((weak))
-void spi_cs_activate(struct spi_slave *slave)
+__weak void spi_cs_activate(struct spi_slave *slave)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
- writel(1 << slave->cs, altspi->base + ALTERA_SPI_SLAVE_SEL);
- writel(ALTERA_SPI_CONTROL_SSO_MSK, altspi->base + ALTERA_SPI_CONTROL);
+ writel(1 << slave->cs, &altspi->regs->slave_sel);
+ writel(ALTERA_SPI_CONTROL_SSO_MSK, &altspi->regs->control);
}
-__attribute__((weak))
-void spi_cs_deactivate(struct spi_slave *slave)
+__weak void spi_cs_deactivate(struct spi_slave *slave)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
- writel(0, altspi->base + ALTERA_SPI_CONTROL);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->control);
+ writel(0, &altspi->regs->slave_sel);
}
void spi_init(void)
if (!altspi)
return NULL;
- altspi->base = altera_spi_base_list[bus];
- debug("%s: bus:%i cs:%i base:%lx\n", __func__,
- bus, cs, altspi->base);
+ altspi->regs = (struct altera_spi_regs *)altera_spi_base_list[bus];
+ debug("%s: bus:%i cs:%i base:%p\n", __func__, bus, cs, altspi->regs);
return &altspi->slave;
}
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- writel(0, altspi->base + ALTERA_SPI_CONTROL);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->control);
+ writel(0, &altspi->regs->slave_sel);
return 0;
}
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
- writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL);
+ writel(0, &altspi->regs->slave_sel);
}
-#ifndef CONFIG_ALTERA_SPI_IDLE_VAL
-# define CONFIG_ALTERA_SPI_IDLE_VAL 0xff
-#endif
-
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)
{
struct altera_spi_slave *altspi = to_altera_spi_slave(slave);
/* assume spi core configured to do 8 bit transfers */
- uint bytes = bitlen / 8;
- const uchar *txp = dout;
- uchar *rxp = din;
+ unsigned int bytes = bitlen / 8;
+ const unsigned char *txp = dout;
+ unsigned char *rxp = din;
+ uint32_t reg, data, start;
debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
- slave->bus, slave->cs, bitlen, bytes, flags);
+ slave->bus, slave->cs, bitlen, bytes, flags);
+
if (bitlen == 0)
goto done;
}
/* empty read buffer */
- if (readl(altspi->base + ALTERA_SPI_STATUS) &
- ALTERA_SPI_STATUS_RRDY_MSK)
- readl(altspi->base + ALTERA_SPI_RXDATA);
+ if (readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK)
+ readl(&altspi->regs->rxdata);
+
if (flags & SPI_XFER_BEGIN)
spi_cs_activate(slave);
while (bytes--) {
- uchar d = txp ? *txp++ : CONFIG_ALTERA_SPI_IDLE_VAL;
- debug("%s: tx:%x ", __func__, d);
- writel(d, altspi->base + ALTERA_SPI_TXDATA);
- while (!(readl(altspi->base + ALTERA_SPI_STATUS) &
- ALTERA_SPI_STATUS_RRDY_MSK))
- ;
- d = readl(altspi->base + ALTERA_SPI_RXDATA);
+ if (txp)
+ data = *txp++;
+ else
+ data = CONFIG_ALTERA_SPI_IDLE_VAL;
+
+ debug("%s: tx:%x ", __func__, data);
+ writel(data, &altspi->regs->txdata);
+
+ start = get_timer(0);
+ while (1) {
+ reg = readl(&altspi->regs->status);
+ if (reg & ALTERA_SPI_STATUS_RRDY_MSK)
+ break;
+ if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
+ printf("%s: Transmission timed out!\n", __func__);
+ goto done;
+ }
+ }
+
+ data = readl(&altspi->regs->rxdata);
if (rxp)
- *rxp++ = d;
- debug("rx:%x\n", d);
+ *rxp++ = data & 0xff;
+
+ debug("rx:%x\n", data);
}
- done:
+
+done:
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
#endif
int gpio;
int ss_pol;
+ unsigned int max_hz;
+ unsigned int mode;
};
static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
}
#ifdef MXC_CSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
unsigned int ctrl_reg;
u32 clk_src;
u32 div;
+ unsigned int max_hz = mxcs->max_hz;
+ unsigned int mode = mxcs->mode;
clk_src = mxc_get_clock(MXC_CSPI_CLK);
#endif
#ifdef MXC_ECSPI
-static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
s32 reg_ctrl, reg_config;
u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
u32 pre_div = 0, post_div = 0;
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
-
- if (max_hz == 0) {
- printf("Error: desired clock is 0\n");
- return -1;
- }
+ unsigned int max_hz = mxcs->max_hz;
+ unsigned int mode = mxcs->mode;
/*
* Reset SPI and set all CSs to master mode, if toggling
reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
MXC_CSPICTRL_POSTDIV(post_div);
- /* We need to disable SPI before changing registers */
- reg_ctrl &= ~MXC_CSPICTRL_EN;
-
if (mode & SPI_CS_HIGH)
ss_pol = 1;
if (bus >= ARRAY_SIZE(spi_bases))
return NULL;
+ if (max_hz == 0) {
+ printf("Error: desired clock is 0\n");
+ return NULL;
+ }
+
mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
if (!mxcs) {
puts("mxc_spi: SPI Slave not allocated !\n");
}
mxcs->base = spi_bases[bus];
+ mxcs->max_hz = max_hz;
+ mxcs->mode = mode;
- ret = spi_cfg_mxc(mxcs, cs, max_hz, mode);
- if (ret) {
- printf("mxc_spi: cannot setup SPI controller\n");
- free(mxcs);
- return NULL;
- }
return &mxcs->slave;
}
int spi_claim_bus(struct spi_slave *slave)
{
+ int ret;
struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
reg_write(®s->rxdata, 1);
udelay(1);
- reg_write(®s->ctrl, mxcs->ctrl_reg);
+ ret = spi_cfg_mxc(mxcs, slave->cs);
+ if (ret) {
+ printf("mxc_spi: cannot setup SPI controller\n");
+ return ret;
+ }
reg_write(®s->period, MXC_CSPIPERIOD_32KHZ);
reg_write(®s->intr, 0);
+config USB_ARCH_HAS_HCD
+ def_bool y
+
+config USB
+ bool "Support for Host-side USB"
+ depends on USB_ARCH_HAS_HCD
+ ---help---
+ Universal Serial Bus (USB) is a specification for a serial bus
+ subsystem which offers higher speeds and more features than the
+ traditional PC serial port. The bus supplies power to peripherals
+ and allows for hot swapping. Up to 127 USB peripherals can be
+ connected to a single USB host in a tree structure.
+
+ The USB host is the root of the tree, the peripherals are the
+ leaves and the inner nodes are special USB devices called hubs.
+ Most PCs now have USB host ports, used to connect peripherals
+ such as scanners, keyboards, mice, modems, cameras, disks,
+ flash memory, network links, and printers to the PC.
+
+ Say Y here if your computer has a host-side USB port and you want
+ to use USB devices. You then need to say Y to at least one of the
+ Host Controller Driver (HCD) options below. Choose a USB 1.1
+ controller, such as "UHCI HCD support" or "OHCI HCD support",
+ and "EHCI HCD (USB 2.0) support" except for older systems that
+ do not have USB 2.0 support. It doesn't normally hurt to select
+ them all if you are not certain.
+
+ If your system has a device-side USB port, used in the peripheral
+ side of the USB protocol, see the "USB Gadget" framework instead.
+
+ After choosing your HCD, then select drivers for the USB peripherals
+ you'll be using. You may want to check out the information provided
+ in <file:Documentation/usb/> and especially the links given in
+ <file:Documentation/usb/usb-help.txt>.
+
+if USB
+
+source "drivers/usb/host/Kconfig"
+
+config USB_STORAGE
+ bool "USB Mass Storage support"
+ ---help---
+ Say Y here if you want to connect USB mass storage devices to your
+ board's USB port.
+
+endif
# new USB host ethernet layer dependencies
obj-$(CONFIG_USB_HOST_ETHER) += usb_ether.o
-ifdef CONFIG_USB_ETHER_ASIX
-obj-y += asix.o
-endif
+obj-$(CONFIG_USB_ETHER_ASIX) += asix.o
obj-$(CONFIG_USB_ETHER_MCS7830) += mcs7830.o
obj-$(CONFIG_USB_ETHER_SMSC95XX) += smsc95xx.o
ifdef CONFIG_USB_GADGET
obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
+obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
obj-$(CONFIG_CI_UDC) += ci_udc.o
obj-$(CONFIG_THOR_FUNCTION) += f_thor.o
#include <asm/io.h>
#include <asm/mach-types.h>
-#include <asm/arch/gpio.h>
#include "regs-otg.h"
#include <usb/lin_gadget_compat.h>
struct usb_gadget_driver *driver);
static int udc_enable(struct s3c_udc *dev);
static void udc_set_address(struct s3c_udc *dev, unsigned char address);
-static void reconfig_usbd(void);
+static void reconfig_usbd(struct s3c_udc *dev);
static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
static void nuke(struct s3c_ep *ep, int status);
static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
void __iomem *regs_otg;
struct s3c_usbotg_reg *reg;
-struct s3c_usbotg_phy *phy;
-static unsigned int usb_phy_ctrl;
bool dfu_usb_get_reset(void)
{
return !!(readl(®->gintsts) & INT_RESET);
}
-void otg_phy_init(struct s3c_udc *dev)
-{
- dev->pdata->phy_control(1);
-
- /*USB PHY0 Enable */
- printf("USB PHY0 Enable\n");
-
- /* Enable PHY */
- writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
-
- if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
- writel((readl(&phy->phypwr)
- &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
- &~FORCE_SUSPEND_0), &phy->phypwr);
- else /* C110 GONI */
- writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
- &~FORCE_SUSPEND_0), &phy->phypwr);
-
- if (s5p_cpu_id == 0x4412)
- writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
- EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
- &phy->phyclk); /* PLL 24Mhz */
- else
- writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
- CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
-
- writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
- | PHY_SW_RST0, &phy->rstcon);
- udelay(10);
- writel(readl(&phy->rstcon)
- &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
- udelay(10);
-}
-
-void otg_phy_off(struct s3c_udc *dev)
-{
- /* reset controller just in case */
- writel(PHY_SW_RST0, &phy->rstcon);
- udelay(20);
- writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
- udelay(20);
-
- writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
- | FORCE_SUSPEND_0, &phy->phypwr);
-
- writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
-
- writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
- &phy->phyclk);
-
- udelay(10000);
-
- dev->pdata->phy_control(0);
-}
+__weak void otg_phy_init(struct s3c_udc *dev) {}
+__weak void otg_phy_off(struct s3c_udc *dev) {}
/***********************************************************/
debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
otg_phy_init(dev);
- reconfig_usbd();
+ reconfig_usbd(dev);
debug_cond(DEBUG_SETUP != 0,
"S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
udc_reinit(dev);
}
-static void reconfig_usbd(void)
+static void reconfig_usbd(struct s3c_udc *dev)
{
/* 2. Soft-reset OTG Core and then unreset again. */
int i;
unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl);
+ uint32_t dflt_gusbcfg;
debug("Reseting OTG controller\n");
- writel(0<<15 /* PHY Low Power Clock sel*/
+ dflt_gusbcfg =
+ 0<<15 /* PHY Low Power Clock sel*/
|1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
|0x5<<10 /* Turnaround time*/
|0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
|0<<6 /* 0: high speed utmi+, 1: full speed serial*/
|0<<4 /* 0: utmi+, 1:ulpi*/
|1<<3 /* phy i/f 0:8bit, 1:16bit*/
- |0x7<<0, /* HS/FS Timeout**/
- ®->gusbcfg);
+ |0x7<<0; /* HS/FS Timeout**/
+
+ if (dev->pdata->usb_gusbcfg)
+ dflt_gusbcfg = dev->pdata->usb_gusbcfg;
+
+ writel(dflt_gusbcfg, ®->gusbcfg);
/* 3. Put the OTG device core in the disconnected state.*/
uTemp = readl(®->dctl);
dev->pdata = pdata;
- phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
- usb_phy_ctrl = pdata->usb_phy_ctrl;
/* regs_otg = (void *)pdata->regs_otg; */
--- /dev/null
+/*
+ * drivers/usb/gadget/s3c_udc_otg.c
+ * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
+ *
+ * Copyright (C) 2008 for Samsung Electronics
+ *
+ * BSP Support for Samsung's UDC driver
+ * available at:
+ * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
+ *
+ * State machine bugfixes:
+ * Marek Szyprowski <m.szyprowski@samsung.com>
+ *
+ * Ported to u-boot:
+ * Marek Szyprowski <m.szyprowski@samsung.com>
+ * Lukasz Majewski <l.majewski@samsumg.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <linux/list.h>
+#include <malloc.h>
+
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <asm/io.h>
+
+#include <asm/mach-types.h>
+
+#include "regs-otg.h"
+#include <usb/lin_gadget_compat.h>
+
+#include <usb/s3c_udc.h>
+
+void otg_phy_init(struct s3c_udc *dev)
+{
+ unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
+ struct s3c_usbotg_phy *phy =
+ (struct s3c_usbotg_phy *)dev->pdata->regs_phy;
+
+ dev->pdata->phy_control(1);
+
+ /* USB PHY0 Enable */
+ printf("USB PHY0 Enable\n");
+
+ /* Enable PHY */
+ writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
+
+ if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
+ writel((readl(&phy->phypwr)
+ &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
+ &~FORCE_SUSPEND_0), &phy->phypwr);
+ else /* C110 GONI */
+ writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
+ &~FORCE_SUSPEND_0), &phy->phypwr);
+
+ if (s5p_cpu_id == 0x4412)
+ writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
+ EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
+ &phy->phyclk); /* PLL 24Mhz */
+ else
+ writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
+ CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
+
+ writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
+ | PHY_SW_RST0, &phy->rstcon);
+ udelay(10);
+ writel(readl(&phy->rstcon)
+ &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
+ udelay(10);
+}
+
+void otg_phy_off(struct s3c_udc *dev)
+{
+ unsigned int usb_phy_ctrl = dev->pdata->usb_phy_ctrl;
+ struct s3c_usbotg_phy *phy =
+ (struct s3c_usbotg_phy *)dev->pdata->regs_phy;
+
+ /* reset controller just in case */
+ writel(PHY_SW_RST0, &phy->rstcon);
+ udelay(20);
+ writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
+ udelay(20);
+
+ writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
+ | FORCE_SUSPEND_0, &phy->phypwr);
+
+ writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
+
+ writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
+ &phy->phyclk);
+
+ udelay(10000);
+
+ dev->pdata->phy_control(0);
+}
debug_cond(DEBUG_ISR,
"\t\tOTG core got reset (%d)!!\n",
reset_available);
- reconfig_usbd();
+ reconfig_usbd(dev);
dev->ep0state = WAIT_FOR_SETUP;
reset_available = 0;
s3c_udc_pre_setup();
--- /dev/null
+#
+# USB Host Controller Drivers
+#
+comment "USB Host Controller Drivers"
+
+config USB_XHCI_HCD
+ bool "xHCI HCD (USB 3.0) support"
+ ---help---
+ The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
+ "SuperSpeed" host controller hardware.
+
+config USB_XHCI
+ bool
+ default USB_XHCI_HCD
+ ---help---
+ TODO: rename after most boards switch to Kconfig
+
+if USB_XHCI_HCD
+
+endif
+
+config USB_EHCI_HCD
+ bool "EHCI HCD (USB 2.0) support"
+ ---help---
+ The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
+ "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
+ If your USB host controller supports USB 2.0, you will likely want to
+ configure this Host Controller Driver.
+
+ EHCI controllers are packaged with "companion" host controllers (OHCI
+ or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports
+ will connect to EHCI if the device is high speed, otherwise they
+ connect to a companion controller. If you configure EHCI, you should
+ probably configure the OHCI (for NEC and some other vendors) USB Host
+ Controller Driver or UHCI (for Via motherboards) Host Controller
+ Driver too.
+
+ You may want to read <file:Documentation/usb/ehci.txt>.
+
+config USB_EHCI
+ bool
+ default USB_EHCI_HCD
+ ---help---
+ TODO: rename after most boards switch to Kconfig
+
+if USB_EHCI_HCD
+
+config USB_EHCI_UNIPHIER
+ bool "Support for Panasonic UniPhier on-chip EHCI USB controller"
+ depends on ARCH_UNIPHIER
+ default y
+ ---help---
+ Enables support for the on-chip EHCI controller on Panasonic
+ UniPhier SoCs.
+
+endif
obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
+obj-$(CONFIG_USB_EHCI_UNIPHIER) += ehci-uniphier.o
obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o
obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
}
struct int_queue {
+ int elementsize;
struct QH *first;
struct QH *current;
struct QH *last;
struct int_queue *result = NULL;
int i;
+ /*
+ * Interrupt transfers requiring several transactions are not supported
+ * because bInterval is ignored.
+ *
+ * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
+ * <= PKT_ALIGN if several qTDs are required, while the USB
+ * specification does not constrain this for interrupt transfers. That
+ * means that ehci_submit_async() would support interrupt transfers
+ * requiring several transactions only as long as the transfer size does
+ * not require more than a single qTD.
+ */
+ if (elementsize > usb_maxpacket(dev, pipe)) {
+ printf("%s: xfers requiring several transactions are not supported.\n",
+ __func__);
+ return NULL;
+ }
+
debug("Enter create_int_queue\n");
if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
debug("ehci intr queue: out of memory\n");
goto fail1;
}
+ result->elementsize = elementsize;
result->first = memalign(USB_DMA_MINALIGN,
sizeof(struct QH) * queuesize);
if (!result->first) {
ALIGN_END_ADDR(struct qTD, result->tds,
queuesize));
- if (disable_periodic(ctrl) < 0) {
- debug("FATAL: periodic should never fail, but did");
- goto fail3;
+ if (ctrl->periodic_schedules > 0) {
+ if (disable_periodic(ctrl) < 0) {
+ debug("FATAL: periodic should never fail, but did");
+ goto fail3;
+ }
}
/* hook up to periodic list */
queue->current++;
else
queue->current = NULL;
+
+ invalidate_dcache_range((uint32_t)cur->buffer,
+ ALIGN_END_ADDR(char, cur->buffer,
+ queue->elementsize));
+
debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n",
hc32_to_cpu(cur_td->qt_token), cur, queue->first);
return cur->buffer;
}
/* Do not free buffers associated with QHs, they're owned by someone else */
-static int
+int
destroy_int_queue(struct usb_device *dev, struct int_queue *queue)
{
struct ehci_ctrl *ctrl = dev->controller;
debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
dev, pipe, buffer, length, interval);
- /*
- * Interrupt transfers requiring several transactions are not supported
- * because bInterval is ignored.
- *
- * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2
- * <= PKT_ALIGN if several qTDs are required, while the USB
- * specification does not constrain this for interrupt transfers. That
- * means that ehci_submit_async() would support interrupt transfers
- * requiring several transactions only as long as the transfer size does
- * not require more than a single qTD.
- */
- if (length > usb_maxpacket(dev, pipe)) {
- printf("%s: Interrupt transfers requiring several "
- "transactions are not supported.\n", __func__);
- return -1;
- }
-
queue = create_int_queue(dev, pipe, 1, length, buffer);
+ if (!queue)
+ return -1;
timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
while ((backbuffer = poll_int_queue(dev, queue)) == NULL)
return -EINVAL;
}
- invalidate_dcache_range((uint32_t)buffer,
- ALIGN_END_ADDR(char, buffer, length));
-
ret = destroy_int_queue(dev, queue);
if (ret < 0)
return ret;
#include "ehci.h"
#if defined(CONFIG_R8A7740)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+static u32 usb_base_address[] = {
0xC6700000
};
#elif defined(CONFIG_R8A7790)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+static u32 usb_base_address[] = {
0xEE080000, /* USB0 (EHCI) */
0xEE0A0000, /* USB1 */
0xEE0C0000, /* USB2 */
};
-#elif defined(CONFIG_R8A7791)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
- 0xEE080000, /* USB0 (EHCI) */
- 0xEE0C0000, /* USB1 */
-};
-#elif defined(CONFIG_R8A7794)
-static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = {
+#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
+ defined(CONFIG_R8A7794)
+static u32 usb_base_address[] = {
0xEE080000, /* USB0 (EHCI) */
0xEE0C0000, /* USB1 */
};
if (!i)
printf("error : ehci(%d) reset failed.\n", index);
- if (index == (CONFIG_USB_MAX_CONTROLLER_COUNT - 1))
+ if (index == (ARRAY_SIZE(usb_base_address) - 1))
setbits_le32(SMSTPCR7, SMSTPCR703);
return 0;
*/
#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <common.h>
#include "ehci.h"
-#define SUNXI_USB1_IO_BASE 0x01c14000
-#define SUNXI_USB2_IO_BASE 0x01c1c000
-
#define SUNXI_USB_PMU_IRQ_ENABLE 0x800
-#define SUNXI_USB_CSR 0x01c13404
+#define SUNXI_USB_CSR 0x404
#define SUNXI_USB_PASSBY_EN 1
#define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
int usb_rst_mask;
int ahb_clk_mask;
int gpio_vbus;
- void *csr;
int irq;
int id;
} sunxi_echi_hcd[] = {
{
- .usb_rst_mask = CCM_USB_CTRL_PHY1_RST,
+ .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0,
- .gpio_vbus = CONFIG_SUNXI_USB_VBUS0_GPIO,
- .csr = (void *)SUNXI_USB_CSR,
+#ifndef CONFIG_MACH_SUN6I
.irq = 39,
+#else
+ .irq = 72,
+#endif
.id = 1,
},
#if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1)
{
- .usb_rst_mask = CCM_USB_CTRL_PHY2_RST,
+ .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
.ahb_clk_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1,
- .gpio_vbus = CONFIG_SUNXI_USB_VBUS1_GPIO,
- .csr = (void *)SUNXI_USB_CSR,
+#ifndef CONFIG_MACH_SUN6I
.irq = 40,
+#else
+ .irq = 74,
+#endif
.id = 2,
}
#endif
static void *get_io_base(int hcd_id)
{
- if (hcd_id == 1)
- return (void *)SUNXI_USB1_IO_BASE;
- else if (hcd_id == 2)
- return (void *)SUNXI_USB2_IO_BASE;
- else
+ switch (hcd_id) {
+ case 0:
+ return (void *)SUNXI_USB0_BASE;
+ case 1:
+ return (void *)SUNXI_USB1_BASE;
+ case 2:
+ return (void *)SUNXI_USB2_BASE;
+ default:
return NULL;
+ }
+}
+
+static int get_vbus_gpio(int hcd_id)
+{
+ switch (hcd_id) {
+ case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
+ case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
+ }
+ return -1;
}
static void usb_phy_write(struct sunxi_ehci_hcd *sunxi_ehci, int addr,
int data, int len)
{
int j = 0, usbc_bit = 0;
- void *dest = sunxi_ehci->csr;
+ void *dest = get_io_base(0) + SUNXI_USB_CSR;
usbc_bit = 1 << (sunxi_ehci->id * 2);
for (j = 0; j < len; j++) {
usb_phy_write(sunxi_ehci, 0x20, 0x14, 5);
/* threshold adjustment disconnect */
-#ifdef CONFIG_SUN4I
+#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN6I
usb_phy_write(sunxi_ehci, 0x2a, 3, 2);
#else
usb_phy_write(sunxi_ehci, 0x2a, 2, 2);
setbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
setbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
+#ifdef CONFIG_MACH_SUN6I
+ setbits_le32(&ccm->ahb_reset0_cfg, sunxi_ehci->ahb_clk_mask);
+#endif
sunxi_usb_phy_init(sunxi_ehci);
sunxi_usb_passby(sunxi_ehci, SUNXI_USB_PASSBY_EN);
- gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
+ if (sunxi_ehci->gpio_vbus != -1)
+ gpio_direction_output(sunxi_ehci->gpio_vbus, 1);
}
static void sunxi_ehci_disable(struct sunxi_ehci_hcd *sunxi_ehci)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
+ if (sunxi_ehci->gpio_vbus != -1)
+ gpio_direction_output(sunxi_ehci->gpio_vbus, 0);
sunxi_usb_passby(sunxi_ehci, !SUNXI_USB_PASSBY_EN);
+#ifdef CONFIG_MACH_SUN6I
+ clrbits_le32(&ccm->ahb_reset0_cfg, sunxi_ehci->ahb_clk_mask);
+#endif
clrbits_le32(&ccm->ahb_gate0, sunxi_ehci->ahb_clk_mask);
clrbits_le32(&ccm->usb_clk_cfg, sunxi_ehci->usb_rst_mask);
}
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
+ int err;
+
+ sunxi_ehci->gpio_vbus = get_vbus_gpio(sunxi_ehci->id);
/* enable common PHY only once */
if (index == 0)
setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
+ if (sunxi_ehci->gpio_vbus != -1) {
+ err = gpio_request(sunxi_ehci->gpio_vbus, "ehci_vbus");
+ if (err)
+ return err;
+ }
+
sunxi_ehci_enable(sunxi_ehci);
*hccr = get_io_base(sunxi_ehci->id);
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_ehci_hcd *sunxi_ehci = &sunxi_echi_hcd[index];
+ int err;
sunxi_ehci_disable(sunxi_ehci);
+ if (sunxi_ehci->gpio_vbus != -1) {
+ err = gpio_free(sunxi_ehci->gpio_vbus);
+ if (err)
+ return err;
+ }
+
/* disable common PHY only once, for the last enabled hcd */
if (enabled_hcd_count == 1)
clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
--- /dev/null
+/*
+ * Copyright (C) 2014 Panasonic Corporation
+ * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <usb.h>
+#include <asm/arch/ehci-uniphier.h>
+#include "ehci.h"
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
+ struct ehci_hcor **hcor)
+{
+ struct ehci_hccr *cr;
+ struct ehci_hcor *or;
+
+ uniphier_ehci_reset(index, 0);
+
+ cr = (struct ehci_hccr *)(uniphier_ehci_platdata[index].base);
+ or = (void *)cr + HC_LENGTH(ehci_readl(&cr->cr_capbase));
+
+ *hccr = cr;
+ *hcor = or;
+
+ return 0;
+}
+
+int ehci_hcd_stop(int index)
+{
+ uniphier_ehci_reset(index, 1);
+
+ return 0;
+}
uint32_t or_usbcmd;
#define CMD_PARK (1 << 11) /* enable "park" */
#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
-#define CMD_ASE (1 << 5) /* async schedule enable */
#define CMD_LRESET (1 << 7) /* partial reset */
-#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */
+#define CMD_IAAD (1 << 6) /* "doorbell" interrupt */
+#define CMD_ASE (1 << 5) /* async schedule enable */
#define CMD_PSE (1 << 4) /* periodic schedule enable */
#define CMD_RESET (1 << 1) /* reset HC not bus */
#define CMD_RUN (1 << 0) /* start/stop HC */
uint64_t crc = salt;
if (table[128] == 0) {
- uint64_t *ct;
+ uint64_t *ct = NULL;
int i, j;
for (i = 0; i < 256; i++) {
for (ct = table + i, *ct = i, j = 8; j > 0; j--)
}
printf("unknown ZAP type\n");
+ free(zapbuf);
return ZFS_ERR_BAD_FS;
}
return ret;
}
printf("unknown ZAP type\n");
+ free(zapbuf);
return 0;
}
ubbest = malloc(sizeof(*ubbest));
if (!ubbest) {
+ free(ub_array);
zfs_unmount(data);
return 0;
}
if (err) {
printf("couldn't zio_read object directory\n");
zfs_unmount(data);
+ free(osp);
free(ubbest);
return 0;
}
hdrsize = SA_HDR_SIZE(((sa_hdr_phys_t *) sahdrp));
file->size = *(uint64_t *) ((char *) sahdrp + hdrsize + SA_SIZE_OFFSET);
+ if ((data->dnode.dn.dn_bonuslen == 0) &&
+ (data->dnode.dn.dn_flags & DNODE_FLAG_SPILL_BLKPTR))
+ free(sahdrp);
} else {
file->size = zfs_to_cpu64(((znode_phys_t *) DN_BONUS(&data->dnode.dn))->zp_size, data->dnode.endian);
}
--- /dev/null
+/*
+ * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
+ *
+ * X-Powers AXP221 Power Management IC driver
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define AXP221_CHIP_ADDR 0x68
+#define AXP221_CTRL_ADDR 0x3e
+#define AXP221_INIT_DATA 0x3e
+
+#define AXP221_CHIP_ID 0x03
+#define AXP221_OUTPUT_CTRL1 0x10
+#define AXP221_OUTPUT_CTRL1_ALDO1_EN (1 << 6)
+#define AXP221_OUTPUT_CTRL1_ALDO2_EN (1 << 7)
+#define AXP221_OUTPUT_CTRL2 0x12
+#define AXP221_OUTPUT_CTRL2_DLDO1_EN (1 << 3)
+#define AXP221_OUTPUT_CTRL2_DLDO2_EN (1 << 4)
+#define AXP221_OUTPUT_CTRL2_DLDO3_EN (1 << 5)
+#define AXP221_OUTPUT_CTRL2_DLDO4_EN (1 << 6)
+#define AXP221_OUTPUT_CTRL2_DCDC1_EN (1 << 7)
+#define AXP221_OUTPUT_CTRL3 0x13
+#define AXP221_OUTPUT_CTRL3_ALDO3_EN (1 << 7)
+#define AXP221_DLDO1_CTRL 0x15
+#define AXP221_DLDO2_CTRL 0x16
+#define AXP221_DLDO3_CTRL 0x17
+#define AXP221_DLDO4_CTRL 0x18
+#define AXP221_DCDC1_CTRL 0x21
+#define AXP221_DCDC2_CTRL 0x22
+#define AXP221_DCDC3_CTRL 0x23
+#define AXP221_DCDC4_CTRL 0x24
+#define AXP221_DCDC5_CTRL 0x25
+#define AXP221_ALDO1_CTRL 0x28
+#define AXP221_ALDO2_CTRL 0x28
+#define AXP221_ALDO3_CTRL 0x2a
+
+int axp221_set_dcdc1(unsigned int mvolt);
+int axp221_set_dcdc2(unsigned int mvolt);
+int axp221_set_dcdc3(unsigned int mvolt);
+int axp221_set_dcdc4(unsigned int mvolt);
+int axp221_set_dcdc5(unsigned int mvolt);
+int axp221_set_dldo1(unsigned int mvolt);
+int axp221_set_dldo2(unsigned int mvolt);
+int axp221_set_dldo3(unsigned int mvolt);
+int axp221_set_dldo4(unsigned int mvolt);
+int axp221_set_aldo1(unsigned int mvolt);
+int axp221_set_aldo2(unsigned int mvolt);
+int axp221_set_aldo3(unsigned int mvolt);
+int axp221_init(void);
/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2004-2006
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
/*
* Valid values for CONFIG_SYS_TEXT_BASE are:
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
#define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_MPC862 1
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */
/*
- * (C) Copyright 2000-2008
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
/*
- * (C) Copyright 2000-2005
+ * (C) Copyright 2000-2014
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2006
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0x40000000
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NFS
#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x70000000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#endif
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_TMU_TIMER
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
+#else
#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
+#endif
#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+/* Filesystems */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+
+/* USB */
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_RMOBILE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
#endif /* __ALT_H */
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
+#ifndef CONFIG_SPL_USBETH_SUPPORT
+/* Fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#endif
+
#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
/* USB TI's IDs */
-#define CONFIG_G_DNL_VENDOR_NUM 0x0403
-#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
+#define CONFIG_G_DNL_VENDOR_NUM 0x0451
+#define CONFIG_G_DNL_PRODUCT_NUM 0xD022
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#endif /* CONFIG_MUSB_GADGET */
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_MXC_SPI
#define CONFIG_SF_DEFAULT_BUS 3
-#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(3, 20)<<8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
# define CONFIG_CMD_FAT
# define CONFIG_CMD_MMC
# define CONFIG_DOS_PARTITION
+# define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
# endif
# ifdef CONFIG_MMC_SPI
# define CONFIG_CMD_MMC_SPI
--- /dev/null
+/*
+ * (C) Copyright 2013 CompuLab, Ltd.
+ * Author: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * Configuration settings for the CompuLab CM-T3517 board
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP /* in a TI OMAP core */
+#define CONFIG_CM_T3517 /* working with CM-T3517 */
+#define CONFIG_OMAP_COMMON
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+
+/*
+ * This is needed for the DMA stuff.
+ * Although the default iss 64, we still define it
+ * to be on the safe side once the default is changed.
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT
+/*
+ * The early kernel mapping on ARM currently only maps from the base of DRAM
+ * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
+ * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
+ * so that leaves DRAM base to DRAM base + 0x4000 available.
+ */
+#define CONFIG_SYS_BOOTMAPSZ 0x4000
+
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SERIAL_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+
+#define CONFIG_OMAP_GPIO
+
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_DOS_PARTITION
+
+/* USB */
+#define CONFIG_USB_MUSB_AM35X
+
+#ifndef CONFIG_USB_MUSB_AM35X
+#define CONFIG_USB_OMAP3
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147
+#else /* !CONFIG_USB_MUSB_AM35X */
+#define CONFIG_MUSB_HOST
+#define CONFIG_MUSB_PIO_ONLY
+#endif /* CONFIG_USB_MUSB_AM35X */
+
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
+ "1920k(u-boot),256k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_NAND /* NAND support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_GPIO
+
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
+#undef CONFIG_CMD_IMLS /* List all found images */
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_OMAP24_I2C_SPEED 400000
+#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
+#define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_I2C_EEPROM_BUS 0
+#define CONFIG_I2C_MULTI_BUS
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_QUIET_TEST
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
+ /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
+ /* to access nand at */
+ /* CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
+ /* devices */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "baudrate=115200\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=auto\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768MR-16@60\0" \
+ "defaultdisplay=dvi\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+ "mmcrootfstype=ext4\0" \
+ "nandroot=/dev/mtdblock4 rw\0" \
+ "nandrootfstype=ubifs\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source ${loadaddr}\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "nandboot=echo Booting from nand ...; " \
+ "run nandargs; " \
+ "nand read ${loadaddr} 2a0000 400000; " \
+ "bootm ${loadaddr}\0" \
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run nandboot; " \
+ "fi; " \
+ "fi; " \
+ "else run nandboot; fi"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD "no"
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT "CM-T3517 # "
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define CONFIG_SYS_CS0_SIZE (256 << 20)
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
+
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20))
+#endif /* CONFIG_CMD_NET */
+
+/* additions for new relocation code, must be added to all boards */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+/* Status LED */
+#define CONFIG_STATUS_LED /* Status LED enabled */
+#define CONFIG_BOARD_SPECIFIC_LED
+#define CONFIG_GPIO_LED
+#define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */
+#define GREEN_LED_DEV 0
+#define STATUS_LED_BIT GREEN_LED_GPIO
+#define STATUS_LED_STATE STATUS_LED_ON
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT GREEN_LED_DEV
+
+/* GPIO banks */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */
+#endif
+
+/* Display Configuration */
+#define CONFIG_OMAP3_GPIO_2
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_VIDEO_OMAP3
+#define LCD_BPP LCD_COLOR16
+
+#define CONFIG_LCD
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASHIMAGE_GUARD
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
+#define CONFIG_SCF0403_LCD
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
#define CONFIG_PHYSMEM
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DM
#define CONFIG_CMD_DM
#define CONFIG_FIT
#undef CONFIG_ZLIB
#undef CONFIG_GZIP
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
/*-----------------------------------------------------------------------
* Watchdog Configuration
#define CONFIG_SYS_MEMTEST_START 0x00100000
#define CONFIG_SYS_MEMTEST_END 0x01000000
-#define CONFIG_SYS_LOAD_ADDR 0x02000000
+#define CONFIG_SYS_LOAD_ADDR 0x20000000
/*-----------------------------------------------------------------------
* SDRAM Configuration
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
#define CONFIG_SPL_TEXT_BASE 0x00908000
-#define CONFIG_SPL_MAX_SIZE (64 * 1024)
+#define CONFIG_SPL_MAX_SIZE 0x10000
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7"
#define CONFIG_SPL_STACK 0x0091FFB8
#define CONFIG_SPL_LIBCOMMON_SUPPORT
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "K2E EVM # "
-#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
- "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
-
-#define KS2_FDT_NAME "name_fdt=k2e-evm.dtb\0"
-#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
-#define KS2_NAME_MON "name_mon=skern-k2e-evm.bin\0"
-#define NAME_UBOOT "name_uboot=u-boot-spi-k2e-evm.gph\0"
-#define NAME_UBI "name_ubi=k2e-evm-ubifs.ubi\0"
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ "addr_mon=0x0c140000\0" \
+ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \
+ "name_fdt=uImage-k2e-evm.dtb\0" \
+ "name_mon=skern-k2e-evm.bin\0" \
+ "name_ubi=k2e-evm-ubifs.ubi\0" \
+ "name_uboot=u-boot-spi-k2e-evm.gph\0" \
+ "name_fs=arago-console-image-k2e-evm.cpio.gz\0"
#include <configs/ks2_evm.h>
#define CONFIG_SYS_NAND_PAGE_2K
/* Network */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
-#define CONFIG_TI_KSNAV
-#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNET_NETCP_V1_5
#define CONFIG_KSNET_CPSW_NUM_PORTS 9
#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
-/* SerDes */
-#define CONFIG_TI_KEYSTONE_SERDES
-
#endif /* __CONFIG_K2E_EVM_H */
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "K2HK EVM # "
-#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
- "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0"
-
-#define KS2_FDT_NAME "name_fdt=k2hk-evm.dtb\0"
-#define KS2_ADDR_MON "addr_mon=0x0c5f0000\0"
-#define KS2_NAME_MON "name_mon=skern-k2hk-evm.bin\0"
-#define NAME_UBOOT "name_uboot=u-boot-spi-k2hk-evm.gph\0"
-#define NAME_UBI "name_ubi=k2hk-evm-ubifs.ubi\0"
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ "addr_mon=0x0c5f0000\0" \
+ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \
+ "name_fdt=uImage-k2hk-evm.dtb\0" \
+ "name_mon=skern-k2hk-evm.bin\0" \
+ "name_ubi=k2hk-evm-ubifs.ubi\0" \
+ "name_uboot=u-boot-spi-k2hk-evm.gph\0" \
+ "name_fs=arago-console-image-k2hk-evm.cpio.gz\0"
#include <configs/ks2_evm.h>
#define CONFIG_SYS_NAND_PAGE_2K
/* Network */
-#define CONFIG_DRIVER_TI_KEYSTONE_NET
-#define CONFIG_TI_KSNAV
-#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNET_NETCP_V1_0
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
-/* SerDes */
-#define CONFIG_TI_KEYSTONE_SERDES
-
#endif /* __CONFIG_K2HK_EVM_H */
/* U-Boot general configuration */
#define CONFIG_SYS_PROMPT "K2L EVM # "
-#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\
- "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0"
-
-#define KS2_FDT_NAME "name_fdt=k2l-evm.dtb\0"
-#define KS2_ADDR_MON "addr_mon=0x0c140000\0"
-#define KS2_NAME_MON "name_mon=skern-k2l-evm.bin\0"
-#define NAME_UBOOT "name_uboot=u-boot-spi-k2l-evm.gph\0"
-#define NAME_UBI "name_ubi=k2l-evm-ubifs.ubi\0"
+#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ "addr_mon=0x0c140000\0" \
+ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \
+ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" \
+ "name_fdt=uImage-k2l-evm.dtb\0" \
+ "name_mon=skern-k2l-evm.bin\0" \
+ "name_ubi=k2l-evm-ubifs.ubi\0" \
+ "name_uboot=u-boot-spi-k2l-evm.gph\0" \
+ "name_fs=arago-console-image-k2l-evm.cpio.gz\0"
#include <configs/ks2_evm.h>
/* NAND Configuration */
#define CONFIG_SYS_NAND_PAGE_4K
+/* Network */
+#define CONFIG_KSNET_NETCP_V1_5
+#define CONFIG_KSNET_CPSW_NUM_PORTS 5
+#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
+
#endif /* __CONFIG_K2L_EVM_H */
#ifndef _CONFIG_KM_ARM_H
#define _CONFIG_KM_ARM_H
+#define CONFIG_SYS_GENERIC_BOARD
+
/* We got removed from Linux mach-types.h */
#define MACH_TYPE_KM_KIRKWOOD 2255
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x70000000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#endif
+
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_TMU_TIMER
/* STACK */
-#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffc
-#define STACK_AREA_SIZE 0xC000
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
+#endif
+
+#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
#define CONFIG_SYS_SGMII_RATESCALE 2
/* Keyston Navigator Configuration */
+#define CONFIG_TI_KSNAV
#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
/* NETCP pktdma */
+#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
/* Keystone net */
+#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
+/* SerDes */
+#define CONFIG_TI_KEYSTONE_SERDES
+
/* AEMIF */
#define CONFIG_TI_AEMIF
#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
#define CONFIG_CMD_SF
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_USB
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
/* U-Boot general configuration */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_EXTRA_ENV_SETTINGS \
- "boot=ramfs\0" \
+ CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
+ "boot=ubi\0" \
"tftp_root=/\0" \
"nfs_root=/export\0" \
"mem_lpae=1\0" \
"mem_reserve=512M\0" \
"addr_fdt=0x87000000\0" \
"addr_kern=0x88000000\0" \
- KS2_ADDR_MON \
"addr_uboot=0x87000000\0" \
"addr_fs=0x82000000\0" \
"addr_ubi=0x82000000\0" \
"addr_secdb_key=0xc000000\0" \
"fdt_high=0xffffffff\0" \
- KS2_FDT_NAME \
- "name_fs=arago-console-image.cpio.gz\0" \
- "name_kern=uImage\0" \
- KS2_NAME_MON \
- NAME_UBOOT \
- NAME_UBI \
+ "name_kern=uImage-keystone-evm.bin\0" \
"run_mon=mon_install ${addr_mon}\0" \
"run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \
"init_net=run args_all args_net\0" \
"init_ubi=run args_all args_ubi; " \
- "ubi part ubifs; ubifsmount boot;" \
+ "ubi part ubifs; ubifsmount ubi:boot;" \
"ubifsload ${addr_secdb_key} securedb.key.bin;\0" \
"get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \
"get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \
"burn_uboot_nand=nand erase 0 0x100000; " \
"nand write ${addr_uboot} 0 ${filesize}\0" \
"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \
- KS2_ARGS_UBI \
"args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
"${nfs_options} ip=dhcp\0" \
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0xB0000000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE8080000
+#endif
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_TMU_TIMER
/* STACK */
-#define CONFIG_SYS_INIT_SP_ADDR 0xE827fffc
-#define STACK_AREA_SIZE 0xC000
+#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC
+#endif
+#define STACK_AREA_SIZE 0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
#define CONFIG_EXTRA_ENV_SETTINGS \
"consdev=ttyAMA0\0" \
"baudrate=115200\0" \
+ "bootscript=boot.scr\0" \
"bootdev=/dev/mmcblk0p2\0" \
"rootdev=/dev/mmcblk0p3\0" \
"netdev=eth0\0" \
+++ /dev/null
-/*
- * (C) Copyright 2006-2008
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC5200
-#define CONFIG_MCC200 1 /* MCC200 board */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFC000000 boot low (standard configuration)
- * 0xFFF00000 boot high
- * 0x00100000 boot from RAM (for testing only)
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFC000000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
-
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/*
- * Serial console configuration
- *
- * To select console on the one of 8 external UARTs,
- * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
- * or as 5, 6, 7, or 8 for the second Quad UART.
- * COM11, COM12, COM13, COM14 are located on the second Quad UART.
- *
- * CONFIG_PSC_CONSOLE must be undefined in this case.
- */
-#if !defined(CONFIG_PRS200)
-/* MCC200 configuration: */
-#ifdef CONFIG_CONSOLE_COM12
-#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */
-#else
-#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */
-#endif
-#else
-/* PRS200 configuration: */
-#undef CONFIG_QUART_CONSOLE
-#endif /* CONFIG_PRS200 */
-/*
- * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
- * and undefine CONFIG_QUART_CONSOLE.
- */
-#if !defined(CONFIG_PRS200)
-/* MCC200 configuration: */
-#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
-#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
-#else
-/* PRS200 configuration: */
-#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
-#endif
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_MII 1
-
-#define CONFIG_DOS_PARTITION
-
-/* USB */
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-/* automatic software updates (see board/mcc200/auto_update.c) */
-#define CONFIG_AUTO_UPDATE 1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_USB
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
-
-#define CONFIG_PREBOOT "echo;" \
- "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
- "echo"
-
-#undef CONFIG_BOOTARGS
-
-#ifdef CONFIG_PRS200
-# define CONFIG_SYS__BOARDNAME "prs200"
-# define CONFIG_SYS__LINUX_CONSOLE "ttyS0"
-#else
-# define CONFIG_SYS__BOARDNAME "mcc200"
-# define CONFIG_SYS__LINUX_CONSOLE "ttyEU5"
-#endif
-
-/* Network */
-#define CONFIG_ETHADDR 00:17:17:ff:00:00
-#define CONFIG_IPADDR 10.76.9.29
-#define CONFIG_SERVERIP 10.76.9.1
-
-#include <version.h> /* For U-Boot version */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "ubootver=" U_BOOT_VERSION "\0" \
- "netdev=eth0\0" \
- "hostname=" CONFIG_SYS__BOARDNAME "\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/mtdblock2 " \
- "rootfstype=cramfs\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addcons=setenv bootargs ${bootargs} " \
- "console=${console},${baudrate} " \
- "ubootver=${ubootver} board=${board}\0" \
- "flash_nfs=run nfsargs addip addcons;" \
- "bootm ${kernel_addr}\0" \
- "flash_self=run ramargs addip addcons;" \
- "bootm ${kernel_addr} ${ramdisk_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};" \
- "run nfsargs addip addcons;bootm\0" \
- "console=" CONFIG_SYS__LINUX_CONSOLE "\0" \
- "rootpath=/opt/eldk/ppc_6xx\0" \
- "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \
- "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \
- "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
- "kernel_addr=0xFC0C0000\0" \
- "update=protect off ${text_base} +${filesize};" \
- "era ${text_base} +${filesize};" \
- "cp.b 200000 ${text_base} ${filesize}\0" \
- "unlock=yes\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "run flash_self"
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-/*
- * Flash configuration (8,16 or 32 MB)
- * TEXT base always at 0xFFF00000
- * ENV_ADDR always at 0xFFF40000
- * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
- * 0xFE000000 for 32 MB
- * 0xFF000000 for 16 MB
- * 0xFF800000 for 8 MB
- */
-#define CONFIG_SYS_FLASH_BASE 0xfc000000
-#define CONFIG_SYS_FLASH_SIZE 0x04000000
-
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
-
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
-
-#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR 0xf0000000
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
-
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT 1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * Ethernet configuration
- */
-/* #define CONFIG_MPC5xxx_FEC 1 */
-/* #define CONFIG_MPC5xxx_FEC_MII100 */
-/*
- * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
- */
-/* #define CONFIG_MPC5xxx_FEC_MII10 */
-#define CONFIG_PHY_ADDR 1
-
-/*
- * LCD Splash Screen
- */
-#if !defined(CONFIG_PRS200)
-#define CONFIG_LCD 1
-#define CONFIG_PROGRESSBAR 1
-#endif
-
-#if defined(CONFIG_LCD)
-#define CONFIG_SPLASH_SCREEN 1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
-#define LCD_BPP LCD_MONOCHROME
-#endif
-
-/*
- * GPIO configuration
- */
-/* 0x10000004 = 32MB SDRAM */
-/* 0x90000004 = 64MB SDRAM */
-#if defined(CONFIG_LCD)
-/* set PSC2 in UART mode */
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044
-#else
-#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG 0x0004fb00
-#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
-
-/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
-#define CONFIG_SYS_CS2_START 0x80000000
-#define CONFIG_SYS_CS2_SIZE 0x00001000
-#define CONFIG_SYS_CS2_CFG 0x1d300
-
-/* Second Quad UART @0x80010000 */
-#define CONFIG_SYS_CS1_START 0x80010000
-#define CONFIG_SYS_CS1_SIZE 0x00001000
-#define CONFIG_SYS_CS1_CFG 0x1d300
-
-/* Leica - build revision resistors */
-/*
-#define CONFIG_SYS_CS3_START 0x80020000
-#define CONFIG_SYS_CS3_SIZE 0x00000004
-#define CONFIG_SYS_CS3_CFG 0x1d300
-*/
-
-/*
- * Select one of quarts as a default
- * console. If undefined - PSC console
- * wil be default
- */
-#define CONFIG_SYS_CS_BURST 0x00000000
-#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
-
-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
-
-/*
- * QUART Expanders support
- */
-#if defined(CONFIG_QUART_CONSOLE)
-/*
- * We'll use NS16550 chip routines,
- */
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_NS16550_SERIAL 1
-#define CONFIG_CONS_INDEX 1
-/*
- * To achieve necessary offset on SC16C554
- * A0-A2 (register select) pins with NS16550
- * functions (in struct NS16550), REG_SIZE
- * should be 4, because A0-A2 pins are connected
- * to DA2-DA4 address bus lines.
- */
-#define CONFIG_SYS_NS16550_REG_SIZE 4
-/*
- * LocalPlus Bus already inited in cpu_init_f(),
- * so can work with QUART's chip selects.
- * One of four SC16C554 UARTs is selected with
- * A3-A4 (DA5-DA6) lines.
- */
-#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
-#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
-#else
-#error "Wrong QUART expander number."
-#endif
-
-/*
- * SC16C554 chip's external crystal oscillator frequency
- * is 7.3728 MHz
- */
-#define CONFIG_SYS_NS16550_CLK 7372800
-#endif /* CONFIG_QUART_CONSOLE */
-/*-----------------------------------------------------------------------
- * USB stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_USB_CLOCK 0x0001BBBB
-#define CONFIG_USB_CONFIG 0x00005000
-
-#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
-#define CONFIG_AUTOBOOT_STOP_STR "432"
-#define CONFIG_SILENT_CONSOLE 1
-
-#endif /* __CONFIG_H */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
- "fdt_file=imx53-qsb.dtb\0" \
"fdt_addr=0x71000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
#endif
#define CONFIG_MP
+#define CONFIG_MXC_GPT_HCLK
#endif
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
+#define CONFIG_PCA953X
+#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
+
#include "mx6sabre_common.h"
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_SPEED 100000
+/* NAND flash command */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+
+/* NAND stuff */
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
#endif /* __MX6QSABREAUTO_CONFIG_H */
#define CONFIG_ENV_IS_IN_MMC
#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_ENV_OFFSET (8 * 64 * 1024)
#endif
#define CONFIG_OF_LIBFDT
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include "imx6_spl.h"
+#endif
+
#define CONFIG_MACH_TYPE 3980
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV "ttymxc0"
#define CONFIG_ENV_OFFSET (6 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
+#endif
+
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Configuration settings for the Novena U-boot.
+ *
+ * Copyright (C) 2014 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* System configurations */
+#define CONFIG_MX6
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MISC_INIT_R
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_FIT
+#define CONFIG_KEYBOARD
+#define CONFIG_MXC_GPIO
+#define CONFIG_OF_LIBFDT
+#define CONFIG_REGEX
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_NO_FLASH
+
+#include "configs/mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <config_cmd_default.h>
+
+/* U-Boot Commands */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_FUSE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SATA
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_USB
+#define CONFIG_VIDEO
+
+/* U-Boot general configurations */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+ /* Print buffer size */
+#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+ /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+
+/* U-Boot environment */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SIZE (16 * 1024)
+/*
+ * Environment is on MMC, starting at offset 512KiB from start of the card.
+ * Please place first partition at offset 1MiB from the start of the card
+ * as recommended by GNU/fdisk. See below for details:
+ * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET (512 * 1024)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
+#define CONFIG_ENV_OFFSET_REDUND \
+ (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#else
+#define CONFIG_ENV_IS_NOWHERE
+#endif
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY 5
+#define CONFIG_BOOTFILE "fitImage"
+#define CONFIG_BOOTARGS "console=ttymxc1,115200 "
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_LOADADDR 0x18000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_HOSTNAME novena
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE 0xF0000000
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x20000000
+
+#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
+
+/* SPL */
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include "imx6_spl.h" /* common IMX6 SPL configuration */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Ethernet Configuration */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0x7
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9021
+#define CONFIG_ARP_TIMEOUT 200UL
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* I2C EEPROM */
+#ifdef CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_SPD_BUS_NUM 2
+#endif
+
+/* MMC Configs */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#endif
+
+/* OCOTP Configs */
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+/* PCI express */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29)
+#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12)
+#endif
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
+/* SATA Configs */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* UART */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART2_BASE
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_CONS_INDEX 1
+
+/* USB Configs */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+/* Gadget part */
+#define CONFIG_CI_UDC
+#define CONFIG_USBD_HS
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_CDC
+#define CONFIG_NETCONSOLE
+#endif
+
+/* Video output */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CMD_HDMIDETECT
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+/* Extra U-Boot environment. */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "consdev=ttymxc1\0" \
+ "baudrate=115200\0" \
+ "bootdev=/dev/mmcblk0p1\0" \
+ "rootdev=/dev/mmcblk0p2\0" \
+ "netdev=eth0\0" \
+ "kernel_addr_r=0x18000000\0" \
+ "addcons=" \
+ "setenv bootargs ${bootargs} " \
+ "console=${consdev},${baudrate}\0" \
+ "addip=" \
+ "setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:${hostname}:${netdev}:off\0" \
+ "addmisc=" \
+ "setenv bootargs ${bootargs} ${miscargs}\0" \
+ "addargs=run addcons addmisc\0" \
+ "mmcload=" \
+ "mmc rescan ; " \
+ "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \
+ "netload=" \
+ "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \
+ "miscargs=nohlt panic=1\0" \
+ "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \
+ "nfsargs=" \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath},v3,tcp\0" \
+ "mmc_mmc=" \
+ "run mmcload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "mmc_nfs=" \
+ "run mmcload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_mmc=" \
+ "run netload mmcargs addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "net_nfs=" \
+ "run netload nfsargs addip addargs ; " \
+ "bootm ${kernel_addr_r}\0" \
+ "update_sd_spl_filename=SPL\0" \
+ "update_sd_uboot_filename=u-boot.img\0" \
+ "update_sd_firmware=" /* Update the SD firmware partition */ \
+ "if mmc rescan ; then " \
+ "if dhcp ${update_sd_spl_filename} ; then " \
+ "mmc write ${loadaddr} 2 0x200 ; " \
+ "fi ; " \
+ "if dhcp ${update_sd_uboot_filename} ; then " \
+ "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\
+ "fi ; " \
+ "fi\0" \
+
+#endif /* __CONFIG_H */
* High Level Configuration Options
*/
#define CONFIG_MPC5200
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */
#define CONFIG_REVISION_TAG 1
-#define CONFIG_SUPPORT_RAW_INITRD
-
/* define to enable boot progress via leds */
#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
(CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
#ifdef CONFIG_MX6Q
#define CONFIG_CMD_SATA
#endif
#endif
#endif
-#define CONFIG_SYS_LITTLE_ENDIAN
-
#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
-#define CONFIG_DDR_FREQ 1600
-
/*
* Memory Size & Mapping
*/
#define CONFIG_DDR_NUM_CH0 2
#define CONFIG_DDR_NUM_CH1 2
-#define CONFIG_DDR_FREQ 1600
-
#define CONFIG_UNIPHIER_SMP
/*
#define CONFIG_DDR_NUM_CH0 1
#define CONFIG_DDR_NUM_CH1 1
-#define CONFIG_DDR_FREQ 1333
-
/* #define CONFIG_DDR_STANDARD */
/*
#define CONFIG_SYS_MAX_I2C_BUS 7
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
#define CONFIG_USB_GADGET_DUALSPEED
/*
#undef CONFIG_BOARD_COMMON
#undef CONFIG_USB_GADGET
#undef CONFIG_USB_GADGET_S3C_UDC_OTG
+#undef CONFIG_USB_GADGET_S3C_UDC_OTG_PHY
#undef CONFIG_CMD_USB_MASS_STORAGE
#undef CONFIG_REVISION_TAG
#undef CONFIG_CMD_THOR_DOWNLOAD
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x0
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
+/*
+ * EPCS/EPCQx1 Serial Flash Controller
+ */
+#ifdef CONFIG_ALTERA_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+/*
+ * The base address is configurable in QSys, each board must specify the
+ * base address based on it's particular FPGA configuration. Please note
+ * that the address here is incremented by 0x400 from the Base address
+ * selected in QSys, since the SPI registers are at offset +0x400.
+ * #define CONFIG_SYS_SPI_BASE 0xff240400
+ */
+#endif
+
/*
* Ethernet on SoC (EMAC)
*/
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
#endif
+ /*
+ * I2C support
+ */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_DW
+#define CONFIG_SYS_I2C_BUS_MAX 4
+#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
+#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
+#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
+#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
+/* Using standard mode which the speed up to 100Kb/s */
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SPEED1 100000
+#define CONFIG_SYS_I2C_SPEED2 100000
+#define CONFIG_SYS_I2C_SPEED3 100000
+/* Address of device when used as slave */
+#define CONFIG_SYS_I2C_SLAVE 0x02
+#define CONFIG_SYS_I2C_SLAVE1 0x02
+#define CONFIG_SYS_I2C_SLAVE2 0x02
+#define CONFIG_SYS_I2C_SLAVE3 0x02
+#ifndef __ASSEMBLY__
+/* Clock supplied to I2C controller in unit of MHz */
+unsigned int cm_get_l4_sp_clk_hz(void);
+#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
+#endif
+#define CONFIG_CMD_I2C
+
/*
* Serial Driver
*/
*/
#endif
+/*
+ * USB Gadget (DFU, UMS)
+ */
+#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
+#define DFU_DEFAULT_POLL_TIMEOUT 300
+
+/* USB IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x0525 /* NetChip */
+#define CONFIG_G_DNL_PRODUCT_NUM 0xA4A5 /* Linux-USB File-backed Storage Gadget */
+#define CONFIG_G_DNL_UMS_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_UMS_PRODUCT_NUM CONFIG_G_DNL_PRODUCT_NUM
+#ifndef CONFIG_G_DNL_MANUFACTURER
+#define CONFIG_G_DNL_MANUFACTURER "Altera"
+#endif
+#endif
+
/*
* U-Boot environment
*/
/* Booting Linux */
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "zImage"
-#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_BOOTCOMMAND "run ramboot"
#else
/*
* A10 specific configuration
*/
-#define CONFIG_SUN4I /* sun4i SoC generation */
#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun4i# "
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
-
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#ifndef CONFIG_SUNXI_USB_VBUS0_GPIO
-#define CONFIG_SUNXI_USB_VBUS0_GPIO SUNXI_GPH(6)
-#endif
-#ifndef CONFIG_SUNXI_USB_VBUS1_GPIO
-#define CONFIG_SUNXI_USB_VBUS1_GPIO SUNXI_GPH(3)
-#endif
#endif
/*
/*
* High Level Configuration Options
*/
-#define CONFIG_SUN5I /* sun5i SoC generation */
#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun5i# "
/*
* A31 specific configuration
*/
-#define CONFIG_SUN6I /* sun6i SoC generation */
+#define CONFIG_CLK_FULL_SPEED 1008000000
#define CONFIG_SYS_PROMPT "sun6i# "
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_SUNXI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
/*
* Include common sunxi configuration where most the settings are
*/
/*
* A20 specific configuration
*/
-#define CONFIG_SUN7I /* sun7i SoC generation */
#define CONFIG_CLK_FULL_SPEED 912000000
#define CONFIG_SYS_PROMPT "sun7i# "
#ifdef CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_SUNXI
-
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#ifndef CONFIG_SUNXI_USB_VBUS0_GPIO
-#define CONFIG_SUNXI_USB_VBUS0_GPIO SUNXI_GPH(6)
-#endif
-#ifndef CONFIG_SUNXI_USB_VBUS1_GPIO
-#define CONFIG_SUNXI_USB_VBUS1_GPIO SUNXI_GPH(3)
-#endif
#endif
#define CONFIG_ARMV7_VIRT 1
/*
* A23 specific configuration
*/
-#define CONFIG_SUN8I /* sun8i SoC generation */
#define CONFIG_SYS_PROMPT "sun8i# "
/*
#define CONFIG_SYS_TEXT_BASE 0x4a000000
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
+# define CONFIG_CMD_DM
+# define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_DW_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
+#endif
+
/*
* Display CPU information
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
-#define CONFIG_SYS_NS16550_REG_SIZE -4
#define CONFIG_SYS_NS16550_CLK 24000000
-#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
-#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
-#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
-#define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
+#ifndef CONFIG_DM_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE -4
+# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
+# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
+# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
+# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
+# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
+#endif
/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
--- /dev/null
+/*
+ * Copyright (C) 2014 Soeren Moch <smoch@web.de>
+ *
+ * Configuration settings for the TBS2910 MatrixARM board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __TBS2910_CONFIG_H
+#define __TBS2910_CONFIG_H
+
+#include "mx6_common.h"
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+
+/* General configuration */
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_MACH_TYPE 3980
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+#define CONFIG_SYS_GENERIC_BOARD
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+#define CONFIG_CMD_GPIO
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "Matrix U-Boot> "
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE \
+ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
+
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END \
+ (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
+
+#define CONFIG_SYS_TEXT_BASE 0x80000000
+#define CONFIG_SYS_BOOTMAPSZ 0x6C000000
+#define CONFIG_SYS_LOAD_ADDR 0x10800000
+
+/* Serial console */
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_CONS_INDEX 1
+
+/* *** Command definition *** */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_TIME
+
+/* Filesystems / image support */
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+#define CONFIG_CMD_FS_GENERIC
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_FIT
+
+/* MMC */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM 3
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+
+/* Ethernet */
+#define CONFIG_FEC_MXC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 4
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_CFB_CONSOLE_ANSI
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_IMX_HDMI
+#define CONFIG_IMX_VIDEO_SKIP
+#define CONFIG_CMD_HDMIDETECT
+#endif
+
+/* PCI */
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
+#endif
+
+/* SATA */
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_DWC_AHSATA_PORT_ID 0
+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
+/* USB */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#ifdef CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+#define CONFIG_SYS_STDIO_DEREGISTER
+#define CONFIG_PREBOOT "if hdmidet; then usb start; fi"
+#endif /* CONFIG_USB_KEYBOARD */
+#endif /* CONFIG_CMD_USB */
+
+/* RTC */
+#define CONFIG_CMD_DATE
+#ifdef CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_RTC_DS1307
+#define CONFIG_SYS_RTC_BUS_NUM 2
+#endif
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_I2C_EDID
+#endif
+
+/* Fuses */
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+/* Flash and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 2
+#define CONFIG_SYS_MMC_ENV_PART 1
+#define CONFIG_ENV_SIZE (8 * 1024)
+#define CONFIG_ENV_OFFSET (384 * 1024)
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
+ "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
+ "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
+ "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
+ "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
+ "${bootargs_mmc3}\0" \
+ "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
+ "rdinit=/sbin/init enable_wait_mode=off\0" \
+ "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
+ "mmc read 0x10800000 0x800 0x4000; bootm\0" \
+ "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
+ "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
+ "run bootargs_upd; " \
+ "bootm 0x10800000 0x10d00000\0" \
+ "console=ttymxc0\0" \
+ "fan=gpio set 92\0" \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vga\0" \
+ "stderr=serial,vga\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc rescan; " \
+ "if run bootcmd_up1; then " \
+ "run bootcmd_up2; " \
+ "else " \
+ "run bootcmd_mmc; " \
+ "fi"
+
+#endif /* __TBS2910_CONFIG_H * */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
/*
* Common filesystems support. When we have removable storage we
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_MX6
+
+/* SPL */
+/* #if defined(CONFIG_SPL_BUILD) */
+
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_EXT_SUPPORT
+
+/* common IMX6 SPL configuration */
+#include "imx6_spl.h"
+
+/* #endif */
+
#include "mx6_common.h"
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
#include <linux/sizes.h>
-#define CONFIG_MX6
-
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define PHYS_SDRAM_SIZE (512u * SZ_1M)
#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_BUS 0
-#define CONFIG_SF_DEFAULT_CS (0 | (IMX_GPIO_NR(3, 19) << 8))
+#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 50000000
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE
#define CONFIG_SMC911X_32_BIT
-#define CONFIG_SYS_MALLOC_F_LEN 0x7000
+#define CONFIG_SYS_MALLOC_F_LEN 0x2000
/*-----------------------------------------------------------------------
* MMU and Cache Setting
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_CMD_FAT
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
#define CONFIG_SYS_TEXT_BASE 0x84000000
-#if defined(CONFIG_SPL_BUILD)
#define CONFIG_BOARD_POSTCLK_INIT
-#else
+
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
/* Ethernet Configuration */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
--- /dev/null
+/*
+ * (C) Copyright 2012 Xilinx
+ * (C) Copyright 2014 Digilent Inc.
+ *
+ * Configuration for Zynq Development Board - ZYBO
+ * See zynq-common.h for Zynq common configs
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_ZYNQ_ZYBO_H
+#define __CONFIG_ZYNQ_ZYBO_H
+
+#define CONFIG_SYS_SDRAM_SIZE (512 * 1024 * 1024)
+
+#define CONFIG_ZYNQ_SERIAL_UART1
+#define CONFIG_ZYNQ_GEM0
+#define CONFIG_ZYNQ_GEM_PHY_ADDR0 0
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ZYNQ_SDHCI0
+#define CONFIG_ZYNQ_BOOT_FREEBSD
+
+/* Define ZYBO PS Clock Frequency to 50MHz */
+#define CONFIG_ZYNQ_PS_CLK_FREQ 50000000UL
+
+#include <configs/zynq-common.h>
+
+#endif /* __CONFIG_ZYNQ_ZYBO_H */
--- /dev/null
+/*
+ * This header provides constants for most input bindings.
+ *
+ * Most input bindings include key code, matrix key code format.
+ * In most cases, key code and matrix key code format uses
+ * the standard values/macro defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INPUT_INPUT_H
+#define _DT_BINDINGS_INPUT_INPUT_H
+
+#define KEY_RESERVED 0
+#define KEY_ESC 1
+#define KEY_1 2
+#define KEY_2 3
+#define KEY_3 4
+#define KEY_4 5
+#define KEY_5 6
+#define KEY_6 7
+#define KEY_7 8
+#define KEY_8 9
+#define KEY_9 10
+#define KEY_0 11
+#define KEY_MINUS 12
+#define KEY_EQUAL 13
+#define KEY_BACKSPACE 14
+#define KEY_TAB 15
+#define KEY_Q 16
+#define KEY_W 17
+#define KEY_E 18
+#define KEY_R 19
+#define KEY_T 20
+#define KEY_Y 21
+#define KEY_U 22
+#define KEY_I 23
+#define KEY_O 24
+#define KEY_P 25
+#define KEY_LEFTBRACE 26
+#define KEY_RIGHTBRACE 27
+#define KEY_ENTER 28
+#define KEY_LEFTCTRL 29
+#define KEY_A 30
+#define KEY_S 31
+#define KEY_D 32
+#define KEY_F 33
+#define KEY_G 34
+#define KEY_H 35
+#define KEY_J 36
+#define KEY_K 37
+#define KEY_L 38
+#define KEY_SEMICOLON 39
+#define KEY_APOSTROPHE 40
+#define KEY_GRAVE 41
+#define KEY_LEFTSHIFT 42
+#define KEY_BACKSLASH 43
+#define KEY_Z 44
+#define KEY_X 45
+#define KEY_C 46
+#define KEY_V 47
+#define KEY_B 48
+#define KEY_N 49
+#define KEY_M 50
+#define KEY_COMMA 51
+#define KEY_DOT 52
+#define KEY_SLASH 53
+#define KEY_RIGHTSHIFT 54
+#define KEY_KPASTERISK 55
+#define KEY_LEFTALT 56
+#define KEY_SPACE 57
+#define KEY_CAPSLOCK 58
+#define KEY_F1 59
+#define KEY_F2 60
+#define KEY_F3 61
+#define KEY_F4 62
+#define KEY_F5 63
+#define KEY_F6 64
+#define KEY_F7 65
+#define KEY_F8 66
+#define KEY_F9 67
+#define KEY_F10 68
+#define KEY_NUMLOCK 69
+#define KEY_SCROLLLOCK 70
+#define KEY_KP7 71
+#define KEY_KP8 72
+#define KEY_KP9 73
+#define KEY_KPMINUS 74
+#define KEY_KP4 75
+#define KEY_KP5 76
+#define KEY_KP6 77
+#define KEY_KPPLUS 78
+#define KEY_KP1 79
+#define KEY_KP2 80
+#define KEY_KP3 81
+#define KEY_KP0 82
+#define KEY_KPDOT 83
+
+#define KEY_ZENKAKUHANKAKU 85
+#define KEY_102ND 86
+#define KEY_F11 87
+#define KEY_F12 88
+#define KEY_RO 89
+#define KEY_KATAKANA 90
+#define KEY_HIRAGANA 91
+#define KEY_HENKAN 92
+#define KEY_KATAKANAHIRAGANA 93
+#define KEY_MUHENKAN 94
+#define KEY_KPJPCOMMA 95
+#define KEY_KPENTER 96
+#define KEY_RIGHTCTRL 97
+#define KEY_KPSLASH 98
+#define KEY_SYSRQ 99
+#define KEY_RIGHTALT 100
+#define KEY_LINEFEED 101
+#define KEY_HOME 102
+#define KEY_UP 103
+#define KEY_PAGEUP 104
+#define KEY_LEFT 105
+#define KEY_RIGHT 106
+#define KEY_END 107
+#define KEY_DOWN 108
+#define KEY_PAGEDOWN 109
+#define KEY_INSERT 110
+#define KEY_DELETE 111
+#define KEY_MACRO 112
+#define KEY_MUTE 113
+#define KEY_VOLUMEDOWN 114
+#define KEY_VOLUMEUP 115
+#define KEY_POWER 116 /* SC System Power Down */
+#define KEY_KPEQUAL 117
+#define KEY_KPPLUSMINUS 118
+#define KEY_PAUSE 119
+#define KEY_SCALE 120 /* AL Compiz Scale (Expose) */
+
+#define KEY_KPCOMMA 121
+#define KEY_HANGEUL 122
+#define KEY_HANGUEL KEY_HANGEUL
+#define KEY_HANJA 123
+#define KEY_YEN 124
+#define KEY_LEFTMETA 125
+#define KEY_RIGHTMETA 126
+#define KEY_COMPOSE 127
+
+#define KEY_STOP 128 /* AC Stop */
+#define KEY_AGAIN 129
+#define KEY_PROPS 130 /* AC Properties */
+#define KEY_UNDO 131 /* AC Undo */
+#define KEY_FRONT 132
+#define KEY_COPY 133 /* AC Copy */
+#define KEY_OPEN 134 /* AC Open */
+#define KEY_PASTE 135 /* AC Paste */
+#define KEY_FIND 136 /* AC Search */
+#define KEY_CUT 137 /* AC Cut */
+#define KEY_HELP 138 /* AL Integrated Help Center */
+#define KEY_MENU 139 /* Menu (show menu) */
+#define KEY_CALC 140 /* AL Calculator */
+#define KEY_SETUP 141
+#define KEY_SLEEP 142 /* SC System Sleep */
+#define KEY_WAKEUP 143 /* System Wake Up */
+#define KEY_FILE 144 /* AL Local Machine Browser */
+#define KEY_SENDFILE 145
+#define KEY_DELETEFILE 146
+#define KEY_XFER 147
+#define KEY_PROG1 148
+#define KEY_PROG2 149
+#define KEY_WWW 150 /* AL Internet Browser */
+#define KEY_MSDOS 151
+#define KEY_COFFEE 152 /* AL Terminal Lock/Screensaver */
+#define KEY_SCREENLOCK KEY_COFFEE
+#define KEY_DIRECTION 153
+#define KEY_CYCLEWINDOWS 154
+#define KEY_MAIL 155
+#define KEY_BOOKMARKS 156 /* AC Bookmarks */
+#define KEY_COMPUTER 157
+#define KEY_BACK 158 /* AC Back */
+#define KEY_FORWARD 159 /* AC Forward */
+#define KEY_CLOSECD 160
+#define KEY_EJECTCD 161
+#define KEY_EJECTCLOSECD 162
+#define KEY_NEXTSONG 163
+#define KEY_PLAYPAUSE 164
+#define KEY_PREVIOUSSONG 165
+#define KEY_STOPCD 166
+#define KEY_RECORD 167
+#define KEY_REWIND 168
+#define KEY_PHONE 169 /* Media Select Telephone */
+#define KEY_ISO 170
+#define KEY_CONFIG 171 /* AL Consumer Control Configuration */
+#define KEY_HOMEPAGE 172 /* AC Home */
+#define KEY_REFRESH 173 /* AC Refresh */
+#define KEY_EXIT 174 /* AC Exit */
+#define KEY_MOVE 175
+#define KEY_EDIT 176
+#define KEY_SCROLLUP 177
+#define KEY_SCROLLDOWN 178
+#define KEY_KPLEFTPAREN 179
+#define KEY_KPRIGHTPAREN 180
+#define KEY_NEW 181 /* AC New */
+#define KEY_REDO 182 /* AC Redo/Repeat */
+
+#define KEY_F13 183
+#define KEY_F14 184
+#define KEY_F15 185
+#define KEY_F16 186
+#define KEY_F17 187
+#define KEY_F18 188
+#define KEY_F19 189
+#define KEY_F20 190
+#define KEY_F21 191
+#define KEY_F22 192
+#define KEY_F23 193
+#define KEY_F24 194
+
+#define KEY_PLAYCD 200
+#define KEY_PAUSECD 201
+#define KEY_PROG3 202
+#define KEY_PROG4 203
+#define KEY_DASHBOARD 204 /* AL Dashboard */
+#define KEY_SUSPEND 205
+#define KEY_CLOSE 206 /* AC Close */
+#define KEY_PLAY 207
+#define KEY_FASTFORWARD 208
+#define KEY_BASSBOOST 209
+#define KEY_PRINT 210 /* AC Print */
+#define KEY_HP 211
+#define KEY_CAMERA 212
+#define KEY_SOUND 213
+#define KEY_QUESTION 214
+#define KEY_EMAIL 215
+#define KEY_CHAT 216
+#define KEY_SEARCH 217
+#define KEY_CONNECT 218
+#define KEY_FINANCE 219 /* AL Checkbook/Finance */
+#define KEY_SPORT 220
+#define KEY_SHOP 221
+#define KEY_ALTERASE 222
+#define KEY_CANCEL 223 /* AC Cancel */
+#define KEY_BRIGHTNESSDOWN 224
+#define KEY_BRIGHTNESSUP 225
+#define KEY_MEDIA 226
+
+#define KEY_SWITCHVIDEOMODE 227 /* Cycle between available video
+ outputs (Monitor/LCD/TV-out/etc) */
+#define KEY_KBDILLUMTOGGLE 228
+#define KEY_KBDILLUMDOWN 229
+#define KEY_KBDILLUMUP 230
+
+#define KEY_SEND 231 /* AC Send */
+#define KEY_REPLY 232 /* AC Reply */
+#define KEY_FORWARDMAIL 233 /* AC Forward Msg */
+#define KEY_SAVE 234 /* AC Save */
+#define KEY_DOCUMENTS 235
+
+#define KEY_BATTERY 236
+
+#define KEY_BLUETOOTH 237
+#define KEY_WLAN 238
+#define KEY_UWB 239
+
+#define KEY_UNKNOWN 240
+
+#define KEY_VIDEO_NEXT 241 /* drive next video source */
+#define KEY_VIDEO_PREV 242 /* drive previous video source */
+#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
+#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */
+#define KEY_DISPLAY_OFF 245 /* display device to off state */
+
+#define KEY_WIMAX 246
+#define KEY_RFKILL 247 /* Key that controls all radios */
+
+#define KEY_MICMUTE 248 /* Mute / unmute the microphone */
+
+/* Code 255 is reserved for special needs of AT keyboard driver */
+
+#define BTN_MISC 0x100
+#define BTN_0 0x100
+#define BTN_1 0x101
+#define BTN_2 0x102
+#define BTN_3 0x103
+#define BTN_4 0x104
+#define BTN_5 0x105
+#define BTN_6 0x106
+#define BTN_7 0x107
+#define BTN_8 0x108
+#define BTN_9 0x109
+
+#define BTN_MOUSE 0x110
+#define BTN_LEFT 0x110
+#define BTN_RIGHT 0x111
+#define BTN_MIDDLE 0x112
+#define BTN_SIDE 0x113
+#define BTN_EXTRA 0x114
+#define BTN_FORWARD 0x115
+#define BTN_BACK 0x116
+#define BTN_TASK 0x117
+
+#define BTN_JOYSTICK 0x120
+#define BTN_TRIGGER 0x120
+#define BTN_THUMB 0x121
+#define BTN_THUMB2 0x122
+#define BTN_TOP 0x123
+#define BTN_TOP2 0x124
+#define BTN_PINKIE 0x125
+#define BTN_BASE 0x126
+#define BTN_BASE2 0x127
+#define BTN_BASE3 0x128
+#define BTN_BASE4 0x129
+#define BTN_BASE5 0x12a
+#define BTN_BASE6 0x12b
+#define BTN_DEAD 0x12f
+
+#define BTN_GAMEPAD 0x130
+#define BTN_SOUTH 0x130
+#define BTN_A BTN_SOUTH
+#define BTN_EAST 0x131
+#define BTN_B BTN_EAST
+#define BTN_C 0x132
+#define BTN_NORTH 0x133
+#define BTN_X BTN_NORTH
+#define BTN_WEST 0x134
+#define BTN_Y BTN_WEST
+#define BTN_Z 0x135
+#define BTN_TL 0x136
+#define BTN_TR 0x137
+#define BTN_TL2 0x138
+#define BTN_TR2 0x139
+#define BTN_SELECT 0x13a
+#define BTN_START 0x13b
+#define BTN_MODE 0x13c
+#define BTN_THUMBL 0x13d
+#define BTN_THUMBR 0x13e
+
+#define BTN_DIGI 0x140
+#define BTN_TOOL_PEN 0x140
+#define BTN_TOOL_RUBBER 0x141
+#define BTN_TOOL_BRUSH 0x142
+#define BTN_TOOL_PENCIL 0x143
+#define BTN_TOOL_AIRBRUSH 0x144
+#define BTN_TOOL_FINGER 0x145
+#define BTN_TOOL_MOUSE 0x146
+#define BTN_TOOL_LENS 0x147
+#define BTN_TOOL_QUINTTAP 0x148 /* Five fingers on trackpad */
+#define BTN_TOUCH 0x14a
+#define BTN_STYLUS 0x14b
+#define BTN_STYLUS2 0x14c
+#define BTN_TOOL_DOUBLETAP 0x14d
+#define BTN_TOOL_TRIPLETAP 0x14e
+#define BTN_TOOL_QUADTAP 0x14f /* Four fingers on trackpad */
+
+#define BTN_WHEEL 0x150
+#define BTN_GEAR_DOWN 0x150
+#define BTN_GEAR_UP 0x151
+
+#define KEY_OK 0x160
+#define KEY_SELECT 0x161
+#define KEY_GOTO 0x162
+#define KEY_CLEAR 0x163
+#define KEY_POWER2 0x164
+#define KEY_OPTION 0x165
+#define KEY_INFO 0x166 /* AL OEM Features/Tips/Tutorial */
+#define KEY_TIME 0x167
+#define KEY_VENDOR 0x168
+#define KEY_ARCHIVE 0x169
+#define KEY_PROGRAM 0x16a /* Media Select Program Guide */
+#define KEY_CHANNEL 0x16b
+#define KEY_FAVORITES 0x16c
+#define KEY_EPG 0x16d
+#define KEY_PVR 0x16e /* Media Select Home */
+#define KEY_MHP 0x16f
+#define KEY_LANGUAGE 0x170
+#define KEY_TITLE 0x171
+#define KEY_SUBTITLE 0x172
+#define KEY_ANGLE 0x173
+#define KEY_ZOOM 0x174
+#define KEY_MODE 0x175
+#define KEY_KEYBOARD 0x176
+#define KEY_SCREEN 0x177
+#define KEY_PC 0x178 /* Media Select Computer */
+#define KEY_TV 0x179 /* Media Select TV */
+#define KEY_TV2 0x17a /* Media Select Cable */
+#define KEY_VCR 0x17b /* Media Select VCR */
+#define KEY_VCR2 0x17c /* VCR Plus */
+#define KEY_SAT 0x17d /* Media Select Satellite */
+#define KEY_SAT2 0x17e
+#define KEY_CD 0x17f /* Media Select CD */
+#define KEY_TAPE 0x180 /* Media Select Tape */
+#define KEY_RADIO 0x181
+#define KEY_TUNER 0x182 /* Media Select Tuner */
+#define KEY_PLAYER 0x183
+#define KEY_TEXT 0x184
+#define KEY_DVD 0x185 /* Media Select DVD */
+#define KEY_AUX 0x186
+#define KEY_MP3 0x187
+#define KEY_AUDIO 0x188 /* AL Audio Browser */
+#define KEY_VIDEO 0x189 /* AL Movie Browser */
+#define KEY_DIRECTORY 0x18a
+#define KEY_LIST 0x18b
+#define KEY_MEMO 0x18c /* Media Select Messages */
+#define KEY_CALENDAR 0x18d
+#define KEY_RED 0x18e
+#define KEY_GREEN 0x18f
+#define KEY_YELLOW 0x190
+#define KEY_BLUE 0x191
+#define KEY_CHANNELUP 0x192 /* Channel Increment */
+#define KEY_CHANNELDOWN 0x193 /* Channel Decrement */
+#define KEY_FIRST 0x194
+#define KEY_LAST 0x195 /* Recall Last */
+#define KEY_AB 0x196
+#define KEY_NEXT 0x197
+#define KEY_RESTART 0x198
+#define KEY_SLOW 0x199
+#define KEY_SHUFFLE 0x19a
+#define KEY_BREAK 0x19b
+#define KEY_PREVIOUS 0x19c
+#define KEY_DIGITS 0x19d
+#define KEY_TEEN 0x19e
+#define KEY_TWEN 0x19f
+#define KEY_VIDEOPHONE 0x1a0 /* Media Select Video Phone */
+#define KEY_GAMES 0x1a1 /* Media Select Games */
+#define KEY_ZOOMIN 0x1a2 /* AC Zoom In */
+#define KEY_ZOOMOUT 0x1a3 /* AC Zoom Out */
+#define KEY_ZOOMRESET 0x1a4 /* AC Zoom */
+#define KEY_WORDPROCESSOR 0x1a5 /* AL Word Processor */
+#define KEY_EDITOR 0x1a6 /* AL Text Editor */
+#define KEY_SPREADSHEET 0x1a7 /* AL Spreadsheet */
+#define KEY_GRAPHICSEDITOR 0x1a8 /* AL Graphics Editor */
+#define KEY_PRESENTATION 0x1a9 /* AL Presentation App */
+#define KEY_DATABASE 0x1aa /* AL Database App */
+#define KEY_NEWS 0x1ab /* AL Newsreader */
+#define KEY_VOICEMAIL 0x1ac /* AL Voicemail */
+#define KEY_ADDRESSBOOK 0x1ad /* AL Contacts/Address Book */
+#define KEY_MESSENGER 0x1ae /* AL Instant Messaging */
+#define KEY_DISPLAYTOGGLE 0x1af /* Turn display (LCD) on and off */
+#define KEY_SPELLCHECK 0x1b0 /* AL Spell Check */
+#define KEY_LOGOFF 0x1b1 /* AL Logoff */
+
+#define KEY_DOLLAR 0x1b2
+#define KEY_EURO 0x1b3
+
+#define KEY_FRAMEBACK 0x1b4 /* Consumer - transport controls */
+#define KEY_FRAMEFORWARD 0x1b5
+#define KEY_CONTEXT_MENU 0x1b6 /* GenDesc - system context menu */
+#define KEY_MEDIA_REPEAT 0x1b7 /* Consumer - transport control */
+#define KEY_10CHANNELSUP 0x1b8 /* 10 channels up (10+) */
+#define KEY_10CHANNELSDOWN 0x1b9 /* 10 channels down (10-) */
+#define KEY_IMAGES 0x1ba /* AL Image Browser */
+
+#define KEY_DEL_EOL 0x1c0
+#define KEY_DEL_EOS 0x1c1
+#define KEY_INS_LINE 0x1c2
+#define KEY_DEL_LINE 0x1c3
+
+#define KEY_FN 0x1d0
+#define KEY_FN_ESC 0x1d1
+#define KEY_FN_F1 0x1d2
+#define KEY_FN_F2 0x1d3
+#define KEY_FN_F3 0x1d4
+#define KEY_FN_F4 0x1d5
+#define KEY_FN_F5 0x1d6
+#define KEY_FN_F6 0x1d7
+#define KEY_FN_F7 0x1d8
+#define KEY_FN_F8 0x1d9
+#define KEY_FN_F9 0x1da
+#define KEY_FN_F10 0x1db
+#define KEY_FN_F11 0x1dc
+#define KEY_FN_F12 0x1dd
+#define KEY_FN_1 0x1de
+#define KEY_FN_2 0x1df
+#define KEY_FN_D 0x1e0
+#define KEY_FN_E 0x1e1
+#define KEY_FN_F 0x1e2
+#define KEY_FN_S 0x1e3
+#define KEY_FN_B 0x1e4
+
+#define KEY_BRL_DOT1 0x1f1
+#define KEY_BRL_DOT2 0x1f2
+#define KEY_BRL_DOT3 0x1f3
+#define KEY_BRL_DOT4 0x1f4
+#define KEY_BRL_DOT5 0x1f5
+#define KEY_BRL_DOT6 0x1f6
+#define KEY_BRL_DOT7 0x1f7
+#define KEY_BRL_DOT8 0x1f8
+#define KEY_BRL_DOT9 0x1f9
+#define KEY_BRL_DOT10 0x1fa
+
+#define KEY_NUMERIC_0 0x200 /* used by phones, remote controls, */
+#define KEY_NUMERIC_1 0x201 /* and other keypads */
+#define KEY_NUMERIC_2 0x202
+#define KEY_NUMERIC_3 0x203
+#define KEY_NUMERIC_4 0x204
+#define KEY_NUMERIC_5 0x205
+#define KEY_NUMERIC_6 0x206
+#define KEY_NUMERIC_7 0x207
+#define KEY_NUMERIC_8 0x208
+#define KEY_NUMERIC_9 0x209
+#define KEY_NUMERIC_STAR 0x20a
+#define KEY_NUMERIC_POUND 0x20b
+
+#define KEY_CAMERA_FOCUS 0x210
+#define KEY_WPS_BUTTON 0x211 /* WiFi Protected Setup key */
+
+#define KEY_TOUCHPAD_TOGGLE 0x212 /* Request switch touchpad on or off */
+#define KEY_TOUCHPAD_ON 0x213
+#define KEY_TOUCHPAD_OFF 0x214
+
+#define KEY_CAMERA_ZOOMIN 0x215
+#define KEY_CAMERA_ZOOMOUT 0x216
+#define KEY_CAMERA_UP 0x217
+#define KEY_CAMERA_DOWN 0x218
+#define KEY_CAMERA_LEFT 0x219
+#define KEY_CAMERA_RIGHT 0x21a
+
+#define KEY_ATTENDANT_ON 0x21b
+#define KEY_ATTENDANT_OFF 0x21c
+#define KEY_ATTENDANT_TOGGLE 0x21d /* Attendant call on or off */
+#define KEY_LIGHTS_TOGGLE 0x21e /* Reading light on or off */
+
+#define BTN_DPAD_UP 0x220
+#define BTN_DPAD_DOWN 0x221
+#define BTN_DPAD_LEFT 0x222
+#define BTN_DPAD_RIGHT 0x223
+
+#define MATRIX_KEY(row, col, code) \
+ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF))
+
+#endif /* _DT_BINDINGS_INPUT_INPUT_H */
--- /dev/null
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET 2
+#define SCUPER_RESET 3
+#define L2_RESET 4
+
+/* PERMODRST */
+#define EMAC0_RESET 32
+#define EMAC1_RESET 33
+#define USB0_RESET 34
+#define USB1_RESET 35
+#define NAND_RESET 36
+#define QSPI_RESET 37
+#define L4WD0_RESET 38
+#define L4WD1_RESET 39
+#define OSC1TIMER0_RESET 40
+#define OSC1TIMER1_RESET 41
+#define SPTIMER0_RESET 42
+#define SPTIMER1_RESET 43
+#define I2C0_RESET 44
+#define I2C1_RESET 45
+#define I2C2_RESET 46
+#define I2C3_RESET 47
+#define UART0_RESET 48
+#define UART1_RESET 49
+#define SPIM0_RESET 50
+#define SPIM1_RESET 51
+#define SPIS0_RESET 52
+#define SPIS1_RESET 53
+#define SDMMC_RESET 54
+#define CAN0_RESET 55
+#define CAN1_RESET 56
+#define GPIO0_RESET 57
+#define GPIO1_RESET 58
+#define GPIO2_RESET 59
+#define DMA_RESET 60
+#define SDR_RESET 61
+
+/* PER2MODRST */
+#define DMAIF0_RESET 64
+#define DMAIF1_RESET 65
+#define DMAIF2_RESET 66
+#define DMAIF3_RESET 67
+#define DMAIF4_RESET 68
+#define DMAIF5_RESET 69
+#define DMAIF6_RESET 70
+#define DMAIF7_RESET 71
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET 97
+#define FPGA2HPS_RESET 98
+
+/* MISCMODRST*/
+#define ROM_RESET 128
+#define OCRAM_RESET 129
+#define SYSMGR_RESET 130
+#define SYSMGRCOLD_RESET 131
+#define FPGAMGR_RESET 132
+#define ACPIDMAP_RESET 133
+#define S2F_RESET 134
+#define S2FCOLD_RESET 135
+#define NRSTPIN_RESET 136
+#define TIMESTAMPCOLD_RESET 137
+#define CLKMGRCOLD_RESET 138
+#define SCANMGR_RESET 139
+#define FRZCTRLCOLD_RESET 140
+#define SYSDBG_RESET 141
+#define DBG_RESET 142
+#define TAPCOLD_RESET 143
+#define SDRCOLD_RESET 144
+
+#endif
#define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */
#define IH_ARCH_ARM64 22 /* ARM64 */
#define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */
+#define IH_ARCH_X86_64 24 /* AMD x86_64, Intel and Via */
/*
* Image Types
void *priv; /* Pointer to driver-specific data */
} vidinfo_t;
-#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
+#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */
extern vidinfo_t panel_info;
--- /dev/null
+/*
+ * include/linux/serial_reg.h
+ *
+ * Copyright (C) 1992, 1994 by Theodore Ts'o.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * These are the UART port assignments, expressed as offsets from the base
+ * register. These assignments should hold for any serial port based on
+ * a 8250, 16450, or 16550(A).
+ */
+
+#ifndef _LINUX_SERIAL_REG_H
+#define _LINUX_SERIAL_REG_H
+
+/*
+ * DLAB=0
+ */
+#define UART_RX 0 /* In: Receive buffer */
+#define UART_TX 0 /* Out: Transmit buffer */
+
+#define UART_IER 1 /* Out: Interrupt Enable Register */
+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
+/*
+ * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
+ */
+#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
+
+#define UART_IIR 2 /* In: Interrupt ID Register */
+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define UART_IIR_ID 0x0e /* Mask for the interrupt ID */
+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+#define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */
+
+#define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */
+#define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */
+#define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */
+
+#define UART_FCR 2 /* Out: FIFO Control Register */
+#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+/*
+ * Note: The FIFO trigger levels are chip specific:
+ * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
+ * PC16550D: 1 4 8 14 xx xx xx xx
+ * TI16C550A: 1 4 8 14 xx xx xx xx
+ * TI16C550C: 1 4 8 14 xx xx xx xx
+ * ST16C550: 1 4 8 14 xx xx xx xx
+ * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
+ * NS16C552: 1 4 8 14 xx xx xx xx
+ * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
+ * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
+ * TI16C752: 8 16 56 60 8 16 32 56
+ * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
+ */
+#define UART_FCR_R_TRIG_00 0x00
+#define UART_FCR_R_TRIG_01 0x40
+#define UART_FCR_R_TRIG_10 0x80
+#define UART_FCR_R_TRIG_11 0xc0
+#define UART_FCR_T_TRIG_00 0x00
+#define UART_FCR_T_TRIG_01 0x10
+#define UART_FCR_T_TRIG_10 0x20
+#define UART_FCR_T_TRIG_11 0x30
+
+#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+/* 16650 definitions */
+#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
+#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
+#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
+#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
+#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
+#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
+
+#define UART_LCR 3 /* Out: Line Control Register */
+/*
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
+#define UART_LCR_SBC 0x40 /* Set break control */
+#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
+#define UART_LCR_EPAR 0x10 /* Even parity select */
+#define UART_LCR_PARITY 0x08 /* Parity Enable */
+#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
+#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
+#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
+#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
+#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
+
+/*
+ * Access to some registers depends on register access / configuration
+ * mode.
+ */
+#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */
+#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */
+
+#define UART_MCR 4 /* Out: Modem Control Register */
+#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
+#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
+#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
+#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_OUT2 0x08 /* Out2 complement */
+#define UART_MCR_OUT1 0x04 /* Out1 complement */
+#define UART_MCR_RTS 0x02 /* RTS complement */
+#define UART_MCR_DTR 0x01 /* DTR complement */
+
+#define UART_LSR 5 /* In: Line Status Register */
+#define UART_LSR_FIFOE 0x80 /* Fifo error */
+#define UART_LSR_TEMT 0x40 /* Transmitter empty */
+#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
+#define UART_LSR_BI 0x10 /* Break interrupt indicator */
+#define UART_LSR_FE 0x08 /* Frame error indicator */
+#define UART_LSR_PE 0x04 /* Parity error indicator */
+#define UART_LSR_OE 0x02 /* Overrun error indicator */
+#define UART_LSR_DR 0x01 /* Receiver data ready */
+#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
+
+#define UART_MSR 6 /* In: Modem Status Register */
+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
+#define UART_MSR_RI 0x40 /* Ring Indicator */
+#define UART_MSR_DSR 0x20 /* Data Set Ready */
+#define UART_MSR_CTS 0x10 /* Clear to Send */
+#define UART_MSR_DDCD 0x08 /* Delta DCD */
+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR 0x02 /* Delta DSR */
+#define UART_MSR_DCTS 0x01 /* Delta CTS */
+#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
+
+#define UART_SCR 7 /* I/O: Scratch Register */
+
+/*
+ * DLAB=1
+ */
+#define UART_DLL 0 /* Out: Divisor Latch Low */
+#define UART_DLM 1 /* Out: Divisor Latch High */
+
+/*
+ * LCR=0xBF (or DLAB=1 for 16C660)
+ */
+#define UART_EFR 2 /* I/O: Extended Features Register */
+#define UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */
+#define UART_EFR_CTS 0x80 /* CTS flow control */
+#define UART_EFR_RTS 0x40 /* RTS flow control */
+#define UART_EFR_SCD 0x20 /* Special character detect */
+#define UART_EFR_ECB 0x10 /* Enhanced control bit */
+/*
+ * the low four bits control software flow control
+ */
+
+/*
+ * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
+ */
+#define UART_XON1 4 /* I/O: Xon character 1 */
+#define UART_XON2 5 /* I/O: Xon character 2 */
+#define UART_XOFF1 6 /* I/O: Xoff character 1 */
+#define UART_XOFF2 7 /* I/O: Xoff character 2 */
+
+/*
+ * EFR[4]=1 MCR[6]=1, TI16C752
+ */
+#define UART_TI752_TCR 6 /* I/O: transmission control register */
+#define UART_TI752_TLR 7 /* I/O: trigger level register */
+
+/*
+ * LCR=0xBF, XR16C85x
+ */
+#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
+ * In: Fifo count
+ * Out: Fifo custom trigger levels */
+/*
+ * These are the definitions for the Programmable Trigger Register
+ */
+#define UART_TRG_1 0x01
+#define UART_TRG_4 0x04
+#define UART_TRG_8 0x08
+#define UART_TRG_16 0x10
+#define UART_TRG_32 0x20
+#define UART_TRG_64 0x40
+#define UART_TRG_96 0x60
+#define UART_TRG_120 0x78
+#define UART_TRG_128 0x80
+
+#define UART_FCTR 1 /* Feature Control Register */
+#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
+#define UART_FCTR_RTS_4DELAY 0x01
+#define UART_FCTR_RTS_6DELAY 0x02
+#define UART_FCTR_RTS_8DELAY 0x03
+#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
+#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
+#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
+#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
+#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
+#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
+#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
+#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
+#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
+
+/*
+ * LCR=0xBF, FCTR[6]=1
+ */
+#define UART_EMSR 7 /* Extended Mode Select Register */
+#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
+#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
+
+/*
+ * The Intel XScale on-chip UARTs define these bits
+ */
+#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
+#define UART_IER_UUE 0x40 /* UART Unit Enable */
+#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
+#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
+
+#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
+
+#define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */
+#define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */
+#define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */
+#define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */
+
+/*
+ * Intel MID on-chip HSU (High Speed UART) defined bits
+ */
+#define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */
+#define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */
+#define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */
+#define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */
+
+#define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */
+#define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */
+#define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */
+#define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */
+
+#define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */
+#define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */
+
+#define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */
+#define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */
+
+/*
+ * These register definitions are for the 16C950
+ */
+#define UART_ASR 0x01 /* Additional Status Register */
+#define UART_RFL 0x03 /* Receiver FIFO level */
+#define UART_TFL 0x04 /* Transmitter FIFO level */
+#define UART_ICR 0x05 /* Index Control Register */
+
+/* The 16950 ICR registers */
+#define UART_ACR 0x00 /* Additional Control Register */
+#define UART_CPR 0x01 /* Clock Prescalar Register */
+#define UART_TCR 0x02 /* Times Clock Register */
+#define UART_CKS 0x03 /* Clock Select Register */
+#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
+#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
+#define UART_FCL 0x06 /* Flow Control Level Lower */
+#define UART_FCH 0x07 /* Flow Control Level Higher */
+#define UART_ID1 0x08 /* ID #1 */
+#define UART_ID2 0x09 /* ID #2 */
+#define UART_ID3 0x0A /* ID #3 */
+#define UART_REV 0x0B /* Revision */
+#define UART_CSR 0x0C /* Channel Software Reset */
+#define UART_NMR 0x0D /* Nine-bit Mode Register */
+#define UART_CTR 0xFF
+
+/*
+ * The 16C950 Additional Control Register
+ */
+#define UART_ACR_RXDIS 0x01 /* Receiver disable */
+#define UART_ACR_TXDIS 0x02 /* Transmitter disable */
+#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
+#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
+#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
+#define UART_ACR_ASREN 0x80 /* Additional status enable */
+
+
+
+/*
+ * These definitions are for the RSA-DV II/S card, from
+ *
+ * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
+ */
+
+#define UART_RSA_BASE (-8)
+
+#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
+
+#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
+#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
+#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
+#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
+
+#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
+
+#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
+#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
+#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
+#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
+#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
+
+#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
+
+#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
+#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
+#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
+#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
+#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
+#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
+#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
+#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
+
+#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
+
+#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
+
+#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
+
+#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
+
+/*
+ * The RSA DSV/II board has two fixed clock frequencies. One is the
+ * standard rate, and the other is 8 times faster.
+ */
+#define SERIAL_RSA_BAUD_BASE (921600)
+#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
+
+/*
+ * Extra serial register definitions for the internal UARTs
+ * in TI OMAP processors.
+ */
+#define UART_OMAP_MDR1 0x08 /* Mode definition register */
+#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
+#define UART_OMAP_SCR 0x10 /* Supplementary control register */
+#define UART_OMAP_SSR 0x11 /* Supplementary status register */
+#define UART_OMAP_EBLR 0x12 /* BOF length register */
+#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
+#define UART_OMAP_MVER 0x14 /* Module version register */
+#define UART_OMAP_SYSC 0x15 /* System configuration register */
+#define UART_OMAP_SYSS 0x16 /* System status register */
+#define UART_OMAP_WER 0x17 /* Wake-up enable register */
+
+/*
+ * These are the definitions for the MDR1 register
+ */
+#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
+#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */
+#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
+#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */
+#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */
+#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */
+#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */
+#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
+
+/*
+ * These are definitions for the Exar XR17V35X and XR17(C|D)15X
+ */
+#define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */
+#define UART_EXAR_SLEEP 0x8b /* Sleep mode */
+#define UART_EXAR_DVID 0x8d /* Device identification */
+
+#define UART_EXAR_FCTR 0x08 /* Feature Control Register */
+#define UART_FCTR_EXAR_IRDA 0x08 /* IrDa data encode select */
+#define UART_FCTR_EXAR_485 0x10 /* Auto 485 half duplex dir ctl */
+#define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */
+#define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */
+#define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */
+#define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */
+
+#define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */
+#define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */
+
+#endif /* _LINUX_SERIAL_REG_H */
+
/* Access the serial operations for a device */
#define serial_get_ops(dev) ((struct dm_serial_ops *)(dev)->driver->ops)
+void altera_jtag_serial_initialize(void);
+void altera_serial_initialize(void);
+void amirix_serial_initialize(void);
+void arc_serial_initialize(void);
+void arm_dcc_initialize(void);
+void asc_serial_initialize(void);
+void atmel_serial_initialize(void);
+void au1x00_serial_initialize(void);
+void bfin_jtag_initialize(void);
+void bfin_serial_initialize(void);
+void bmw_serial_initialize(void);
+void clps7111_serial_initialize(void);
+void cogent_serial_initialize(void);
+void cpci750_serial_initialize(void);
+void evb64260_serial_initialize(void);
+void imx_serial_initialize(void);
+void iop480_serial_initialize(void);
+void jz_serial_initialize(void);
+void ks8695_serial_initialize(void);
+void leon2_serial_initialize(void);
+void leon3_serial_initialize(void);
+void lh7a40x_serial_initialize(void);
+void lpc32xx_serial_initialize(void);
+void marvell_serial_initialize(void);
+void max3100_serial_initialize(void);
+void mcf_serial_initialize(void);
+void ml2_serial_initialize(void);
+void mpc512x_serial_initialize(void);
+void mpc5xx_serial_initialize(void);
+void mpc8260_scc_serial_initialize(void);
+void mpc8260_smc_serial_initialize(void);
+void mpc85xx_serial_initialize(void);
+void mpc8xx_serial_initialize(void);
+void mxc_serial_initialize(void);
+void mxs_auart_initialize(void);
+void ns16550_serial_initialize(void);
+void oc_serial_initialize(void);
+void p3mx_serial_initialize(void);
+void pl01x_serial_initialize(void);
+void pxa_serial_initialize(void);
+void s3c24xx_serial_initialize(void);
+void s5p_serial_initialize(void);
+void sa1100_serial_initialize(void);
+void sandbox_serial_initialize(void);
+void sconsole_serial_initialize(void);
+void sh_serial_initialize(void);
+void uartlite_serial_initialize(void);
+void zynq_serial_initialize(void);
+
#endif
/* Voltage Selection in PM Receiver Module */
#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
+#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09
+#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01
#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03
+#define TWL4030_PM_RECEIVER_VMMC2_VSEL_30 0x0B
+#define TWL4030_PM_RECEIVER_VMMC2_VSEL_32 0x0C
#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03
/* Device Selection in PM Receiver Module */
#include <usb_defs.h>
#include <linux/usb/ch9.h>
+#include <asm/cache.h>
+#include <part.h>
/*
* The EHCI spec says that we must align to at least 32 bytes. However,
unsigned int slot_id;
};
+struct int_queue;
+
/*
* You can initialize platform's USB host or device
* ports by passing this enum as an argument to
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int transfer_len, int interval);
+#ifdef CONFIG_USB_EHCI /* Only the ehci code has pollable int support */
+struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe,
+ int queuesize, int elementsize, void *buffer);
+int destroy_int_queue(struct usb_device *dev, struct int_queue *queue);
+void *poll_int_queue(struct usb_device *dev, struct int_queue *queue);
+#endif
+
/* Defines */
#define USB_UHCI_VEND_ID 0x8086
#define USB_UHCI_DEV_ID 0x7112
+++ /dev/null
-/*
- * (C) Copyright 2003
- * Gerry Hamel, geh@ti.com, Texas Instruments
- *
- * Based on
- * linux/drivers/usb/device/bi/omap.h
- * Register definitions for TI OMAP1510 USB bus interface driver
- *
- * Author: MontaVista Software, Inc.
- * source@mvista.com
- *
- * 2003 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __USBDCORE_OMAP1510_H__
-#define __USBDCORE_OMAP1510_H__
-
-
-/*
- * 13.2 MPU Register Map
- */
-
-/* Table 13-1. USB Function Module Registers (endpoint) */
-#define UDC_BASE 0xFFFB4000
-#define UDC_OFFSET(offset) (UDC_BASE + (offset))
-#define UDC_REV UDC_OFFSET(0x0) /* Revision */
-#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */
-#define UDC_DATA UDC_OFFSET(0x08) /* Data */
-#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */
-#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */
-#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */
-#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */
-#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */
-#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */
-#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */
-#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */
-#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */
-#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */
-#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */
-#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */
-
-/* IRQ_EN register fields */
-#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */
-#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */
-#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */
-#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */
-#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */
-
-/* IRQ_SRC register fields */
-#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */
-#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */
-#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */
-#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */
-#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */
-#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */
-#define UDC_DS_Chg (1 << 3) /* Device state changed */
-#define UDC_Setup (1 << 2) /* Setup transaction */
-#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */
-#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */
-
-/* DEVSTAT register fields, 14.2.9 */
-#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */
-#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */
-#define UDC_SUS (1 << 4) /* Suspended state */
-#define UDC_CFG (1 << 3) /* Configured state */
-#define UDC_ADD (1 << 2) /* Addressed state */
-#define UDC_DEF (1 << 1) /* Default state */
-#define UDC_ATT (1 << 0) /* Attached state */
-
-/* SYSCON1 register fields */
-#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */
-#define UDC_Nak_En (1 << 4) /* NAK enable */
-#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */
-#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */
-#define UDC_Pullup_En (1 << 0) /* External pullup enabled */
-
-/* SYSCON2 register fields */
-#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */
-#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */
-#define UDC_Dev_Cfg (1 << 3) /* Device configured */
-#define UDC_Clr_Cfg (1 << 2) /* Clear configured */
-
-/*
- * Select and enable endpoints
- */
-
-/* Table 13-1. USB Function Module Registers (endpoint configuration) */
-#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */
-#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */
-#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */
-#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4)
-#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */
-#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4)
-
-/* EP_NUM register fields */
-#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */
-#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */
-#define UDC_EP_Dir (1 << 4) /* Endpoint direction */
-
-/* CTRL register fields */
-#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */
-#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */
-#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */
-#define UDC_Clr_EP (1 << 1) /* Clear endpoint */
-#define UDC_Reset_EP (1 << 0) /* Reset endpoint */
-
-/* STAT_FLG register fields */
-#define UDC_Miss_In (1 << 14)
-#define UDC_Data_Flush (1 << 13)
-#define UDC_ISO_Err (1 << 12)
-#define UDC_ISO_FIFO_Empty (1 << 9)
-#define UDC_ISO_FIFO_Full (1 << 8)
-#define UDC_EP_Halted (1 << 6)
-#define UDC_STALL (1 << 5)
-#define UDC_NAK (1 << 4)
-#define UDC_ACK (1 << 3)
-#define UDC_FIFO_En (1 << 2)
-#define UDC_Non_ISO_FIFO_Empty (1 << 1)
-#define UDC_Non_ISO_FIFO_Full (1 << 0)
-
-/* EPn_RX register fields */
-#define UDC_EPn_RX_Valid (1 << 15) /* valid */
-#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */
-#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */
-
-/* EPn_TX register fields */
-#define UDC_EPn_TX_Valid (1 << 15) /* valid */
-#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */
-#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */
-
-#define EP0_PACKETSIZE 0x40
-
-/* physical to logical endpoint mapping
- * Physical endpoints are an index into device->bus->endpoint_array.
- * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in
- * the USB specification.
- *
- * physical ep logical ep direction endpoint_address
- * 0 0 IN and OUT 0x00
- * 1 to 15 1 to 15 OUT 0x01 to 0x0f
- * 16 to 30 1 to 15 IN 0x81 to 0x8f
- */
-#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80))
-#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a))
-
-/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */
-#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17)
-
-/* Other registers (may be) related to USB */
-
-#define CLOCK_CTRL (0xFFFE0830)
-#define APLL_CTRL (0xFFFE084C)
-#define DPLL_CTRL (0xFFFE083C)
-#define SOFT_REQ (0xFFFE0834)
-#define STATUS_REQ (0xFFFE0840)
-
-/* FUNC_MUX_CTRL_0 bits related to USB */
-#define UDC_VBUS_CTRL (1 << 19)
-#define UDC_VBUS_MODE (1 << 18)
-
-/* OMAP Endpoint parameters */
-#define UDC_OUT_PACKET_SIZE 64
-#define UDC_IN_PACKET_SIZE 64
-#define UDC_INT_PACKET_SIZE 16
-#define UDC_BULK_PACKET_SIZE 16
-
-#define UDC_INT_ENDPOINT 5
-#define UDC_OUT_ENDPOINT 2
-#define UDC_IN_ENDPOINT 1
-
-#endif
unsigned int regs_otg;
unsigned int usb_phy_ctrl;
unsigned int usb_flags;
+ unsigned int usb_gusbcfg;
};
#endif
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj=
# Usage:
# $(Q)$(MAKE) $(build)=dir
-build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj
+build := -f $(srctree)/scripts/Makefile.build obj
###
# Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj=
# Usage:
# $(Q)$(MAKE) $(modbuiltin)=dir
-modbuiltin := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.modbuiltin obj
+modbuiltin := -f $(srctree)/scripts/Makefile.modbuiltin obj
# Prefix -I with $(srctree) if it is not an absolute path.
# skip if -I has no parameter
arg-check = $(if $(strip $(cmd_$@)),,1)
endif
-# >'< substitution is for echo to work,
-# >$< substitution to preserve $ when reloading .cmd file
-# note: when using inline perl scripts [perl -e '...$$t=1;...']
-# in $(cmd_xxx) double $$ your perl vars
-make-cmd = $(subst \\,\\\\,$(subst \#,\\\#,$(subst $$,$$$$,$(call escsq,$(cmd_$(1))))))
+# Replace >$< with >$$< to preserve $ when reloading the .cmd file
+# (needed for make)
+# Replace >#< with >\#< to avoid starting a comment in the .cmd file
+# (needed for make)
+# Replace >'< with >'\''< to be able to enclose the whole string in '...'
+# (needed for the shell)
+make-cmd = $(call escsq,$(subst \#,\\\#,$(subst $$,$$$$,$(cmd_$(1)))))
# Find any prerequisites that is newer than target or that does not exist.
# PHONY targets skipped in both cases.
if_changed = $(if $(strip $(any-prereq) $(arg-check)), \
@set -e; \
$(echo-cmd) $(cmd_$(1)); \
- echo 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
+ printf '%s\n' 'cmd_$@ := $(make-cmd)' > $(dot-target).cmd)
# Execute the command and also postprocess generated .d dependencies file.
if_changed_dep = $(if $(strip $(any-prereq) $(arg-check) ), \
create_symlink:
ifneq ($(KBUILD_SRC),)
$(Q)mkdir -p include/asm
+ $(Q)ln -fsn $(KBUILD_SRC)/arch/$(ARCH)/include/asm/arch-$(if $(SOC),$(SOC),$(CPU)) \
+ include/asm/arch
+else
+ $(Q)ln -fsn arch-$(if $(SOC),$(SOC),$(CPU)) \
+ arch/$(ARCH)/include/asm/arch
endif
- $(Q)ln -fsn $(srctree)/arch/$(ARCH)/include/asm/arch-$(if $(SOC),$(SOC),$(CPU)) \
- $(if $(KBUILD_SRC),,arch/$(ARCH)/)include/asm/arch
PHONY += FORCE
FORCE:
# ===========================================================================
-ifneq ($(strip $(lib-y) $(lib-m) $(lib-n) $(lib-)),)
+ifneq ($(strip $(lib-y) $(lib-m) $(lib-)),)
lib-target := $(obj)/lib.a
endif
-ifneq ($(strip $(obj-y) $(obj-m) $(obj-n) $(obj-) $(subdir-m) $(lib-target)),)
+ifneq ($(strip $(obj-y) $(obj-m) $(obj-) $(subdir-m) $(lib-target)),)
builtin-target := $(obj)/built-in.o
endif
quiet_cmd_link_multi-m = LD [M] $@
cmd_link_multi-m = $(cmd_link_multi-y)
-# We would rather have a list of rules like
-# foo.o: $(foo-objs)
-# but that's not so easy, so we rather make all composite objects depend
-# on the set of all their parts
-$(multi-used-y) : %.o: $(multi-objs-y) FORCE
+$(multi-used-y): FORCE
$(call if_changed,link_multi-y)
+$(call multi_depend, $(multi-used-y), .o, -objs -y)
-$(multi-used-m) : %.o: $(multi-objs-m) FORCE
+$(multi-used-m): FORCE
$(call if_changed,link_multi-m)
@{ echo $(@:.o=.ko); echo $(link_multi_deps); } > $(MODVERDIR)/$(@F:.o=.mod)
+$(call multi_depend, $(multi-used-m), .o, -objs -y)
targets += $(multi-used-y) $(multi-used-m)
# Shorthand for $(Q)$(MAKE) scripts/Makefile.clean obj=dir
# Usage:
# $(Q)$(MAKE) $(clean)=dir
-clean := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.clean obj
+clean := -f $(srctree)/scripts/Makefile.clean obj
# The filename Kbuild has precedence over Makefile
kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src))
subdir-y += $(__subdir-y)
__subdir-m := $(patsubst %/,%,$(filter %/, $(obj-m)))
subdir-m += $(__subdir-m)
-__subdir-n := $(patsubst %/,%,$(filter %/, $(obj-n)))
-subdir-n += $(__subdir-n)
__subdir- := $(patsubst %/,%,$(filter %/, $(obj-)))
subdir- += $(__subdir-)
# Subdirectories we need to descend into
subdir-ym := $(sort $(subdir-y) $(subdir-m))
-subdir-ymn := $(sort $(subdir-ym) $(subdir-n) $(subdir-))
+subdir-ymn := $(sort $(subdir-ym) $(subdir-))
# Add subdir path
warning-1 += $(call cc-option, -Wunused-but-set-variable)
warning-1 += $(call cc-disable-warning, missing-field-initializers)
-# Clang
-warning-1 += $(call cc-disable-warning, initializer-overrides)
-warning-1 += $(call cc-disable-warning, unused-value)
-warning-1 += $(call cc-disable-warning, format)
-warning-1 += $(call cc-disable-warning, unknown-warning-option)
-warning-1 += $(call cc-disable-warning, sign-compare)
-warning-1 += $(call cc-disable-warning, format-zero-length)
-warning-1 += $(call cc-disable-warning, uninitialized)
-warning-1 += $(call cc-option, -fcatch-undefined-behavior)
-
warning-2 := -Waggregate-return
warning-2 += -Wcast-align
warning-2 += -Wdisabled-optimization
# Will compile qconf as a C++ program, and menu as a C program.
# They are linked as C++ code to the executable qconf
-# hostprogs-y := conf
-# conf-objs := conf.o libkconfig.so
-# libkconfig-objs := expr.o type.o
-# Will create a shared library named libkconfig.so that consists of
-# expr.o and type.o (they are both compiled as C code and the object files
-# are made as position independent code).
-# conf.c is compiled as a C program, and conf.o is linked together with
-# libkconfig.so as the executable conf.
-# Note: Shared libraries consisting of C++ files are not supported
-
__hostprogs := $(sort $(hostprogs-y) $(hostprogs-m))
# C code
# Executables compiled from a single .c file
-host-csingle := $(foreach m,$(__hostprogs),$(if $($(m)-objs),,$(m)))
+host-csingle := $(foreach m,$(__hostprogs), \
+ $(if $($(m)-objs)$($(m)-cxxobjs),,$(m)))
# C executables linked based on several .o files
host-cmulti := $(foreach m,$(__hostprogs),\
host-cobjs := $(sort $(foreach m,$(__hostprogs),$($(m)-objs)))
# C++ code
-# C++ executables compiled from at least on .cc file
+# C++ executables compiled from at least one .cc file
# and zero or more .c files
host-cxxmulti := $(foreach m,$(__hostprogs),$(if $($(m)-cxxobjs),$(m)))
# C++ Object (.o) files compiled from .cc files
host-cxxobjs := $(sort $(foreach m,$(host-cxxmulti),$($(m)-cxxobjs)))
-# Shared libaries (only .c supported)
-# Shared libraries (.so) - all .so files referenced in "xxx-objs"
-host-cshlib := $(sort $(filter %.so, $(host-cobjs)))
-# Remove .so files from "xxx-objs"
-host-cobjs := $(filter-out %.so,$(host-cobjs))
-
-#Object (.o) files used by the shared libaries
-host-cshobjs := $(sort $(foreach m,$(host-cshlib),$($(m:.so=-objs))))
-
# output directory for programs/.o files
-# hostprogs-y := tools/build may have been specified. Retrieve directory
-host-objdirs := $(foreach f,$(__hostprogs), $(if $(dir $(f)),$(dir $(f))))
-# directory of .o files from prog-objs notation
-host-objdirs += $(foreach f,$(host-cmulti), \
- $(foreach m,$($(f)-objs), \
- $(if $(dir $(m)),$(dir $(m)))))
-# directory of .o files from prog-cxxobjs notation
-host-objdirs += $(foreach f,$(host-cxxmulti), \
- $(foreach m,$($(f)-cxxobjs), \
- $(if $(dir $(m)),$(dir $(m)))))
+# hostprogs-y := tools/build may have been specified.
+# Retrieve also directory of .o files from prog-objs or prog-cxxobjs notation
+host-objdirs := $(dir $(__hostprogs) $(host-cobjs) $(host-cxxobjs))
host-objdirs := $(strip $(sort $(filter-out ./,$(host-objdirs))))
host-cobjs := $(addprefix $(obj)/,$(host-cobjs))
host-cxxmulti := $(addprefix $(obj)/,$(host-cxxmulti))
host-cxxobjs := $(addprefix $(obj)/,$(host-cxxobjs))
-host-cshlib := $(addprefix $(obj)/,$(host-cshlib))
-host-cshobjs := $(addprefix $(obj)/,$(host-cshobjs))
host-objdirs := $(addprefix $(obj)/,$(host-objdirs))
obj-dirs += $(host-objdirs)
cmd_host-cmulti = $(HOSTCC) $(HOSTLDFLAGS) -o $@ \
$(addprefix $(obj)/,$($(@F)-objs)) \
$(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
-$(host-cmulti): $(obj)/%: $(host-cobjs) $(host-cshlib) FORCE
+$(host-cmulti): FORCE
$(call if_changed,host-cmulti)
+$(call multi_depend, $(host-cmulti), , -objs)
# Create .o file from a single .c file
# host-cobjs -> .o
$(foreach o,objs cxxobjs,\
$(addprefix $(obj)/,$($(@F)-$(o)))) \
$(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
-$(host-cxxmulti): $(obj)/%: $(host-cobjs) $(host-cxxobjs) $(host-cshlib) FORCE
+$(host-cxxmulti): FORCE
$(call if_changed,host-cxxmulti)
+$(call multi_depend, $(host-cxxmulti), , -objs -cxxobjs)
# Create .o file from a single .cc (C++) file
quiet_cmd_host-cxxobjs = HOSTCXX $@
$(host-cxxobjs): $(obj)/%.o: $(src)/%.cc FORCE
$(call if_changed_dep,host-cxxobjs)
-# Compile .c file, create position independent .o file
-# host-cshobjs -> .o
-quiet_cmd_host-cshobjs = HOSTCC -fPIC $@
- cmd_host-cshobjs = $(HOSTCC) $(hostc_flags) -fPIC -c -o $@ $<
-$(host-cshobjs): $(obj)/%.o: $(src)/%.c FORCE
- $(call if_changed_dep,host-cshobjs)
-
-# Link a shared library, based on position independent .o files
-# *.o -> .so shared library (host-cshlib)
-quiet_cmd_host-cshlib = HOSTLLD -shared $@
- cmd_host-cshlib = $(HOSTCC) $(HOSTLDFLAGS) -shared -o $@ \
- $(addprefix $(obj)/,$($(@F:.so=-objs))) \
- $(HOST_LOADLIBES) $(HOSTLOADLIBES_$(@F))
-$(host-cshlib): $(obj)/%: $(host-cshobjs) FORCE
- $(call if_changed,host-cshlib)
-
targets += $(host-csingle) $(host-cmulti) $(host-cobjs)\
- $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs)
+ $(host-cxxmulti) $(host-cxxobjs)
modname-multi = $(sort $(foreach m,$(multi-used),\
$(if $(filter $(subst $(obj)/,,$*.o), $($(m:.o=-objs)) $($(m:.o=-y))),$(m:.o=))))
+# Useful for describing the dependency of composite objects
+# Usage:
+# $(call multi_depend, multi_used_targets, suffix_to_remove, suffix_to_add)
+define multi_depend
+$(foreach m, $(notdir $1), \
+ $(eval $(obj)/$m: \
+ $(addprefix $(obj)/, $(foreach s, $3, $($(m:%$(strip $2)=%$(s)))))))
+endef
+
ifdef REGENERATE_PARSERS
# GPERF
%_defconfig: $(obj)/conf
$(Q)$< --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig)
+configfiles=$(wildcard $(srctree)/kernel/configs/$(1).config $(srctree)/arch/$(SRCARCH)/configs/$(1).config)
+
+define mergeconfig
+$(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target))
+$(if $(call configfiles,$(1)),, $(error No configuration exists for this target on this architecture))
+$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config $(call configfiles,$(1))
+$(Q)yes "" | $(MAKE) -f $(srctree)/Makefile oldconfig
+endef
+
+PHONY += kvmconfig
+kvmconfig:
+ $(call mergeconfig,kvm_guest)
+
+PHONY += tinyconfig
+tinyconfig: allnoconfig
+ $(call mergeconfig,tiny)
+
# Help text used by make help
help:
@echo ' config - Update current config utilising a line-oriented program'
@echo ' randconfig - New config with random answer to all options'
@echo ' listnewconfig - List new options'
@echo ' olddefconfig - Same as silentoldconfig but sets new symbols to their default value'
+# @echo ' kvmconfig - Enable additional options for guest kernel support'
+# @echo ' tinyconfig - Configure the tiniest possible kernel'
# lxdialog stuff
check-lxdialog := $(srctree)/$(src)/lxdialog/check-lxdialog.sh
qconf-objs := zconf.tab.o
gconf-objs := gconf.o zconf.tab.o
-hostprogs-y := conf
-
-ifeq ($(MAKECMDGOALS),nconfig)
- hostprogs-y += nconf
-endif
-
-ifeq ($(MAKECMDGOALS),menuconfig)
- hostprogs-y += mconf
-endif
-
-ifeq ($(MAKECMDGOALS),update-po-config)
- hostprogs-y += kxgettext
-endif
-
-ifeq ($(MAKECMDGOALS),xconfig)
- qconf-target := 1
-endif
-ifeq ($(MAKECMDGOALS),gconfig)
- gconf-target := 1
-endif
-
-
-ifeq ($(qconf-target),1)
- hostprogs-y += qconf
-endif
-
-ifeq ($(gconf-target),1)
- hostprogs-y += gconf
-endif
+hostprogs-y := conf nconf mconf kxgettext qconf gconf
clean-files := qconf.moc .tmp_qtcheck .tmp_gtkcheck
clean-files += zconf.tab.c zconf.lex.c zconf.hash.c gconf.glade.h
-clean-files += mconf qconf gconf nconf
clean-files += config.pot linux.pot
# Check that we have the required ncurses stuff installed for lxdialog (menuconfig)
HOSTLOADLIBES_mconf = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))
HOSTLOADLIBES_nconf = $(shell \
- pkg-config --libs menu panel ncurses 2>/dev/null \
+ pkg-config --libs menuw panelw ncursesw 2>/dev/null \
+ || pkg-config --libs menu panel ncurses 2>/dev/null \
|| echo "-lmenu -lpanel -lncurses" )
$(obj)/qconf.o: $(obj)/.tmp_qtcheck
-ifeq ($(qconf-target),1)
+ifeq ($(MAKECMDGOALS),xconfig)
$(obj)/.tmp_qtcheck: $(src)/Makefile
-include $(obj)/.tmp_qtcheck
$(obj)/gconf.o: $(obj)/.tmp_gtkcheck
-ifeq ($(gconf-target),1)
+ifeq ($(MAKECMDGOALS),gconfig)
-include $(obj)/.tmp_gtkcheck
# GTK needs some extra effort, too...
/* item list manipulation for lxdialog use */
#define MAXITEMSTR 200
struct dialog_item {
- char str[MAXITEMSTR]; /* promtp displayed */
+ char str[MAXITEMSTR]; /* prompt displayed */
char tag;
void *data; /* pointer to menu item - used by menubox+checklist */
int selected; /* Set to 1 by dialog_*() function if selected. */
sub dump_function($$) {
my $prototype = shift;
my $file = shift;
+ my $noret = 0;
$prototype =~ s/^static +//;
$prototype =~ s/^extern +//;
$prototype =~ s/^noinline +//;
$prototype =~ s/__init +//;
$prototype =~ s/__init_or_module +//;
+ $prototype =~ s/__meminit +//;
$prototype =~ s/__must_check +//;
$prototype =~ s/__weak +//;
- $prototype =~ s/^#\s*define\s+//; #ak added
+ my $define = $prototype =~ s/^#\s*define\s+//; #ak added
$prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//;
# Yes, this truly is vile. We are looking for:
# - atomic_set (macro)
# - pci_match_device, __copy_to_user (long return type)
- if ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ if ($define && $prototype =~ m/^()([a-zA-Z0-9_~:]+)\s+/) {
+ # This is an object-like macro, it has no return type and no parameter
+ # list.
+ # Function-like macros are not allowed to have spaces between
+ # declaration_name and opening parenthesis (notice the \s+).
+ $return_type = $1;
+ $declaration_name = $2;
+ $noret = 1;
+ } elsif ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
$prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
$prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
$prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
# of warnings goes sufficiently down, the check is only performed in
# verbose mode.
# TODO: always perform the check.
- if ($verbose) {
+ if ($verbose && !$noret) {
check_return_section($file, $declaration_name, $return_type);
}
fi
}
+do_board_felconfig () {
+ do_board_defconfig ${1%%_felconfig}_defconfig
+ if ! grep -q CONFIG_ARCH_SUNXI=y .config || ! grep -q CONFIG_SPL=y .config ; then
+ echo "$progname: Cannot felconfig a non-sunxi or non-SPL platform" >&2
+ exit 1
+ fi
+ sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y/g' \
+ .config spl/.config
+}
+
do_savedefconfig () {
if [ -r "$KCONFIG_CONFIG" ]; then
subimages=$(get_enabled_subimages)
case $target in
*_defconfig)
do_board_defconfig $target;;
+*_felconfig)
+ do_board_felconfig $target;;
*_config)
# backward compatibility
do_board_defconfig ${target%_config}_defconfig;;
#endif
#endif
+ assert(run_command("", 0) == 0);
+ assert(run_command(" ", 0) == 0);
+
+ assert(run_command("'", 0) == 1);
+
printf("%s: Everything went swimmingly\n", __func__);
return 0;
}
#HOSTCFLAGS_mpc86x_clk.o := -pedantic
quiet_cmd_wrap = WRAP $@
-cmd_wrap = echo "\#include <$(srctree)/$(patsubst $(obj)/%,%,$@)>" >$@
+cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@
$(obj)/lib/%.c $(obj)/common/%.c:
$(call cmd,wrap)
#endif
static inline ulong getenvsize (void)
{
- ulong rc = CUR_ENVSIZE - sizeof(long);
+ ulong rc = CUR_ENVSIZE - sizeof(uint32_t);
if (HaveRedundEnv)
rc -= sizeof (char);
*
* The remaining fraction of a block bytes would not be loaded!
*/
- *header_size_ptr = ROUND(sbuf->st_size, 4096);
+ *header_size_ptr = ROUND((sbuf->st_size + imximage_ivt_offset), 4096);
if (csf_ptr && imximage_csf_size) {
*csf_ptr = params->ep - imximage_init_loadsize +
*/
#include "imagetool.h"
+#include <limits.h>
#include <image.h>
#include <stdint.h>
#include "kwbimage.h"
main_hdr = image;
/* Fill in the main header */
- main_hdr->blocksize = payloadsz + sizeof(uint32_t);
+ main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz;
main_hdr->srcaddr = headersz;
main_hdr->ext = has_ext;
main_hdr->destaddr = params->addr;
ret = stat(binarye->binary.file, &s);
if (ret < 0) {
- char *cwd = get_current_dir_name();
+ char cwd[PATH_MAX];
+ char *dir = cwd;
+
+ memset(cwd, 0, sizeof(cwd));
+ if (!getcwd(cwd, sizeof(cwd))) {
+ dir = "current working directory";
+ perror("getcwd() failed");
+ }
+
fprintf(stderr,
"Didn't find the file '%s' in '%s' which is mandatory to generate the image\n"
"This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n"
"image for your board. See 'kwbimage -x' to extract it from an existing image.\n",
- binarye->binary.file, cwd);
- free(cwd);
+ binarye->binary.file, dir);
return 0;
}
}
version = image_get_version();
- /* Fallback to version 0 is no version is provided in the cfg file */
- if (version == -1)
- version = 0;
-
- if (version == 0)
+ switch (version) {
+ /*
+ * Fallback to version 0 if no version is provided in the
+ * cfg file
+ */
+ case -1:
+ case 0:
image = image_create_v0(&headersz, params, sbuf->st_size);
- else if (version == 1)
+ break;
+
+ case 1:
image = image_create_v1(&headersz, params, sbuf->st_size);
+ break;
+
+ default:
+ fprintf(stderr, "Unsupported version %d\n", version);
+ free(image_cfg);
+ exit(EXIT_FAILURE);
+ }
if (!image) {
fprintf(stderr, "Could not create image\n");
printf("Image Type: MVEBU Boot from %s Image\n",
image_boot_mode_name(mhdr->blockid));
- printf("Data Size: ");
printf("Image version:%d\n", image_version((void *)ptr));
+ printf("Data Size: ");
genimg_print_size(mhdr->blocksize - sizeof(uint32_t));
printf("Load Address: %08x\n", mhdr->destaddr);
printf("Entry Point: %08x\n", mhdr->execaddr);
main_hdr = (void *)ptr;
checksum = image_checksum8(ptr,
- sizeof(struct main_hdr_v0));
+ sizeof(struct main_hdr_v0)
+ - sizeof(uint8_t));
if (checksum != main_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
if (image_version((void *)ptr) == 0) {
ext_hdr = (void *)ptr + sizeof(struct main_hdr_v0);
checksum = image_checksum8(ext_hdr,
- sizeof(struct ext_hdr_v0));
+ sizeof(struct ext_hdr_v0)
+ - sizeof(uint8_t));
if (checksum != ext_hdr->checksum)
return -FDT_ERR_BADSTRUCTURE;
}
"\t\tkey1=value1\n"
"\t\tkey2=value2\n"
"\t\t...\n"
+ "\tEmpty lines are skipped, and lines with a # in the first\n"
+ "\tcolumn are treated as comments (also skipped).\n"
"\t-r : the environment has multiple copies in flash\n"
"\t-b : the target is big endian (default is little endian)\n"
"\t-p <byte> : fill the image with <byte> bytes instead of 0xff bytes\n"
/* Replace newlines separating variables with \0 */
for (fp = 0, ep = 0 ; fp < filesize ; fp++) {
if (filebuf[fp] == '\n') {
- if (ep == 0) {
+ if (fp == 0 || filebuf[fp-1] == '\n') {
/*
- * Newlines at the beginning of the file ?
- * Ignore them.
+ * Skip empty lines.
*/
continue;
} else if (filebuf[fp-1] == '\\') {
/* End of a variable */
envptr[ep++] = '\0';
}
+ } else if ((fp == 0 || filebuf[fp-1] == '\n') && filebuf[fp] == '#') {
+ /* Comment, skip the line. */
+ while (++fp < filesize && filebuf[fp] != '\n')
+ continue;
} else {
envptr[ep++] = filebuf[fp];
}
projects / karo-tx-uboot.git / commitdiff