]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
drm/i915: change VLV IOSF sideband accessors to not return error code
authorJani Nikula <jani.nikula@intel.com>
Wed, 22 May 2013 12:36:20 +0000 (15:36 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 23 May 2013 21:25:42 +0000 (23:25 +0200)
We never check the return values, and there's not much we could do on
errors anyway. Just simplify the signatures. No functional changes.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_sysfs.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_sideband.c

index bc0f6a55c74ba6cd30e05ad51111b082fbba5594..2eb572afbcd37219d6e730d4aa1ebe74b9f90686 100644 (file)
@@ -1137,16 +1137,15 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
                u32 freq_sts, val;
 
                mutex_lock(&dev_priv->rps.hw_lock);
-               vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS,
-                                     &freq_sts);
+               freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
                seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
                seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
 
-               vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1, &val);
+               val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1);
                seq_printf(m, "max GPU freq: %d MHz\n",
                           vlv_gpu_freq(dev_priv->mem_freq, val));
 
-               vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
+               val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM);
                seq_printf(m, "min GPU freq: %d MHz\n",
                           vlv_gpu_freq(dev_priv->mem_freq, val));
 
index 28d14d6cf4cc872573b4756ef9d3d07f0c65eecb..f6419f40df382f4d0ee5c909b6e248de8db983d8 100644 (file)
@@ -1931,9 +1931,9 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
 
 /* intel_sideband.c */
-int vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
-int vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
-int vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val);
+u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
+void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
+u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
index 588fa00e693880af520bd06df96be72a38fcdd64..6875b5654c63d55a65dcf639734e0de101f1f037 100644 (file)
@@ -214,7 +214,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
        mutex_lock(&dev_priv->rps.hw_lock);
        if (IS_VALLEYVIEW(dev_priv->dev)) {
                u32 freq;
-               vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &freq);
+               freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
                ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff);
        } else {
                ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
index 52f1b39148c0ab5684793772955449ff9b1ba25e..fa4c818d4b009e65be2b1e579ca73371acc30120 100644 (file)
@@ -2569,7 +2569,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
        vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
 
        do {
-               vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+               pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
                if (time_after(jiffies, timeout)) {
                        DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
                        break;
@@ -2577,7 +2577,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
                udelay(10);
        } while (pval & 1);
 
-       vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
+       pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
        if ((pval >> 8) != val)
                DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
                          val, pval >> 8);
@@ -2882,7 +2882,7 @@ int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
 {
        u32 val, rp0;
 
-       vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
+       val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
 
        rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
        /* Clamp to max */
@@ -2895,9 +2895,9 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
 {
        u32 val, rpe;
 
-       vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
+       val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
        rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
-       vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
+       val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
        rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
 
        return rpe;
@@ -2905,11 +2905,7 @@ static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
 
 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
 {
-       u32 val;
-
-       vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
-
-       return val & 0xff;
+       return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
 }
 
 static void vlv_rps_timer_work(struct work_struct *work)
@@ -3018,7 +3014,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
        I915_WRITE(GEN6_RC_CONTROL,
                   GEN7_RC_CTL_TO_MODE);
 
-       vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
+       val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
        switch ((val >> 6) & 3) {
        case 0:
        case 1:
index d150972da04865ae99e5319d94ac3188a13c806d..9a0e6c5ea540544f10aa719a9c1fea6cbab82eb0 100644 (file)
@@ -63,46 +63,42 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
        return 0;
 }
 
-int vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
 {
-       int ret;
+       u32 val = 0;
 
        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 
        mutex_lock(&dev_priv->dpio_lock);
-       ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
-                             PUNIT_OPCODE_REG_READ, addr, val);
+       vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
+                       PUNIT_OPCODE_REG_READ, addr, &val);
        mutex_unlock(&dev_priv->dpio_lock);
 
-       return ret;
+       return val;
 }
 
-int vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
+void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
 {
-       int ret;
-
        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 
        mutex_lock(&dev_priv->dpio_lock);
-       ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
-                             PUNIT_OPCODE_REG_WRITE, addr, &val);
+       vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
+                       PUNIT_OPCODE_REG_WRITE, addr, &val);
        mutex_unlock(&dev_priv->dpio_lock);
-
-       return ret;
 }
 
-int vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
+u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
 {
-       int ret;
+       u32 val = 0;
 
        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
 
        mutex_lock(&dev_priv->dpio_lock);
-       ret = vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
-                             PUNIT_OPCODE_REG_READ, addr, val);
+       vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
+                       PUNIT_OPCODE_REG_READ, addr, &val);
        mutex_unlock(&dev_priv->dpio_lock);
 
-       return ret;
+       return val;
 }
 
 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg)