]> git.kernelconcepts.de Git - karo-tx-linux.git/commitdiff
bnx2x: correct LPI pass-through configuration
authorYuval Mintz <yuvalmin@broadcom.com>
Sun, 17 Jun 2012 02:04:50 +0000 (02:04 +0000)
committerDavid S. Miller <davem@davemloft.net>
Sun, 17 Jun 2012 23:16:51 +0000 (16:16 -0700)
Commit c8c60d88c59cbb48737732ba948663a3efe882aa contained
an incorrect logic which enabled a buffer overflow when accessing
an array during LPI pass-through configuration.
This patch fixes this issue by removing that logic altogether.

Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com>
Signed-off-by: Yaniv Rosner <yaniv.rosner@broadcom.com>
Signed-off-by: Eilon Greenstein <eilong@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

index c7c814db027da01df111ffac5e278a9ffe11d30b..91aa565d437490536dfb4d9411b84392b7061df4 100644 (file)
@@ -4057,18 +4057,12 @@ static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
                         MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
 
        /* Enable LPI pass through */
-       if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
-           (phy->flags & FLAGS_EEE_10GBT) &&
-           (!(params->eee_mode & EEE_MODE_ENABLE_LPI) ||
-             bnx2x_eee_calc_timer(params)) &&
-           (params->req_duplex[bnx2x_phy_selection(params)] == DUPLEX_FULL)) {
-               DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
-               bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
-                                MDIO_WC_REG_EEE_COMBO_CONTROL0,
-                                0x7c);
-               bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
-                                        MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
-       }
+       DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
+       bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
+                        MDIO_WC_REG_EEE_COMBO_CONTROL0,
+                        0x7c);
+       bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
+                                MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
 
        /* 10G XFI Full Duplex */
        bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,