sh, perf: Use common PMU interrupt disabled code

Transition to using the new generic PERF_PMU_CAP_NO_INTERRUPT method for
failing a sampling event when no PMU interrupt is available.

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: linux-sh@vger.kernel.org
Link: http://lkml.kernel.org/r/alpine.DEB.2.10.1406150205300.16738@vincent-weaver-1.umelst.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/sh/kernel/perf_event.c b/arch/sh/kernel/perf_event.c
index 02331672b6db985f22d8452a30e7d6dbf013b840..7cfd7f153966719c9201a66ff6043c3e48a47a93 100644 (file)
--- a/arch/sh/kernel/perf_event.c
+++ b/arch/sh/kernel/perf_event.c
@@ -128,14 +128,6 @@ static int __hw_perf_event_init(struct perf_event *event)
        if (!sh_pmu_initialized())
                return -ENODEV;
 
-       /*
-        * All of the on-chip counters are "limited", in that they have
-        * no interrupts, and are therefore unable to do sampling without
-        * further work and timer assistance.
-        */
-       if (hwc->sample_period)
-               return -EINVAL;
-
        /*
         * See if we need to reserve the counter.
         *
@@ -392,6 +384,13 @@ int register_sh_pmu(struct sh_pmu *_pmu)
 
        pr_info("Performance Events: %s support registered\n", _pmu->name);
 
+       /*
+        * All of the on-chip counters are "limited", in that they have
+        * no interrupts, and are therefore unable to do sampling without
+        * further work and timer assistance.
+        */
+       pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
+
        WARN_ON(_pmu->num_events > MAX_HWEVENTS);
 
        perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);