Merge branch 'perf/x86-ibs' into perf/core

diff --combined arch/x86/include/asm/msr-index.h
index ccb805966f68536d4e17710f2bce5cccfdf7f5aa,4e3cd382a06f94b0578640f896a7dbd69c7eba74..957ec87385afe0c5c53fbac8afac109e75c374d5
--- 1/arch/x86/include/asm/msr-index.h
--- 2/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@@ -56,13 -56,6 +56,13 @@@
  #define MSR_OFFCORE_RSP_0             0x000001a6
  #define MSR_OFFCORE_RSP_1             0x000001a7
  
 +#define MSR_LBR_SELECT                        0x000001c8
 +#define MSR_LBR_TOS                   0x000001c9
 +#define MSR_LBR_NHM_FROM              0x00000680
 +#define MSR_LBR_NHM_TO                        0x000006c0
 +#define MSR_LBR_CORE_FROM             0x00000040
 +#define MSR_LBR_CORE_TO                       0x00000060
 +
  #define MSR_IA32_PEBS_ENABLE          0x000003f1
  #define MSR_IA32_DS_AREA              0x00000600
  #define MSR_IA32_PERF_CAPABILITIES    0x00000345
@@@ -134,6 -127,8 +134,8 @@@
  #define MSR_AMD64_IBSFETCHCTL         0xc0011030
  #define MSR_AMD64_IBSFETCHLINAD               0xc0011031
  #define MSR_AMD64_IBSFETCHPHYSAD      0xc0011032
+ #define MSR_AMD64_IBSFETCH_REG_COUNT  3
+ #define MSR_AMD64_IBSFETCH_REG_MASK   ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
  #define MSR_AMD64_IBSOPCTL            0xc0011033
  #define MSR_AMD64_IBSOPRIP            0xc0011034
  #define MSR_AMD64_IBSOPDATA           0xc0011035
@@@ -141,8 -136,11 +143,11 @@@
  #define MSR_AMD64_IBSOPDATA3          0xc0011037
  #define MSR_AMD64_IBSDCLINAD          0xc0011038
  #define MSR_AMD64_IBSDCPHYSAD         0xc0011039
+ #define MSR_AMD64_IBSOP_REG_COUNT     7
+ #define MSR_AMD64_IBSOP_REG_MASK      ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
  #define MSR_AMD64_IBSCTL              0xc001103a
  #define MSR_AMD64_IBSBRTARGET         0xc001103b
+ #define MSR_AMD64_IBS_REG_COUNT_MAX   8 /* includes MSR_AMD64_IBSBRTARGET */
  
  /* Fam 15h MSRs */
  #define MSR_F15H_PERF_CTL             0xc0010200

diff --combined arch/x86/include/asm/perf_event.h
index 2291895b1836a4acf9b9313722fb670717f0d4c5,9cf66965141d342586c75071bfd32a6f18a1729a..8a3c75d824b7e966a922390b72903cf24ff43ca0
--- 1/arch/x86/include/asm/perf_event.h
--- 2/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@@ -23,7 -23,6 +23,7 @@@
  #define ARCH_PERFMON_EVENTSEL_USR                     (1ULL << 16)
  #define ARCH_PERFMON_EVENTSEL_OS                      (1ULL << 17)
  #define ARCH_PERFMON_EVENTSEL_EDGE                    (1ULL << 18)
 +#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL             (1ULL << 19)
  #define ARCH_PERFMON_EVENTSEL_INT                     (1ULL << 20)
  #define ARCH_PERFMON_EVENTSEL_ANY                     (1ULL << 21)
  #define ARCH_PERFMON_EVENTSEL_ENABLE                  (1ULL << 22)
@@@ -178,6 -177,8 +178,8 @@@ struct x86_pmu_capability 
  #define IBS_FETCH_MAX_CNT     0x0000FFFFULL
  
  /* IbsOpCtl bits */
+ /* lower 4 bits of the current count are ignored: */
+ #define IBS_OP_CUR_CNT                (0xFFFF0ULL<<32)
  #define IBS_OP_CNT_CTL                (1ULL<<19)
  #define IBS_OP_VAL            (1ULL<<18)
  #define IBS_OP_ENABLE         (1ULL<<17)