ARM: dts: berlin: Add BG2 ethernet DT nodes

Marvell BG2 has two fast ethernet controllers with internal PHY,
add the corresponding nodes to SoC dtsi.

Tested-by: Antoine Ténart <antoine.tenart@free-electrons.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index d7e81e124de07db4ba49677e0694cdb96db9ade6..bbdad9510f1998dde89927c5c3bd4cb51d0f5c53 100644 (file)
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -79,11 +79,47 @@
                        clocks = <&chip CLKID_TWD>;
                };
 
+               eth1: ethernet@b90000 {
+                       compatible = "marvell,pxa168-eth";
+                       reg = <0xb90000 0x10000>;
+                       clocks = <&chip CLKID_GETH1>;
+                       interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                       /* set by bootloader */
+                       local-mac-address = [00 00 00 00 00 00];
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       phy-connection-type = "mii";
+                       phy-handle = <&ethphy1>;
+                       status = "disabled";
+
+                       ethphy1: ethernet-phy@0 {
+                               reg = <0>;
+                       };
+               };
+
                cpu-ctrl@dd0000 {
                        compatible = "marvell,berlin-cpu-ctrl";
                        reg = <0xdd0000 0x10000>;
                };
 
+               eth0: ethernet@e50000 {
+                       compatible = "marvell,pxa168-eth";
+                       reg = <0xe50000 0x10000>;
+                       clocks = <&chip CLKID_GETH0>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       /* set by bootloader */
+                       local-mac-address = [00 00 00 00 00 00];
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       phy-connection-type = "mii";
+                       phy-handle = <&ethphy0>;
+                       status = "disabled";
+
+                       ethphy0: ethernet-phy@0 {
+                               reg = <0>;
+                       };
+               };
+
                apb@e80000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;