powerpc/8xx: Declare SPRG2 as a SCRATCH register

Since commit 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index bffd89d27301db29594688225eb83b1033f5d2e2..1ff8ba94b9f428486acd5674e72bbdcafbd8a7b2 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -950,7 +950,7 @@
  * 32-bit 8xx:
  *     - SPRG0 scratch for exception vectors
  *     - SPRG1 scratch for exception vectors
- *     - SPRG2 apparently unused but initialized
+ *     - SPRG2 scratch for exception vectors
  *
  */
 #ifdef CONFIG_PPC64
@@ -1060,6 +1060,7 @@
 #ifdef CONFIG_8xx
 #define SPRN_SPRG_SCRATCH0     SPRN_SPRG0
 #define SPRN_SPRG_SCRATCH1     SPRN_SPRG1
+#define SPRN_SPRG_SCRATCH2     SPRN_SPRG2
 #endif
 
 

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 7ee876d2adb57c6cc1e78d1d3204ab240238c02d..9db2e4491922700ad76eaaaf50422e94b3dfe7cc 100644 (file)
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -301,7 +301,7 @@ InstructionTLBMiss:
        stw     r11, 4(r0)
 #else
        mtspr   SPRN_DAR, r10
-       mtspr   SPRN_SPRG2, r11
+       mtspr   SPRN_SPRG_SCRATCH2, r11
 #endif
        mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
 #ifdef CONFIG_8xx_CPU15
@@ -363,7 +363,7 @@ InstructionTLBMiss:
        mfspr   r10, SPRN_DAR
        mtcr    r10
        mtspr   SPRN_DAR, r11   /* Tag DAR */
-       mfspr   r11, SPRN_SPRG2
+       mfspr   r11, SPRN_SPRG_SCRATCH2
 #else
        lwz     r11, 0(r0)
        mtcr    r11
@@ -386,7 +386,7 @@ InstructionTLBMiss:
        mtcr    r10
        li      r11, 0x00f0
        mtspr   SPRN_DAR, r11   /* Tag DAR */
-       mfspr   r11, SPRN_SPRG2
+       mfspr   r11, SPRN_SPRG_SCRATCH2
 #else
        lwz     r11, 0(r0)
        mtcr    r11
@@ -409,7 +409,7 @@ DataStoreTLBMiss:
        stw     r11, 4(r0)
 #else
        mtspr   SPRN_DAR, r10
-       mtspr   SPRN_SPRG2, r11
+       mtspr   SPRN_SPRG_SCRATCH2, r11
 #endif
        mfspr   r10, SPRN_M_TWB /* Get level 1 table entry address */
 
@@ -487,7 +487,7 @@ DataStoreTLBMiss:
        mfspr   r10, SPRN_DAR
        mtcr    r10
        mtspr   SPRN_DAR, r11   /* Tag DAR */
-       mfspr   r11, SPRN_SPRG2
+       mfspr   r11, SPRN_SPRG_SCRATCH2
 #else
        mtspr   SPRN_DAR, r11   /* Tag DAR */
        lwz     r11, 0(r0)