devconcenter PPC460EX
dlvision PPC405EP
+ dlvision-10g PPC405EP
gdppc440etx PPC440EP/GR
intip PPC460EX
io PPC405EP
# MA 02111-1307 USA
#
-CROSS_COMPILE ?= i386-linux-
-
STANDALONE_LOAD_ADDR = 0x40000
PLATFORM_CPPFLAGS += -fno-strict-aliasing
PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time))
PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector)
PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2)
-PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__
+PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
+PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
+
+PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
+
+PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
+
+LDFLAGS_u-boot += --gc-sections -pie
+LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
-LDFLAGS += --cref
-LDFLAGS_u-boot += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections
# MA 02111-1307 USA
#
-PLATFORM_RELFLAGS +=
+CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -march=i386 -Werror
+PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__ -march=i386 -Werror
+
+# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
+LDPPFLAGS += -DRESET_SEG_START=0xffff0000
+LDPPFLAGS += -DRESET_SEG_SIZE=0x10000
+LDPPFLAGS += -DRESET_VEC_LOC=0xfff0
+LDPPFLAGS += -DSTART_16=0xf800
#include <common.h>
#include <command.h>
+#include <asm/processor.h>
+#include <asm/processor-flags.h>
#include <asm/interrupt.h>
/* Constructor for a conventional segment GDT (or LDT) entry */
(((base) & 0x00ffffffULL) << 16) | \
(((limit) & 0x0000ffffULL)))
-/* Simple and small GDT entries for booting only */
-
-#define GDT_ENTRY_32BIT_CS 2
-#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1)
-#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1)
-#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1)
-
/*
* Set up the GDT
*/
}
-int cpu_init_f(void)
+int x86_cpu_init_f(void)
{
+ const u32 em_rst = ~X86_CR0_EM;
+ const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
+
/* initialize FPU, reset EM, set MP and NE */
asm ("fninit\n" \
- "movl %cr0, %eax\n" \
- "andl $~0x4, %eax\n" \
- "orl $0x22, %eax\n" \
- "movl %eax, %cr0\n" );
+ "movl %%cr0, %%eax\n" \
+ "andl %0, %%eax\n" \
+ "orl %1, %%eax\n" \
+ "movl %%eax, %%cr0\n" \
+ : : "i" (em_rst), "i" (mp_ne_set) : "eax");
return 0;
}
+int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
-int cpu_init_r(void)
+int x86_cpu_init_r(void)
{
+ const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
+
+ /* turn on the cache and disable write through */
+ asm("movl %%cr0, %%eax\n"
+ "andl %0, %%eax\n"
+ "movl %%eax, %%cr0\n"
+ "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+
reload_gdt();
/* Initialize core interrupt and exception functionality of CPU */
cpu_init_interrupts ();
return 0;
}
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#include <common.h>
#include <asm/interrupt.h>
+#include <asm/io.h>
+#include <asm/processor-flags.h>
#define DECLARE_INTERRUPT(x) \
".globl irq_"#x"\n" \
{
unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
unsigned long d0, d1, d2, d3, d6, d7;
+ unsigned long sp;
printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
(u16)regs->xcs, regs->eip, regs->eflags);
d7 = get_debugreg(7);
printf("DR6: %08lx DR7: %08lx\n",
d6, d7);
+
+ printf("Stack:\n");
+ sp = regs->esp;
+
+ sp += 64;
+
+ while (sp > (regs->esp - 16)) {
+ if (sp == regs->esp)
+ printf("--->");
+ else
+ printf(" ");
+ printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
+ sp -= 4;
+ }
}
struct idt_entry {
asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
- return (flags&0x200); /* IE flags is bit 9 */
+ return flags & X86_EFLAGS_IF; /* IE flags is bit 9 */
}
/* IRQ Low-Level Service Routine */
LIB := $(obj)lib$(SOC).o
COBJS-$(CONFIG_SYS_SC520) += sc520.o
+COBJS-$(CONFIG_PCI) += sc520_pci.o
+COBJS-$(CONFIG_SYS_SC520) += sc520_sdram.o
COBJS-$(CONFIG_SYS_SC520_SSI) += sc520_ssi.o
COBJS-$(CONFIG_SYS_SC520_TIMER) += sc520_timer.o
-COBJS-$(CONFIG_PCI) += sc520_pci.o
-SOBJS-$(CONFIG_SYS_SC520) += sc520_asm.o
+SOBJS-$(CONFIG_SYS_SC520) += sc520_car.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
/*
* (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ * Daniel Engstr�m, Omicron Ceti AB <daniel@omicron.se>.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <common.h>
#include <asm/io.h>
+#include <asm/processor-flags.h>
#include <asm/ic/sc520.h>
DECLARE_GLOBAL_DATA_PTR;
-/*
- * utility functions for boards based on the AMD sc520
- *
- * void init_sc520(void)
- * unsigned long init_sc520_dram(void)
- */
+sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
-volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
-
-void init_sc520(void)
+int cpu_init_f(void)
{
- /*
- * Set the UARTxCTL register at it's slower,
- * baud clock giving us a 1.8432 MHz reference
- */
- writeb(0x07, &sc520_mmcr->uart1ctl);
- writeb(0x07, &sc520_mmcr->uart2ctl);
-
- /* first set the timer pin mapping */
- writeb(0x72, &sc520_mmcr->clksel); /* no clock frequency selected, use 1.1892MHz */
-
- /* enable PCI bus arbiter (concurrent mode) */
- writeb(0x02, &sc520_mmcr->sysarbctl);
-
- /* enable external grants */
- writeb(0x1f, &sc520_mmcr->sysarbmenb);
-
- /* enable posted-writes */
- writeb(0x04, &sc520_mmcr->hbctl);
-
if (CONFIG_SYS_SC520_HIGH_SPEED) {
/* set it to 133 MHz and write back */
writeb(0x02, &sc520_mmcr->cpuctl);
gd->cpu_clk = 133000000;
- printf("## CPU Speed set to 133MHz\n");
} else {
/* set it to 100 MHz and write back */
writeb(0x01, &sc520_mmcr->cpuctl);
- printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000;
}
-
/* wait at least one millisecond */
asm("movl $0x2000, %%ecx\n"
"0: pushl %%ecx\n"
"popl %%ecx\n"
"loop 0b\n": : : "ecx");
- /* turn on the SDRAM write buffer */
- writeb(0x11, &sc520_mmcr->dbctl);
-
- /* turn on the cache and disable write through */
- asm("movl %%cr0, %%eax\n"
- "andl $0x9fffffff, %%eax\n"
- "movl %%eax, %%cr0\n" : : : "eax");
+ return x86_cpu_init_f();
}
-unsigned long init_sc520_dram(void)
+int cpu_init_r(void)
{
- bd_t *bd = gd->bd;
-
- u32 dram_present=0;
- u32 dram_ctrl;
-
-#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
- /* these memory control registers are set up in the assember part,
- * in sc520_asm.S, during 'mem_init'. If we muck with them here,
- * after we are running a stack in RAM, we have troubles. Besides,
- * these refresh and delay values are better ? simply specified
- * outright in the include/configs/{cfg} file since the HW designer
- * simply dictates it.
- */
-#else
- u8 tmp;
- u8 val;
-
- int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
- int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
- int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
-
- /* set SDRAM speed here */
-
- refresh_rate /= 78;
- if (refresh_rate <= 1) {
- val = 0; /* 7.8us */
- } else if (refresh_rate == 2) {
- val = 1; /* 15.6us */
- } else if (refresh_rate == 3 || refresh_rate == 4) {
- val = 2; /* 31.2us */
- } else {
- val = 3; /* 62.4us */
- }
-
- tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);
- writeb(tmp, &sc520_mmcr->drcctl);
+ /* Disable the PAR used for CAR */
+ writel(0x0000000, &sc520_mmcr->par[2]);
- val = readb(&sc520_mmcr->drctmctl) & 0xf0;
-
- if (cas_precharge_delay==3) {
- val |= 0x04; /* 3T */
- } else if (cas_precharge_delay==4) {
- val |= 0x08; /* 4T */
- } else if (cas_precharge_delay>4) {
- val |= 0x0c;
- }
-
- if (ras_cas_delay > 3) {
- val |= 2;
- } else {
- val |= 1;
- }
- writeb(val, &c520_mmcr->drctmctl);
-#endif
-
- /*
- * We read-back the configuration of the dram
- * controller that the assembly code wrote
- */
- dram_ctrl = readl(&sc520_mmcr->drcbendadr);
-
- bd->bi_dram[0].start = 0;
- if (dram_ctrl & 0x80) {
- /* bank 0 enabled */
- dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
- bd->bi_dram[0].size = bd->bi_dram[1].start;
- } else {
- bd->bi_dram[0].size = 0;
- bd->bi_dram[1].start = bd->bi_dram[0].start;
- }
-
- if (dram_ctrl & 0x8000) {
- /* bank 1 enabled */
- dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
- bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
- } else {
- bd->bi_dram[1].size = 0;
- bd->bi_dram[2].start = bd->bi_dram[1].start;
- }
-
- if (dram_ctrl & 0x800000) {
- /* bank 2 enabled */
- dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
- bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
- } else {
- bd->bi_dram[2].size = 0;
- bd->bi_dram[3].start = bd->bi_dram[2].start;
- }
-
- if (dram_ctrl & 0x80000000) {
- /* bank 3 enabled */
- dram_present = (dram_ctrl & 0x7f000000) >> 2;
- bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
- } else {
- bd->bi_dram[3].size = 0;
- }
- gd->ram_size = dram_present;
+ /* turn on the SDRAM write buffer */
+ writeb(0x11, &sc520_mmcr->dbctl);
- return dram_present;
+ return x86_cpu_init_r();
}
#ifdef CONFIG_SYS_SC520_RESET
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* This file is largely based on code obtned from AMD. AMD's original
- * copyright is included below
- */
-
-/* TITLE SIZER - Aspen DRAM Sizing Routine.
- * =============================================================================
- *
- * Copyright 1999 Advanced Micro Devices, Inc.
- * You may redistribute this program and/or modify this program under the terms
- * of the GNU General Public License as published by the Free Software Foundation;
- * either version 2 of the License, or (at your option) any later version.
- *
- * This program is distributed WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
- * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
- *
- * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
- * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
- * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
- * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
- * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
- * INTERRUPTION, LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY
- * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
- * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
- * LIMITATION MAY NOT APPLY TO YOU.
- *
- * AMD does not assume any responsibility for any errors that may appear in
- * the Materials nor any responsibility to support or update the Materials.
- * AMD retains the right to make changes to its test specifications at any
- * time, without notice.
- * ==============================================================================
- */
-
-/*
- ******************************************************************************
- *
- * FILE : sizer.asm - SDRAM DIMM Sizing Algorithm
- *
- *
- *
- * FUNCTIONS : sizemem() - jumped to, not called. To be executed after
- * reset to determine the size of the SDRAM DIMMs. Initializes
- * the memory subsystem.
- *
- *
- * AUTHOR : Buddy Fey - Original.
- *
- *
- * DESCRIPTION : Performs sizing on SDRAM DIMMs on ASPEN processor.
- * NOTE: This is a small memory model version
- *
- *
- * INPUTS : BP contains return address offset
- * CACHE is assumed to be disabled.
- * The FS segment limit has already been set to big real mode
- * (full 32-bit addressing capability)
- *
- *
- * OUTPUTS : None
- *
- *
- * REG USE : ax,bx,cx,dx,di,si,bp, fs
- *
- *
- * REVISION : See PVCS info below
- *
- *
- * TEST PLAN CROSS REFERENCE:
- *
- *
- * $Workfile: $
- * $Revision: 1.2 $
- * $Date: 1999/09/22 12:49:33 $
- * $Author: chipf $
- * $Log: sizer.asm $
- * Revision 1.2 1999/09/22 12:49:33 chipf
- * Add legal header
- *
- *******************************************************************************
- */
-
-
-/*******************************************************************************
- * FUNCTIONAL DESCRIPTION:
- * This routine is called to autodetect the geometry of the DRAM.
- *
- * This routine is called to determine the number of column bits for the DRAM
- * devices in this external bank. This routine assumes that the external bank
- * has been configured for an 11-bit column and for 4 internal banks. This gives
- * us the maximum address reach in memory. By writing a test value to the max
- * address and locating where it aliases to, we can determine the number of valid
- * column bits.
- *
- * This routine is called to determine the number of internal banks each DRAM
- * device has. The external bank (under test) is configured for maximum reach
- * with 11-bit columns and 4 internal banks. This routine will write to a max
- * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if
- * that column is a "don't care". If BA1 does not affect write/read of data,
- * then this device has only 2 internal banks.
- *
- * This routine is called to determine the ending address for this external
- * bank of SDRAM. We write to a max address with a data value and then disable
- * row address bits looking for "don't care" locations. Each "don't care" bit
- * represents a dividing of the maximum density (128M) by 2. By dividing the
- * maximum of 32 4M chunks in an external bank down by all the "don't care" bits
- * determined during sizing, we set the proper density.
- *
- * WARNINGS.
- * bp must be preserved because it is used for return linkage.
- *
- * EXIT
- * nothing returned - but the memory subsystem is enabled
- *******************************************************************************
- */
-
-#include <config.h>
-
-.section .text
-.equ DRCCTL, 0x0fffef010 /* DRAM control register */
-.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */
-.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
-.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
-.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
-.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
-.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
-
-.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
-.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */
-.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */
-.equ COL09_ADR, 0x0e000600 /* 9 col addrs */
-.equ COL08_ADR, 0x0e000200 /* 8 col addrs */
-.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */
-.equ ROW13_ADR, 0x07000000 /* 13 row addrs */
-.equ ROW12_ADR, 0x03000000 /* 12 row addrs */
-.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */
-.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */
-.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */
-.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */
-.equ COL09_DATA, 0x09090909 /* 9 col data */
-.equ COL08_DATA, 0x08080808 /* 8 col data */
-.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */
-.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */
-.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */
-.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
-.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
-
-.globl mem_init
-mem_init:
- /* Preserve Boot Flags */
- movl %ebx, %ebp
-
- /* initialize dram controller registers */
- xorw %ax, %ax
- movl $DBCTL, %edi
- movb %al, (%edi) /* disable write buffer */
-
- movl $ECCCTL, %edi
- movb %al, (%edi) /* disable ECC */
-
- movl $DRCTMCTL, %edi
- movb $0x1e, %al /* Set SDRAM timing for slowest */
- movb %al, (%edi)
-
- /* setup loop to do 4 external banks starting with bank 3 */
- movl $0xff000000, %eax /* enable last bank and setup */
- movl $DRCBENDADR, %edi /* ending address register */
- movl %eax, (%edi)
-
- movl $DRCCFG, %edi /* setup */
- movw $0xbbbb, %ax /* dram config register for */
- movw %ax, (%edi)
-
- /* issue a NOP to all DRAMs */
- movl $DRCCTL, %edi /* setup DRAM control register with */
- movb $0x01, %al /* Disable refresh,disable write buffer */
- movb %al, (%edi)
- movl $CACHELINESZ, %esi /* just a dummy address to write for */
- movw %ax, (%esi)
-
- /* delay for 100 usec? */
- movw $100, %cx
-sizdelay:
- loop sizdelay
-
- /* issue all banks precharge */
- movb $0x02, %al
- movb %al, (%edi)
- movw %ax, (%esi)
-
- /* issue 2 auto refreshes to all banks */
- movb $0x04, %al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $0x02, %cx
-refresh1:
- movw %ax, (%esi)
- loop refresh1
-
- /* issue LOAD MODE REGISTER command */
- movb $0x03, %al /* Load mode register cmd */
- movb %al, (%edi)
- movw %ax, (%esi)
-
- /* issue 8 more auto refreshes to all banks */
- movb $0x04, %al /* Auto refresh cmd */
- movb %al, (%edi)
- movw $0x0008, %cx
-refresh2:
- movw %ax, (%esi)
- loop refresh2
-
- /* set control register to NORMAL mode */
- movb $0x00, %al /* Normal mode value */
- movb %al, (%edi)
-
- /*
- * size dram starting with external bank 3
- * moving to external bank 0
- */
- movl $0x3, %ecx /* start with external bank 3 */
-
-nextbank:
-
- /* write col 11 wrap adr */
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
- movl %eax, (%esi) /* write max col pattern at max col adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write col 10 wrap adr */
- movl $COL10_ADR, %esi /* set address to 10 col wrap address */
- movl $COL10_DATA, %eax /* pattern for 10 col wrap */
- movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write col 9 wrap adr */
- movl $COL09_ADR, %esi /* set address to 9 col wrap address */
- movl $COL09_DATA, %eax /* pattern for 9 col wrap */
- movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write col 8 wrap adr */
- movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
- movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
- movl %eax, (%esi) /* write min col pattern @ min col adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write row 14 wrap adr */
- movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
- movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
- movl %eax, (%esi) /* write max row pattern at max row adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write row 13 wrap adr */
- movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
- movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
- movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write row 12 wrap adr */
- movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
- movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
- movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
- movl (%esi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /* write row 11 wrap adr */
- movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
- movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
- movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
- movl (%edi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /*
- * write row 10 wrap adr --- this write is really to determine
- * number of banks
- */
- movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
- movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
- movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
- movl (%edi), %ebx /* optional read */
- cmpl %ebx, %eax /* to verify write */
- jnz bad_ram /* this ram is bad */
-
- /*
- * read data @ row 12 wrap adr to determine * banks,
- * and read data @ row 14 wrap adr to determine * rows.
- * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
- * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
- * if data @ row 12 wrap == 11 or 12, we have 4 banks,
- */
- xorw %di, %di /* value for 2 banks in DI */
- movl (%esi), %ebx /* read from 12 row wrap to check banks */
- /* (esi is setup from the write to row 12 wrap) */
- cmpl %ebx, %eax /* check for AA pattern (eax holds the aa pattern) */
- jz only2 /* if pattern == AA, we only have 2 banks */
-
- /* 4 banks */
-
- movw $0x008, %di /* value for 4 banks in DI (BNK_CNT bit) */
- cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
- jz only2
- cmpl $ROW12_DATA, %ebx /* and 12 */
- jnz bad_ram /* its bad if not 11 or 12! */
-
- /* fall through */
-only2:
- /*
- * validate row mask
- */
- movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
- movl (%esi), %eax /* read actual number of rows @ row14 adr */
-
- cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
- jb bad_ram
-
- cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
- ja bad_ram
-
- cmpb %ah, %al /* verify all 4 bytes of dword same */
- jnz bad_ram
- movl %eax, %ebx
- shrl $16, %ebx
- cmpw %bx, %ax
- jnz bad_ram
-
- /*
- * read col 11 wrap adr for real column data value
- */
- movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
- movl (%esi), %eax /* read real col number at max col adr */
-
- /*
- * validate column data
- */
- cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
- jb bad_ram
-
- cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
- ja bad_ram
-
- subl $COL08_DATA, %eax /* normalize column data to zero */
- jc bad_ram
- cmpb %ah, %al /* verify all 4 bytes of dword equal */
- jnz bad_ram
- movl %eax, %edx
- shrl $16, %edx
- cmpw %dx, %ax
- jnz bad_ram
-
- /*
- * merge bank and col data together
- */
- addw %di, %dx /* merge of bank and col info in dl */
-
- /*
- * fix ending addr mask based upon col info
- */
- movb $0x03, %al
- subb %dh, %al /* dh contains the overflow from the bank/col merge */
- movb %bl, %dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
- xchgw %cx, %ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
- shrb %cl, %dh
- incb %dh /* ending addr is 1 greater than real end */
- xchgw %cx, %ax /* cx is bank number again */
-
-bad_reint:
- /*
- * issue all banks precharge
- */
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x02, %al /* All banks precharge */
- movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
- movw %ax, (%esi)
-
- /*
- * update ENDING ADDRESS REGISTER
- */
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movl %ecx, %ebx
- addl %ebx, %edi
- movb %dh, (%edi)
-
- /*
- * update CONFIG REGISTER
- */
- xorb %dh, %dh
- movw $0x000f, %bx
- movw %cx, %ax
- shlw $2, %ax
- xchgw %cx, %ax
- shlw %cl, %dx
- shlw %cl, %bx
- notw %bx
- xchgw %cx, %ax
- movl $DRCCFG, %edi
- movw (%edi), %ax
- andw %bx, %ax
- orw %dx, %ax
- movw %ax, (%edi)
- jcxz cleanup
-
- decw %cx
- movl %ecx, %ebx
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movb $0xff, %al
- addl %ebx, %edi
- movb %al, (%edi)
-
- /*
- * set control register to NORMAL mode
- */
- movl $DRCCTL, %esi /* setup DRAM control register with */
- movb $0x00, %al /* Normal mode value */
- movb %al, (%esi)
- movl $CACHELINESZ, %esi /* address to init read buffer */
- movw %ax, (%esi)
- jmp nextbank
-
-cleanup:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
- movw $0x04, %cx
- xorw %ax, %ax
-cleanuplp:
- movb (%edi), %al
- orb %al, %al
- jz emptybank
-
- addb %ah, %al
- jns nottoomuch
-
- movb $0x7f, %al
-nottoomuch:
- movb %al, %ah
- orb $0x80, %al
- movb %al, (%edi)
-emptybank:
- incl %edi
- loop cleanuplp
-
-#if defined CONFIG_SYS_SDRAM_DRCTMCTL
- /* just have your hardware desinger _GIVE_ you what you need here! */
- movl $DRCTMCTL, %edi
- movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
- movb %al, (%edi)
-#else
-#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
- /*
- * Set the CAS latency now since it is hard to do
- * when we run from the RAM
- */
- movl $DRCTMCTL, %edi /* DRAM timing register */
- movb (%edi), %al
-#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
- andb $0xef, %al
-#endif
-#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
- orb $0x10, %al
-#endif
- movb %al, (%edi)
-#endif
-#endif
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x03, %al /* Load mode register cmd */
- movb %al, (%edi)
- movw %ax, (%esi)
-
-
- movl $DRCCTL, %edi /* DRAM Control register */
- movb $0x18, %al /* Enable refresh and NORMAL mode */
- movb %al, (%edi)
-
- jmp dram_done
-
-bad_ram:
- xorl %edx, %edx
- xorl %edi, %edi
- jmp bad_reint
-
-dram_done:
- /* Restore Boot Flags */
- movl %ebx, %ebp
- jmp mem_init_ret
-
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
-.globl init_ecc
-init_ecc:
- /* A nominal memory test: just a byte at each address line */
- movl %eax, %ecx
- shrl $0x1, %ecx
- movl $0x1, %edi
-memtest0:
- movb $0xa5, (%edi)
- cmpb $0xa5, (%edi)
- jne out
- shrl $0x1, %ecx
- andl %ecx, %ecx
- jz set_ecc
- shll $0x1, %edi
- jmp memtest0
-
-set_ecc:
- /* clear all ram with a memset */
- movl %eax, %ecx
- xorl %esi, %esi
- xorl %edi, %edi
- xorl %eax, %eax
- shrl $0x2, %ecx
- cld
- rep stosl
-
- /* enable read, write buffers */
- movb $0x11, %al
- movl $DBCTL, %edi
- movb %al, (%edi)
-
- /* enable NMI mapping for ECC */
- movl $ECCINT, %edi
- movb $0x10, %al
- movb %al, (%edi)
-
- /* Turn on ECC */
- movl $ECCCTL, %edi
- movb $0x05, %al
- movb %al,(%edi)
-
-out:
- jmp init_ecc_ret
-#endif
-
-/*
- * Read and decode the sc520 DRCBENDADR MMCR and return the number of
- * available ram bytes in %eax
- */
-.globl get_mem_size
-get_mem_size:
- movl $DRCBENDADR, %edi /* DRAM ending address register */
-
-bank0: movl (%edi), %eax
- movl %eax, %ecx
- andl $0x00000080, %ecx
- jz bank1
- andl $0x0000007f, %eax
- shll $22, %eax
- movl %eax, %edx
-
-bank1: movl (%edi), %eax
- movl %eax, %ecx
- andl $0x00008000, %ecx
- jz bank2
- andl $0x00007f00, %eax
- shll $14, %eax
- movl %eax, %edx
-
-bank2: movl (%edi), %eax
- movl %eax, %ecx
- andl $0x00800000, %ecx
- jz bank3
- andl $0x007f0000, %eax
- shll $6, %eax
- movl %eax, %edx
-
-bank3: movl (%edi), %eax
- movl %eax, %ecx
- andl $0x80000000, %ecx
- jz done
- andl $0x7f000000, %eax
- shrl $2, %eax
- movl %eax, %edx
-
-done:
- movl %edx, %eax
- jmp get_mem_size_ret
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Graeme Russ <graeme.russ@gmail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <asm/processor-flags.h>
+#include <asm/ic/sc520.h>
+
+.section .text
+
+.globl car_init
+car_init:
+ /*
+ * How to enable Cache-As-RAM for the AMD Elan SC520:
+ * 1. Turn off the CPU Cache (may not be strictly required)
+ * 2. Set code execution PAR (usually the BOOTCS region) to be
+ * non-cachable
+ * 3. Create a Cachable PAR Region for an area of memory which is
+ * a) NOT where the code is being executed
+ * b) NOT SDRAM (Controller not initialised yet)
+ * c) WILL response to read requests
+ * The easiest way to do this is to create a second BOOTCS
+ * PAR mappnig with an address != the PAR in step 2
+ * 4. Issue a wbinvd to invalidate the CPU cache
+ * 5. Turn on the CPU Cache
+ * 6. Read 16kB from the cached PAR region setup in step 3
+ * 7. Turn off the CPU Cache (but DO NOT issue a wbinvd)
+ *
+ * The following code uses PAR2 as the cached PAR (PAR0 and PAR1
+ * are avoided as these are the only two PARs which can be used
+ * as PCI BUS Memory regions which the board might require)
+ *
+ * The configuration of PAR2 must be set in the board configuration
+ * file as CONFIG_SYS_SC520_CAR_PAR
+ */
+
+ /* Configure Cache-As-RAM PAR */
+ movl $CONFIG_SYS_SC520_CAR_PAR, %eax
+ movl $SC520_PAR2, %edi
+ movl %eax, (%edi)
+
+ /* Trash the cache then turn it on */
+ wbinvd
+ movl %cr0, %eax
+ andl $~(X86_CR0_NW | X86_CR0_CD), %eax
+ movl %eax, %cr0
+
+ /*
+ * The cache is now enabled and empty. Map a region of memory to
+ * it by reading that region.
+ */
+ movl $CONFIG_SYS_CAR_ADDR, %esi
+ movl $CONFIG_SYS_CAR_SIZE, %ecx
+ shrl $2, %ecx /* we are reading longs */
+ cld
+ rep lodsl
+
+ /* Turn off the cache, but don't trash it */
+ movl %cr0, %eax
+ orl $(X86_CR0_NW | X86_CR0_CD), %eax
+ movl %eax, %cr0
+
+ /* Clear the CAR region */
+ xorl %eax, %eax
+ movl $CONFIG_SYS_CAR_ADDR, %edi
+ movl $CONFIG_SYS_CAR_SIZE, %ecx
+ shrl $2, %ecx /* we are writing longs */
+ rep stosl
+
+ /*
+ * Done - We should now have CONFIG_SYS_CAR_SIZE bytes of
+ * Cache-As-RAM
+ */
+ jmp car_init_ret
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Graeme Russ <graeme.russ@gmail.com>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/processor-flags.h>
+#include <asm/ic/sc520.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct sc520_sdram_info {
+ u8 banks;
+ u8 columns;
+ u8 rows;
+ u8 size;
+};
+
+static void sc520_sizemem(void);
+static void sc520_set_dram_timing(void);
+static void sc520_set_dram_refresh_rate(void);
+static void sc520_enable_dram_refresh(void);
+static void sc520_enable_sdram(void);
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+static void sc520_enable_ecc(void)
+#endif
+
+int dram_init_f(void)
+{
+ sc520_sizemem();
+ sc520_set_dram_timing();
+ sc520_set_dram_refresh_rate();
+ sc520_enable_dram_refresh();
+ sc520_enable_sdram();
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+ sc520_enable_ecc();
+#endif
+
+ return 0;
+}
+
+static inline void sc520_dummy_write(void)
+{
+ writew(0x0000, CACHELINESZ);
+}
+static inline void sc520_issue_sdram_op_mode_select(u8 command)
+{
+ writeb(command, &sc520_mmcr->drcctl);
+ sc520_dummy_write();
+}
+
+static inline int check_long(u32 test_long)
+{
+ u8 i;
+ u8 tmp_byte = (u8)(test_long & 0x000000ff);
+
+ for (i = 1; i < 4; i++) {
+ if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
+ return -1;
+ }
+
+ return 0;
+}
+
+static inline int write_and_test(u32 data, u32 address)
+{
+ writel(data, address);
+ if (readl(address) == data)
+ return 0; /* Good */
+ else
+ return -1; /* Bad */
+}
+
+static void sc520_enable_sdram(void)
+{
+ u32 par_config;
+
+ /* Enable Writes, Caching and Code Execution to SDRAM */
+ par_config = readl(&sc520_mmcr->par[3]);
+ par_config &= ~(SC520_PAR_EXEC_DIS |
+ SC520_PAR_CACHE_DIS |
+ SC520_PAR_WRITE_DIS);
+ writel(par_config, &sc520_mmcr->par[3]);
+
+ par_config = readl(&sc520_mmcr->par[4]);
+ par_config &= ~(SC520_PAR_EXEC_DIS |
+ SC520_PAR_CACHE_DIS |
+ SC520_PAR_WRITE_DIS);
+ writel(par_config, &sc520_mmcr->par[4]);
+}
+
+static void sc520_set_dram_timing(void)
+{
+ u8 drctmctl = 0x00;
+
+#if defined CONFIG_SYS_SDRAM_DRCTMCTL
+ /* just have your hardware designer _GIVE_ you what you need here! */
+ drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
+#else
+ switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
+ case 2:
+ break;
+ case 3:
+ drctmctl |= 0x01;
+ break;
+ case 4:
+ default:
+ drctmctl |= 0x02;
+ break;
+ }
+
+ switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
+ case 2:
+ break;
+ case 3:
+ drctmctl |= 0x04;
+ break;
+ case 4:
+ default:
+ drctmctl |= 0x08;
+ break;
+
+ case 6:
+ drctmctl |= 0x0c;
+ break;
+ }
+
+ switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
+ case 2:
+ break;
+ case 3:
+ default:
+ drctmctl |= 0x10;
+ break;
+ }
+#endif
+ writeb(drctmctl, &sc520_mmcr->drctmctl);
+
+ /* Issue load mode register command */
+ sc520_issue_sdram_op_mode_select(0x03);
+}
+
+static void sc520_set_dram_refresh_rate(void)
+{
+ u8 drctl;
+
+ drctl = readb(&sc520_mmcr->drcctl);
+ drctl &= 0xcf;
+
+ switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
+ case 78:
+ break;
+ case 156:
+ default:
+ drctl |= 0x10;
+ break;
+ case 312:
+ drctl |= 0x20;
+ break;
+ case 624:
+ drctl |= 0x30;
+ break;
+ }
+
+ writeb(drctl, &sc520_mmcr->drcctl);
+}
+
+static void sc520_enable_dram_refresh(void)
+{
+ u8 drctl;
+
+ drctl = readb(&sc520_mmcr->drcctl);
+ drctl &= 0x30; /* keep refresh rate */
+ drctl |= 0x08; /* enable refresh, normal mode */
+
+ writeb(drctl, &sc520_mmcr->drcctl);
+}
+
+static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info)
+{
+ u32 col_data;
+ u32 row_data;
+
+ u32 drcbendadr;
+ u16 drccfg;
+
+ u8 banks = 0x00;
+ u8 columns = 0x00;
+ u8 rows = 0x00;
+
+ bank_info->banks = 0x00;
+ bank_info->columns = 0x00;
+ bank_info->rows = 0x00;
+ bank_info->size = 0x00;
+
+ if ((bank < 0) || (bank > 3)) {
+ printf("Bad Bank ID\n");
+ return;
+ }
+
+ /* Save configuration */
+ drcbendadr = readl(&sc520_mmcr->drcbendadr);
+ drccfg = readw(&sc520_mmcr->drccfg);
+
+ /* Setup SDRAM Bank to largest possible size */
+ writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
+
+ /* Set ending address for this bank */
+ writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
+
+ /* write col 11 wrap adr */
+ if (write_and_test(COL11_DATA, COL11_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write col 10 wrap adr */
+ if (write_and_test(COL10_DATA, COL10_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write col 9 wrap adr */
+ if (write_and_test(COL09_DATA, COL09_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write col 8 wrap adr */
+ if (write_and_test(COL08_DATA, COL08_ADR) != 0)
+ goto restore_and_exit;
+
+ col_data = readl(COL11_ADR);
+
+ /* All four bytes in the read long must be the same */
+ if (check_long(col_data) < 0)
+ goto restore_and_exit;
+
+ if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
+ columns = (u8)(col_data & 0x000000ff);
+ else
+ goto restore_and_exit;
+
+ /* write row 14 wrap adr */
+ if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write row 13 wrap adr */
+ if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write row 12 wrap adr */
+ if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
+ goto restore_and_exit;
+
+ /* write row 11 wrap adr */
+ if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
+ goto restore_and_exit;
+
+ if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
+ goto restore_and_exit;
+
+ /*
+ * read data @ row 12 wrap adr to determine number of banks,
+ * and read data @ row 14 wrap adr to determine number of rows.
+ * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
+ * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
+ * if data @ row 12 wrap == 11 or 12, we have 4 banks,
+ */
+ row_data = readl(ROW12_ADR);
+
+ /* All four bytes in the read long must be the same */
+ if (check_long(row_data) != 0)
+ goto restore_and_exit;
+
+ switch (row_data) {
+ case ROW10_DATA:
+ banks = 2;
+ break;
+
+ case ROW11_DATA:
+ case ROW12_DATA:
+ banks = 4;
+ break;
+
+ default:
+ goto restore_and_exit;
+ }
+
+ row_data = readl(ROW14_ADR);
+
+ /* All four bytes in the read long must be the same */
+ if (check_long(row_data) != 0)
+ goto restore_and_exit;
+
+ switch (row_data) {
+ case ROW11_DATA:
+ case ROW12_DATA:
+ case ROW13_DATA:
+ case ROW14_DATA:
+ rows = (u8)(row_data & 0x000000ff);
+ break;
+
+ default:
+ goto restore_and_exit;
+ }
+
+ bank_info->banks = banks;
+ bank_info->columns = columns;
+ bank_info->rows = rows;
+
+ if ((bank_info->banks != 0) &&
+ (bank_info->columns != 0) &&
+ (bank_info->rows != 0)) {
+ bank_info->size = bank_info->rows;
+ bank_info->size >>= (11 - bank_info->columns);
+ bank_info->size++;
+ }
+
+restore_and_exit:
+ /* Restore configuration */
+ writel(drcbendadr, &sc520_mmcr->drcbendadr);
+ writew(drccfg, &sc520_mmcr->drccfg);
+}
+
+static void sc520_setup_sizemem(void)
+{
+ u8 i;
+
+ /* Disable write buffer */
+ writeb(0x00, &sc520_mmcr->dbctl);
+
+ /* Disable ECC */
+ writeb(0x00, &sc520_mmcr->eccctl);
+
+ /* Set slowest SDRAM timing */
+ writeb(0x1e, &sc520_mmcr->drctmctl);
+
+ /* Issue a NOP to all SDRAM banks */
+ sc520_issue_sdram_op_mode_select(0x01);
+
+ /* Delay for 100 microseconds */
+ udelay(100);
+
+ /* Issue 'All Banks Precharge' command */
+ sc520_issue_sdram_op_mode_select(0x02);
+
+ /* Issue 2 'Auto Refresh Enable' command */
+ sc520_issue_sdram_op_mode_select(0x04);
+ sc520_dummy_write();
+
+ /* Issue 'Load Mode Register' command */
+ sc520_issue_sdram_op_mode_select(0x03);
+
+ /* Issue 8 more 'Auto Refresh Enable' commands */
+ sc520_issue_sdram_op_mode_select(0x04);
+ for (i = 0; i < 7; i++)
+ sc520_dummy_write();
+
+ /* Set control register to 'Normal Mode' */
+ writeb(0x00, &sc520_mmcr->drcctl);
+}
+
+static void sc520_sizemem(void)
+{
+ struct sc520_sdram_info sdram_info[4];
+ u8 bank_config = 0x00;
+ u8 end_addr = 0x00;
+ u16 drccfg = 0x0000;
+ u32 drcbendadr = 0x00000000;
+ u8 i;
+
+ /* Use PARs to disable caching of maximum allowable 256MB SDRAM */
+ writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]);
+ writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]);
+
+ sc520_setup_sizemem();
+
+ gd->ram_size = 0;
+
+ /* Size each SDRAM bank */
+ for (i = 0; i <= 3; i++) {
+ sc520_get_bank_info(i, &sdram_info[i]);
+
+ if (sdram_info[i].banks != 0) {
+ /* Update Configuration register */
+ bank_config = sdram_info[i].columns - 8;
+
+ if (sdram_info[i].banks == 4)
+ bank_config |= 0x08;
+
+ drccfg |= bank_config << (i * 4);
+
+ /* Update End Address register */
+ end_addr += sdram_info[i].size;
+ drcbendadr |= (end_addr | 0x80) << (i * 8);
+
+ gd->ram_size += sdram_info[i].size << 22;
+ }
+
+ /* Issue 'All Banks Precharge' command */
+ sc520_issue_sdram_op_mode_select(0x02);
+
+ /* Set control register to 'Normal Mode' */
+ writeb(0x00, &sc520_mmcr->drcctl);
+ }
+
+ writel(drcbendadr, &sc520_mmcr->drcbendadr);
+ writew(drccfg, &sc520_mmcr->drccfg);
+
+ /* Clear PARs preventing caching of SDRAM */
+ writel(0x00000000, &sc520_mmcr->par[3]);
+ writel(0x00000000, &sc520_mmcr->par[4]);
+}
+
+#if CONFIG_SYS_SDRAM_ECC_ENABLE
+static void sc520_enable_ecc(void)
+
+ /* A nominal memory test: just a byte at each address line */
+ movl %eax, %ecx
+ shrl $0x1, %ecx
+ movl $0x1, %edi
+memtest0:
+ movb $0xa5, (%edi)
+ cmpb $0xa5, (%edi)
+ jne out
+ shrl $0x1, %ecx
+ andl %ecx, %ecx
+ jz set_ecc
+ shll $0x1, %edi
+ jmp memtest0
+
+set_ecc:
+ /* clear all ram with a memset */
+ movl %eax, %ecx
+ xorl %esi, %esi
+ xorl %edi, %edi
+ xorl %eax, %eax
+ shrl $0x2, %ecx
+ cld
+ rep stosl
+
+ /* enable read, write buffers */
+ movb $0x11, %al
+ movl $DBCTL, %edi
+ movb %al, (%edi)
+
+ /* enable NMI mapping for ECC */
+ movl $ECCINT, %edi
+ movb $0x10, %al
+ movb %al, (%edi)
+
+ /* Turn on ECC */
+ movl $ECCCTL, %edi
+ movb $0x05, %al
+ movb %al,(%edi)
+
+out:
+ jmp init_ecc_ret
+}
+#endif
+
+int dram_init(void)
+{
+ ulong dram_ctrl;
+ ulong dram_present = 0x00000000;
+
+ /*
+ * We read-back the configuration of the dram
+ * controller that the assembly code wrote
+ */
+ dram_ctrl = readl(&sc520_mmcr->drcbendadr);
+
+ gd->bd->bi_dram[0].start = 0;
+ if (dram_ctrl & 0x80) {
+ /* bank 0 enabled */
+ gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
+ dram_present = gd->bd->bi_dram[1].start;
+ gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
+ } else {
+ gd->bd->bi_dram[0].size = 0;
+ gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
+ }
+
+ if (dram_ctrl & 0x8000) {
+ /* bank 1 enabled */
+ gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
+ dram_present = gd->bd->bi_dram[2].start;
+ gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
+ gd->bd->bi_dram[1].start;
+ } else {
+ gd->bd->bi_dram[1].size = 0;
+ gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
+ }
+
+ if (dram_ctrl & 0x800000) {
+ /* bank 2 enabled */
+ gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
+ dram_present = gd->bd->bi_dram[3].start;
+ gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
+ gd->bd->bi_dram[2].start;
+ } else {
+ gd->bd->bi_dram[2].size = 0;
+ gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
+ }
+
+ if (dram_ctrl & 0x80000000) {
+ /* bank 3 enabled */
+ dram_present = (dram_ctrl & 0x7f000000) >> 2;
+ gd->bd->bi_dram[3].size = dram_present -
+ gd->bd->bi_dram[3].start;
+ } else {
+ gd->bd->bi_dram[3].size = 0;
+ }
+
+ gd->ram_size = dram_present;
+
+ return 0;
+}
/*
* U-boot - i386 Startup Code
*
- * Copyright (c) 2002 Omicron Ceti AB, Daniel Engstr�m <denaiel@omicron.se>
+ * Copyright (c) 2002 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
*
* See file CREDITS for list of people who contributed to this
* project.
#include <config.h>
#include <version.h>
#include <asm/global_data.h>
+#include <asm/processor-flags.h>
.section .text
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $0x60000000, %eax
+ orl $(X86_CR0_NW | X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd
/* Clear the interupt vectors */
lidt blank_idt_ptr
- /* Skip low-level initialization if not starting from cold-reset */
- movl %ebx, %ecx
- andl $GD_FLG_COLD_BOOT, %ecx
- jz skip_mem_init
-
/* Early platform init (setup gpio, etc ) */
jmp early_board_init
.globl early_board_init_ret
early_board_init_ret:
- /* size memory */
- jmp mem_init
-.globl mem_init_ret
-mem_init_ret:
-
-skip_mem_init:
- /* fetch memory size (into %eax) */
- jmp get_mem_size
-.globl get_mem_size_ret
-get_mem_size_ret:
-
-#if CONFIG_SYS_SDRAM_ECC_ENABLE
- /* Skip ECC initialization if not starting from cold-reset */
- movl %ebx, %ecx
- andl $GD_FLG_COLD_BOOT, %ecx
- jz init_ecc_ret
- jmp init_ecc
-
-.globl init_ecc_ret
-init_ecc_ret:
-#endif
-
- /* Check we have enough memory for stack */
- movl $CONFIG_SYS_STACK_SIZE, %ecx
- cmpl %ecx, %eax
- jb die
-mem_ok:
- /* Set stack pointer to upper memory limit*/
- movl %eax, %esp
+ /* Initialise Cache-As-RAM */
+ jmp car_init
+.globl car_init_ret
+car_init_ret:
+ /*
+ * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
+ * or fully initialised SDRAM - we really don't care which)
+ * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
+ */
+ movl $CONFIG_SYS_INIT_SP_ADDR, %esp
+ movl $CONFIG_SYS_INIT_GD_ADDR, %ebp
- /* Test the stack */
- pushl $0
- popl %ecx
- cmpl $0, %ecx
- jne die
- push $0x55aa55aa
- popl %ecx
- cmpl $0x55aa55aa, %ecx
- jne die
+ /* Set Boot Flags in Global Data */
+ movl %ebx, (GD_FLAGS * 4)(%ebp)
- wbinvd
-
- /* Determine our load offset */
+ /* Determine our load offset (and put in Global Data) */
call 1f
1: popl %ecx
subl $1b, %ecx
+ movl %ecx, (GD_LOAD_OFF * 4)(%ebp)
- /* Set the upper memory limit parameter */
- subl $CONFIG_SYS_STACK_SIZE, %eax
-
- /* Reserve space for global data */
- subl $(GD_SIZE * 4), %eax
-
- /* %eax points to the global data structure */
- movl %esp, (GD_RAM_SIZE * 4)(%eax)
- movl %ebx, (GD_FLAGS * 4)(%eax)
- movl %ecx, (GD_LOAD_OFF * 4)(%eax)
+ /* Set parameter to board_init_f() to boot flags */
+ movl (GD_FLAGS * 4)(%ebp), %eax
call board_init_f /* Enter, U-boot! */
/* indicate (lack of) progress */
movw $0x85, %ax
+ jmp die
+
+.globl relocate_code
+.type relocate_code, @function
+relocate_code:
+ /*
+ * SDRAM has been initialised, U-Boot code has been copied into
+ * RAM, BSS has been cleared and relocation adjustments have been
+ * made. It is now time to jump into the in-RAM copy of U-Boot
+ *
+ * %eax = Address of top of stack
+ * %edx = Address of Global Data
+ * %ecx = Base address of in-RAM copy of U-Boot
+ */
+
+ /* Setup stack in RAM */
+ movl %eax, %esp
+
+ /* Setup call address of in-RAM copy of board_init_r() */
+ movl $board_init_r, %ebp
+ addl (GD_RELOC_OFF * 4)(%edx), %ebp
+
+ /* Setup parameters to board_init_r() */
+ movl %edx, %eax
+ movl %ecx, %edx
+
+ /* Jump to in-RAM copy of board_init_r() */
+ call *%ebp
+
die: hlt
jmp die
hlt
*/
#include <asm/global_data.h>
+#include <asm/processor-flags.h>
#define BOOT_SEG 0xffff0000 /* linear segment of boot code */
#define a32 .byte 0x67;
/* Turn of cache (this might require a 486-class CPU) */
movl %cr0, %eax
- orl $0x60000000, %eax
+ orl $(X86_CR0_NW & X86_CR0_CD), %eax
movl %eax, %cr0
wbinvd
/* Now, we enter protected mode */
movl %cr0, %eax
- orl $1, %eax
+ orl $X86_CR0_PE, %eax
movl %eax, %cr0
/* Flush the prefetch queue */
/DISCARD/ : { *(.gnu*) }
/* 16bit realmode trampoline code */
- .realmode 0x7c0 : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
+ .realmode REALMODE_BASE : AT ( LOADADDR(.rel.dyn) + SIZEOF(.rel.dyn) ) { KEEP(*(.realmode)) }
__realmode_start = LOADADDR(.realmode);
__realmode_size = SIZEOF(.realmode);
__bios_start = LOADADDR(.bios);
__bios_size = SIZEOF(.bios);
- /* The load addresses below assumes that the flash
- * will be mapped so that 0x387f0000 == 0xffff0000
- * at reset time
- *
- * The fe00 and ff00 offsets of the start32 and start16
- * segments are arbitrary, the just have to be mapped
- * at reset and the code have to fit.
- * The fff0 offset of resetvec is important, however.
+ /*
+ * The following expressions place the 16-bit Real-Mode code and
+ * Reset Vector at the end of the Flash ROM
*/
- . = 0xfffffe00;
- .start32 : AT (CONFIG_SYS_TEXT_BASE + 0x3fe00) { KEEP(*(.start32)); }
+ . = START_16;
+ .start16 : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + START_16)) { KEEP(*(.start16)); }
- . = 0xf800;
- .start16 : AT (CONFIG_SYS_TEXT_BASE + 0x3f800) { KEEP(*(.start16)); }
-
- . = 0xfff0;
- .resetvec : AT (CONFIG_SYS_TEXT_BASE + 0x3fff0) { KEEP(*(.resetvec)); }
+ . = RESET_VEC_LOC;
+ .resetvec : AT (CONFIG_SYS_TEXT_BASE + (FLASH_SIZE - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
}
#ifndef __ASSEMBLY__
-typedef struct {
+typedef struct global_data {
bd_t *bd;
unsigned long flags;
unsigned long baudrate;
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
+ unsigned long relocaddr; /* Start address of U-Boot in RAM */
+ unsigned long start_addr_sp; /* start_addr_stackpointer */
phys_size_t ram_size; /* RAM size */
unsigned long reset_status; /* reset status register at boot */
void **jt; /* jump table */
#define GD_ENV_VALID 7
#define GD_CPU_CLK 8
#define GD_BUS_CLK 9
-#define GD_RAM_SIZE 10
-#define GD_RESET_STATUS 11
-#define GD_JT 12
+#define GD_RELOC_ADDR 10
+#define GD_START_ADDR_SP 11
+#define GD_RAM_SIZE 12
+#define GD_RESET_STATUS 13
+#define GD_JT 14
-#define GD_SIZE 13
+#define GD_SIZE 15
/*
* Global Data Flags
#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */
#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
-
+#if 0
#define DECLARE_GLOBAL_DATA_PTR
+#else
+#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
+#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
+gd_t *gd
+#endif
#endif /* __ASM_GBL_DATA_H */
u8 pad_0xdc0[0x0240];
} sc520_mmcr_t;
-extern volatile sc520_mmcr_t *sc520_mmcr;
+extern sc520_mmcr_t *sc520_mmcr;
#endif
-/* MMCR Offsets (required for assembler code */
-#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */
-#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */
-#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */
-#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */
-#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */
+/* Memory Mapped Control Registers (MMCR) Base Address */
+#define SC520_MMCR_BASE 0xfffef000
+
+/* MMCR Addresses (required for assembler code) */
+#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
+#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
+#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
+#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
+#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
+#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
+#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
+
+#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
+#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
+#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
+#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
+#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
+#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
+#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
+#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
+#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
+#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
+#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
+#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
+#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
+#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
+#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
+#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
+
+/*
+ * PARs for maximum allowable 256MB of SDRAM @ 0x00000000
+ * Two PARs are required due to maximum PAR size of 128MB
+ * These are used in the SDRAM sizing code to disable caching
+ *
+ * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
+ * 111 0 0 0 1 11111111111 00100000000000 }- 0xe3ffc800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x00000000
+ * | | | | | | 0x08000000
+ * | | | | | +----------------------- 128MB Region Size
+ * | | | | | ((2047 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Enabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- SDRAM
+ */
+#define SC520_SDRAM1_PAR 0xe3ffc000
+#define SC520_SDRAM2_PAR 0xe3ffc800
+
+#define SC520_PAR_WRITE_DIS 0x04000000
+#define SC520_PAR_CACHE_DIS 0x08000000
+#define SC520_PAR_EXEC_DIS 0x10000000
+
+/*
+ * Programmable Address Regions to cover 256MB SDRAM (Maximum supported)
+ * required for DRAM sizing code
+ */
/* MMCR Register bits (not all of them :) ) */
#define UART2_DIS 0x02 /* UART2 Disable */
#define UART1_DIS 0x01 /* UART1 Disable */
+/*
+ * Defines used for SDRAM Sizing (number of columns and rows)
+ * Refer to section 10.6.4 - SDRAM Sizing Algorithm in the
+ * Elan SC520 Microcontroller User's Manual (Order #22004B)
+ */
+#define CACHELINESZ 0x00000010
+
+#define COL11_ADR 0x0e001e00
+#define COL10_ADR 0x0e000e00
+#define COL09_ADR 0x0e000600
+#define COL08_ADR 0x0e000200
+#define COL11_DATA 0x0b0b0b0b
+#define COL10_DATA 0x0a0a0a0a
+#define COL09_DATA 0x09090909
+#define COL08_DATA 0x08080808
+
+#define ROW14_ADR 0x0f000000
+#define ROW13_ADR 0x07000000
+#define ROW12_ADR 0x03000000
+#define ROW11_ADR 0x01000000
+#define ROW10_ADR 0x00000000
+#define ROW14_DATA 0x3f3f3f3f
+#define ROW13_DATA 0x1f1f1f1f
+#define ROW12_DATA 0x0f0f0f0f
+#define ROW11_DATA 0x07070707
+#define ROW10_DATA 0xaaaaaaaa
+
/* 0x28000000 - 0x3fffffff is used by the flash banks */
/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
--- /dev/null
+#ifndef _ASM_X86_PROCESSOR_FLAGS_H
+#define _ASM_X86_PROCESSOR_FLAGS_H
+/* Various flags defined: can be included from assembler. */
+
+/*
+ * EFLAGS bits
+ */
+#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
+#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
+#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
+#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
+#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
+#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
+#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
+#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
+#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
+#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
+#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
+#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
+#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
+#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
+#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
+#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
+
+/*
+ * Basic CPU control in CR0
+ */
+#define X86_CR0_PE 0x00000001 /* Protection Enable */
+#define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */
+#define X86_CR0_EM 0x00000004 /* Emulation */
+#define X86_CR0_TS 0x00000008 /* Task Switched */
+#define X86_CR0_ET 0x00000010 /* Extension Type */
+#define X86_CR0_NE 0x00000020 /* Numeric Error */
+#define X86_CR0_WP 0x00010000 /* Write Protect */
+#define X86_CR0_AM 0x00040000 /* Alignment Mask */
+#define X86_CR0_NW 0x20000000 /* Not Write-through */
+#define X86_CR0_CD 0x40000000 /* Cache Disable */
+#define X86_CR0_PG 0x80000000 /* Paging */
+
+/*
+ * Paging options in CR3
+ */
+#define X86_CR3_PWT 0x00000008 /* Page Write Through */
+#define X86_CR3_PCD 0x00000010 /* Page Cache Disable */
+
+/*
+ * Intel CPU features in CR4
+ */
+#define X86_CR4_VME 0x00000001 /* enable vm86 extensions */
+#define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */
+#define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */
+#define X86_CR4_DE 0x00000008 /* enable debugging extensions */
+#define X86_CR4_PSE 0x00000010 /* enable page size extensions */
+#define X86_CR4_PAE 0x00000020 /* enable physical address extensions */
+#define X86_CR4_MCE 0x00000040 /* Machine check enable */
+#define X86_CR4_PGE 0x00000080 /* enable global pages */
+#define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */
+#define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */
+#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
+#define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */
+#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
+
+/*
+ * x86-64 Task Priority Register, CR8
+ */
+#define X86_CR8_TPR 0x0000000F /* task priority register */
+
+/*
+ * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
+ */
+
+/*
+ * NSC/Cyrix CPU configuration register indexes
+ */
+#define CX86_PCR0 0x20
+#define CX86_GCR 0xb8
+#define CX86_CCR0 0xc0
+#define CX86_CCR1 0xc1
+#define CX86_CCR2 0xc2
+#define CX86_CCR3 0xc3
+#define CX86_CCR4 0xe8
+#define CX86_CCR5 0xe9
+#define CX86_CCR6 0xea
+#define CX86_CCR7 0xeb
+#define CX86_PCR1 0xf0
+#define CX86_DIR0 0xfe
+#define CX86_DIR1 0xff
+#define CX86_ARR_BASE 0xc4
+#define CX86_RCR_BASE 0xdc
+
+#ifdef __KERNEL__
+#ifdef CONFIG_VM86
+#define X86_VM_MASK X86_EFLAGS_VM
+#else
+#define X86_VM_MASK 0 /* No VM86 support */
+#endif
+#endif
+
+#endif /* _ASM_X86_PROCESSOR_FLAGS_H */
#ifndef __ASM_PROCESSOR_H_
#define __ASM_PROCESSOR_H_ 1
-/* Currently this header is unused in the i386 port
- * but some generic files #include <asm/processor.h>
- * so this file is a placeholder. */
+
+#define GDT_ENTRY_32BIT_CS 2
+#define GDT_ENTRY_32BIT_DS (GDT_ENTRY_32BIT_CS + 1)
+#define GDT_ENTRY_16BIT_CS (GDT_ENTRY_32BIT_DS + 1)
+#define GDT_ENTRY_16BIT_DS (GDT_ENTRY_16BIT_CS + 1)
+
#endif
#define _U_BOOT_I386_H_ 1
/* cpu/.../cpu.c */
+int x86_cpu_init_r(void);
int cpu_init_r(void);
+int x86_cpu_init_f(void);
int cpu_init_f(void);
/* cpu/.../timer.c */
/* Architecture specific - can be in arch/i386/cpu/, arch/i386/lib/, or $(BOARD)/ */
int timer_init(void);
+int dram_init_f(void);
/* cpu/.../interrupts.c */
int cpu_init_interrupts(void);
/*
* (C) Copyright 2002
- * Daniel Engstr�m, Omicron Ceti AB, daniel@omicron.se
+ * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#include <miiphy.h>
#endif
-DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Pointer to initial global data area
+ *
+ * Here we initialize it.
+ */
+#undef XTRN_DECLARE_GLOBAL_DATA_PTR
+#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
+DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR);
+
/* Exports from the Linker Script */
extern ulong __text_start;
*/
typedef int (init_fnc_t) (void);
-init_fnc_t *init_sequence[] = {
+static int calculate_relocation_address(void);
+static int copy_uboot_to_ram(void);
+static int clear_bss(void);
+static int do_elf_reloc_fixups(void);
+
+init_fnc_t *init_sequence_f[] = {
+ cpu_init_f,
+ board_early_init_f,
+ env_init,
+ init_baudrate,
+ serial_init,
+ console_init_f,
+ dram_init_f,
+ calculate_relocation_address,
+ copy_uboot_to_ram,
+ clear_bss,
+ do_elf_reloc_fixups,
+
+ NULL,
+};
+
+init_fnc_t *init_sequence_r[] = {
cpu_init_r, /* basic cpu dependent setup */
board_early_init_r, /* basic board dependent setup */
dram_init, /* configure available RAM banks */
interrupt_init, /* set up exceptions */
timer_init,
- env_init, /* initialize environment */
- init_baudrate, /* initialze baudrate settings */
- serial_init, /* serial communications setup */
display_banner,
display_dram_config,
gd_t *gd;
-/*
- * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
- */
-void board_init_f (ulong gdp)
+static int calculate_relocation_address(void)
{
void *text_start = &__text_start;
- void *data_end = &__data_end;
- void *rel_dyn_start = &__rel_dyn_start;
- void *rel_dyn_end = &__rel_dyn_end;
- void *bss_start = &__bss_start;
void *bss_end = &__bss_end;
-
- ulong *dst_addr;
- ulong *src_addr;
- ulong *end_addr;
-
void *dest_addr;
ulong rel_offset;
- Elf32_Rel *re_src;
- Elf32_Rel *re_end;
/* Calculate destination RAM Address and relocation offset */
- dest_addr = (void *)gdp - (bss_end - text_start);
- rel_offset = text_start - dest_addr;
+ dest_addr = (void *)gd->ram_size;
+ dest_addr -= CONFIG_SYS_STACK_SIZE;
+ dest_addr -= (bss_end - text_start);
+ rel_offset = dest_addr - text_start;
- /* Perform low-level initialization only when cold booted */
- if (((gd_t *)gdp)->flags & GD_FLG_COLD_BOOT) {
- /* First stage CPU initialization */
- if (cpu_init_f() != 0)
- hang();
+ gd->start_addr_sp = gd->ram_size;
+ gd->relocaddr = (ulong)dest_addr;
+ gd->reloc_off = rel_offset;
- /* First stage Board initialization */
- if (board_early_init_f() != 0)
- hang();
- }
+ return 0;
+}
- /* Copy U-Boot into RAM */
- dst_addr = (ulong *)dest_addr;
- src_addr = (ulong *)(text_start + ((gd_t *)gdp)->load_off);
- end_addr = (ulong *)(data_end + ((gd_t *)gdp)->load_off);
+static int copy_uboot_to_ram(void)
+{
+ ulong *dst_addr = (ulong *)gd->relocaddr;
+ ulong *src_addr = (ulong *)&__text_start;
+ ulong *end_addr = (ulong *)&__data_end;
while (src_addr < end_addr)
*dst_addr++ = *src_addr++;
- /* Clear BSS */
- dst_addr = (ulong *)(bss_start - rel_offset);
- end_addr = (ulong *)(bss_end - rel_offset);
+ return 0;
+}
+
+static int clear_bss(void)
+{
+ void *bss_start = &__bss_start;
+ void *bss_end = &__bss_end;
+
+ ulong *dst_addr = (ulong *)(bss_start + gd->reloc_off);
+ ulong *end_addr = (ulong *)(bss_end + gd->reloc_off);;
while (dst_addr < end_addr)
*dst_addr++ = 0x00000000;
- /* Perform relocation adjustments */
- re_src = (Elf32_Rel *)(rel_dyn_start + ((gd_t *)gdp)->load_off);
- re_end = (Elf32_Rel *)(rel_dyn_end + ((gd_t *)gdp)->load_off);
+ return 0;
+}
+
+static int do_elf_reloc_fixups(void)
+{
+ Elf32_Rel *re_src = (Elf32_Rel *)(&__rel_dyn_start);
+ Elf32_Rel *re_end = (Elf32_Rel *)(&__rel_dyn_end);
do {
if (re_src->r_offset >= CONFIG_SYS_TEXT_BASE)
- if (*(Elf32_Addr *)(re_src->r_offset - rel_offset) >= CONFIG_SYS_TEXT_BASE)
- *(Elf32_Addr *)(re_src->r_offset - rel_offset) -= rel_offset;
+ if (*(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) >= CONFIG_SYS_TEXT_BASE)
+ *(Elf32_Addr *)(re_src->r_offset + gd->reloc_off) += gd->reloc_off;
} while (re_src++ < re_end);
- ((gd_t *)gdp)->reloc_off = rel_offset;
- ((gd_t *)gdp)->flags |= GD_FLG_RELOC;
+ return 0;
+}
+
+/*
+ * Load U-Boot into RAM, initialize BSS, perform relocation adjustments
+ */
+void board_init_f(ulong boot_flags)
+{
+ init_fnc_t **init_fnc_ptr;
+
+ for (init_fnc_ptr = init_sequence_f; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
+ hang();
+ }
+
+ gd->flags |= GD_FLG_RELOC;
/* Enter the relocated U-Boot! */
- (board_init_r - rel_offset)((gd_t *)gdp, (ulong)dest_addr);
+ relocate_code(gd->start_addr_sp, gd, gd->relocaddr);
- /* NOTREACHED - board_init_f() does not return */
+ /* NOTREACHED - relocate_code() does not return */
while(1);
}
void board_init_r(gd_t *id, ulong dest_addr)
{
char *s;
- int i;
ulong size;
static bd_t bd_data;
+ static gd_t gd_data;
init_fnc_t **init_fnc_ptr;
show_boot_progress(0x21);
- gd = id;
+ /* Global data pointer is now writable */
+ gd = &gd_data;
+ memcpy(gd, id, sizeof(gd_t));
+
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
mem_malloc_init((((ulong)dest_addr - CONFIG_SYS_MALLOC_LEN)+3)&~3,
CONFIG_SYS_MALLOC_LEN);
- for (init_fnc_ptr = init_sequence, i=0; *init_fnc_ptr; ++init_fnc_ptr, i++) {
- show_boot_progress(0xa130|i);
-
- if ((*init_fnc_ptr)() != 0) {
+ for (init_fnc_ptr = init_sequence_r; *init_fnc_ptr; ++init_fnc_ptr) {
+ if ((*init_fnc_ptr)() != 0)
hang ();
- }
}
show_boot_progress(0x23);
#include <asm/realmode.h>
-#define REALMODE_BASE ((char*)0x7c0)
#define REALMODE_MAILBOX ((char*)0xe00)
ulong realmode_size = (ulong)&__realmode_size;
/* copy the realmode switch code */
- if (realmode_size > (REALMODE_MAILBOX-REALMODE_BASE)) {
+ if (realmode_size > (REALMODE_MAILBOX - (char *)REALMODE_BASE)) {
printf("realmode switch too large (%ld bytes, max is %d)\n",
- realmode_size, (REALMODE_MAILBOX-REALMODE_BASE));
+ realmode_size,
+ (REALMODE_MAILBOX - (char *)REALMODE_BASE));
return -1;
}
- memcpy(REALMODE_BASE, (void*)realmode_start, realmode_size);
+ memcpy((char *)REALMODE_BASE, (void *)realmode_start, realmode_size);
asm("wbinvd\n");
return 0;
return 0;
}
+static inline int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
static inline int gpio_direction_input(unsigned gpio)
{
writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2));
{
writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2));
}
+
+static inline int gpio_is_valid(int number)
+{
+ return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH;
+}
#else
extern int gpio_request(unsigned gpio, const char *label);
+extern int gpio_free(unsigned gpio);
extern int gpio_direction_input(unsigned gpio);
extern int gpio_direction_output(unsigned gpio, int value);
extern int gpio_get_value(unsigned gpio);
extern void gpio_set_value(unsigned gpio, int value);
+extern int gpio_is_valid(int number);
#endif /* CONFIG_SYS_GPIO_BASE */
#endif /* _ASM_NIOS2_GPIO_H_ */
typedef unsigned short __kernel_uid_t;
typedef unsigned short __kernel_gid_t;
typedef unsigned long __kernel_size_t;
-typedef int __kernel_ssize_t;
+typedef long __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
+/* private structure for mpc83xx pcie hose */
+static struct mpc83xx_pcie_priv {
+ u8 index;
+} pcie_priv[PCIE_MAX_BUSES] = {
+ {
+ /* pcie controller 1 */
+ .index = 0,
+ },
+ {
+ /* pcie controller 2 */
+ .index = 1,
+ },
+};
+
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
{
int bus = PCI_BUS(dev) - hose->first_busno;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- pex83xx_t *pex = &immr->pciexp[bus];
+ struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
+ pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
u32 dev_base = bus << 24 | devfn << 16;
hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
+ hose->priv_data = &pcie_priv[bus];
+
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
#endif
}
- spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
+ spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
sccr = im->clk.sccr;
#endif
lbiu_clk = csb_clk *
- (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
+ (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
}
mem_clk = csb_clk *
- (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
- corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
+ (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
+ corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
+
#if defined(CONFIG_MPC8360)
mem_sec_clk = csb_clk * (1 +
- ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
+ ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
}
#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
- qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
- qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
+ qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
+ qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
brg_clk = qe_clk / 2;
#endif
COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
COBJS-$(CONFIG_P1011) += p1021_serdes.o
COBJS-$(CONFIG_P1012) += p1021_serdes.o
-COBJS-$(CONFIG_P1013) += p1013_serdes.o
+COBJS-$(CONFIG_P1013) += p1022_serdes.o
COBJS-$(CONFIG_P1020) += p1021_serdes.o
COBJS-$(CONFIG_P1021) += p1021_serdes.o
COBJS-$(CONFIG_P1022) += p1022_serdes.o
#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
puts("Work-around for Erratum ESDHC136 enabled\n");
#endif
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
+ puts("Work-around for Erratum ESDHC-A001 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
puts("Work-around for Erratum CPC-A002 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
puts("Work-around for Erratum DDR-A003 enabled\n");
#endif
-
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
+ puts("Work-around for Erratum DDR115 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ puts("Work-around for Erratum DDR111 enabled\n");
+ puts("Work-around for Erratum DDR134 enabled\n");
+#endif
return 0;
}
unsigned int i;
volatile ccsr_ddr_t *ddr;
u32 temp_sdram_cfg;
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
+ u32 total_gb_size_per_controller;
+#endif
switch (ctrl_num) {
case 0:
* when operatiing in 32-bit bus mode with 4-beat bursts,
* This erratum does not affect DDR3 mode, only for DDR2 mode.
*/
-#ifdef CONFIG_MPC8572
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
&& in_be32(&ddr->sdram_cfg) & 0x80000) {
/* set DEBUG_1[31] */
setbits_be32(&ddr->debug[0], 1);
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ /*
+ * This is the combined workaround for DDR111 and DDR134
+ * following the published errata for MPC8572
+ */
+
+ /* 1. Set EEBACR[3] */
+ setbits_be32(&ecm->eebacr, 0x10000000);
+ debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
+
+ /* 2. Set DINIT in SDRAM_CFG_2*/
+ setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_D_INIT);
+ debug("Setting sdram_cfg_2[D_INIT] to 0x%08x\n",
+ in_be32(&ddr->sdram_cfg_2));
+
+ /* 3. Set DEBUG_3[21] */
+ setbits_be32(&ddr->debug[2], 0x400);
+ debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
+
+#endif /* part 1 of the workaound */
/*
* 500 painful micro-seconds must elapse between
temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
asm volatile("sync;isync");
- while (!(in_be32(&ddr->debug[1]) & 0x2))
- ;
/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
- while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
+ while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
udelay(10000); /* throttle polling rate */
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+ /* continue this workaround */
+
+ /* 4. Clear DEBUG3[21] */
+ clrbits_be32(&ddr->debug[2], 0x400);
+ debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));
+
+ /* DDR134 workaround starts */
+ /* A: Clear sdram_cfg_2[odt_cfg] */
+ clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_ODT_CFG_MASK);
+ debug("Clearing SDRAM_CFG2[ODT_CFG] to 0x%08x\n",
+ in_be32(&ddr->sdram_cfg_2));
+
+ /* B: Set DEBUG1[15] */
+ setbits_be32(&ddr->debug[0], 0x10000);
+ debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
+
+ /* C: Set timing_cfg_2[cpo] to 0b11111 */
+ setbits_be32(&ddr->timing_cfg_2, TIMING_CFG_2_CPO_MASK);
+ debug("Setting TMING_CFG_2[CPO] to 0x%08x\n",
+ in_be32(&ddr->timing_cfg_2));
+
+ /* D: Set D6 to 0x9f9f9f9f */
+ out_be32(&ddr->debug[5], 0x9f9f9f9f);
+ debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));
+
+ /* E: Set D7 to 0x9f9f9f9f */
+ out_be32(&ddr->debug[6], 0x9f9f9f9f);
+ debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));
+
+ /* F: Set D2[20] */
+ setbits_be32(&ddr->debug[1], 0x800);
+ debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));
+
+ /* G: Poll on D2[20] until cleared */
+ while (in_be32(&ddr->debug[1]) & 0x800)
+ udelay(10000); /* throttle polling rate */
+
+ /* H: Clear D1[15] */
+ clrbits_be32(&ddr->debug[0], 0x10000);
+ debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));
+
+ /* I: Set sdram_cfg_2[odt_cfg] */
+ setbits_be32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & SDRAM_CFG2_ODT_CFG_MASK);
+ debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
+
+ /* Continuing with the DDR111 workaround */
+ /* 5. Set D2[21] */
+ setbits_be32(&ddr->debug[1], 0x400);
+ debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));
+
+ /* 6. Poll D2[21] until its cleared */
+ while (in_be32(&ddr->debug[1]) & 0x400)
+ udelay(10000); /* throttle polling rate */
+
+ /* 7. Wait for 400ms/GB */
+ total_gb_size_per_controller = 0;
+ for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+ total_gb_size_per_controller +=
+ ((regs->cs[i].bnds & 0xFFFF) >> 6)
+ - (regs->cs[i].bnds >> 22) + 1;
}
+ if (in_be32(&ddr->sdram_cfg) & 0x80000)
+ total_gb_size_per_controller <<= 1;
+ debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
+ udelay(total_gb_size_per_controller * 400000);
+
+ /* 8. Set sdram_cfg_2[dinit] if options requires */
+ setbits_be32(&ddr->sdram_cfg_2,
+ regs->ddr_sdram_cfg_2 & SDRAM_CFG2_D_INIT);
+ debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
+
+ /* 9. Poll until dinit is cleared */
+ while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
+ udelay(10000);
+
+ /* 10. Clear EEBACR[3] */
+ clrbits_be32(&ecm->eebacr, 10000000);
+ debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));
+#endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
}
* tAXPD=1, need design to confirm.
*/
int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+ unsigned int data_rate = fsl_ddr_get_mem_data_rate();
tmrd_mclk = 4;
/* set the turnaround time */
trwt_mclk = 1;
+ if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
+ twrt_mclk = 1;
if (popts->dynamic_power == 0) { /* powerdown is not used */
act_pd_exit_mclk = 1;
extern unsigned int mclk_to_picos(unsigned int mclk);
extern unsigned int get_memory_clk_period_ps(void);
extern unsigned int picos_to_mclk(unsigned int picos);
-
+extern unsigned int fsl_ddr_get_mem_data_rate(void);
#endif
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_SYS_FSL_ERRATUM_DDR_115
+#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
#elif defined(CONFIG_P1010)
#define CONFIG_MAX_CPUS 1
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#elif defined(CONFIG_P2020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_FSL_SEC_COMPAT 2
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
#elif defined(CONFIG_PPC_P2040)
#define CONFIG_MAX_CPUS 4
#define SDRAM_CFG_2T_EN 0x00008000
#define SDRAM_CFG_BI 0x00000001
+#define SDRAM_CFG2_D_INIT 0x00000010
+#define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
+
+#define TIMING_CFG_2_CPO_MASK 0x0F800000
+
#if defined(CONFIG_P4080)
#define RD_TO_PRE_MASK 0xf
#define RD_TO_PRE_SHIFT 13
#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
unsigned long kbd_status;
#endif
+#ifdef CONFIG_SYS_FPGA_COUNT
+ unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
+#endif
#if defined(CONFIG_WD_MAX_RATE)
unsigned long long wdt_last; /* trace watch-dog triggering rate */
#endif
/* led_pio.s1 is a altera_avalon_pio */
#define LED_PIO_BASE 0x82120870
+#define LED_PIO_WIDTH 8
/* high_res_timer.s1 is a altera_avalon_timer */
#define CONFIG_SYS_TIMER_BASE 0x82120820
#ifndef CONFIG_SYS_GPIO_BASE
#define ALTERA_PIO_BASE LED_PIO_BASE
+#define ALTERA_PIO_WIDTH LED_PIO_WIDTH
#define ALTERA_PIO_DATA (ALTERA_PIO_BASE + 0)
#define ALTERA_PIO_DIR (ALTERA_PIO_BASE + 4)
static u32 pio_data_reg;
return 0;
}
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
int gpio_direction_input(unsigned gpio)
{
u32 mask = 1 << gpio;
pio_data_reg &= ~mask;
writel(pio_data_reg, ALTERA_PIO_DATA);
}
+
+int gpio_is_valid(int number)
+{
+ return ((unsigned)number) < ALTERA_PIO_WIDTH;
+}
#endif
# MA 02111-1307 USA
#
-CONFIG_SYS_TEXT_BASE = 0x06000000
-CFLAGS_common/dlmalloc.o += -Wa,--no-warn -fno-strict-aliasing
-PLATFORM_RELFLAGS += -fvisibility=hidden
-PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
-PLATFORM_LDFLAGS += -pic --emit-relocs -Bsymbolic -Bsymbolic-functions
+LDPPFLAGS += -DFLASH_SIZE=0x40000
DECLARE_GLOBAL_DATA_PTR;
-#undef SC520_CDP_DEBUG
-
-#ifdef SC520_CDP_DEBUG
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
-unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
-
static void enet_timer_isr(void);
static void enet_toggle_run_led(void);
-
-void init_sc520_enet (void)
-{
- /* Set CPU Speed to 100MHz */
- writeb(0x01, &sc520_mmcr->cpuctl);
-
- /* wait at least one millisecond */
- asm("movl $0x2000,%%ecx\n"
- "0: pushl %%ecx\n"
- "popl %%ecx\n"
- "loop 0b\n": : : "ecx");
-
- /* turn on the SDRAM write buffer */
- writeb(0x11, &sc520_mmcr->dbctl);
-
- /* turn on the cache and disable write through */
- asm("movl %%cr0, %%eax\n"
- "andl $0x9fffffff, %%eax\n"
- "movl %%eax, %%cr0\n" : : : "eax");
-}
+static void enet_setup_pars(void);
/*
* Miscellaneous platform dependent initializations
*/
int board_early_init_f(void)
{
- init_sc520_enet();
-
- writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
- writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
- writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
- writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
- writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
- writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
- writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
-
- writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
- writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
- writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
- writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
- writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
- writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
- writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
-
- writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
- writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
- writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
- writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
- writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
- writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
- writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
- writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
- writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
- writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
- writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
- writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
-/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
-/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+ u16 pio_out_cfg = 0x0000;
+
+ /* Configure General Purpose Bus timing */
+ writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
+ writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
+ writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
+ writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
+ writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
+ writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
+ writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
+
+ /* Configure Programmable Input/Output Pins */
+ writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
+ writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
+ writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
+ writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
+ writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
+ writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
+
+ /*
+ * Turn off top board
+ * Set StrataFlash chips to 16-bit width
+ * Set StrataFlash chips to normal (non reset/power down) mode
+ */
+ pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
+ writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
+
+ /* Turn off auxiliary power output */
+ writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
+
+ /* Clear FPGA program mode */
+ writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
+
+ enet_setup_pars();
/* Disable Watchdog */
writew(0x3333, &sc520_mmcr->wdtmrctl);
writew(0x0000, &sc520_mmcr->wdtmrctl);
/* Chip Select Configuration */
- writew(0x0033, &sc520_mmcr->bootcsctl);
- writew(0x0615, &sc520_mmcr->romcs1ctl);
- writew(0x0615, &sc520_mmcr->romcs2ctl);
+ writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
+ writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
+ writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
+
+ writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
+ writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
+ writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
+
+ writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
+ writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
- writeb(0x00, &sc520_mmcr->adddecctl);
- writeb(0x07, &sc520_mmcr->uart1ctl);
- writeb(0x07, &sc520_mmcr->uart2ctl);
- writeb(0x06, &sc520_mmcr->sysarbctl);
- writew(0x0003, &sc520_mmcr->sysarbmenb);
+ /* enable posted-writes */
+ writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
return 0;
}
+static void enet_setup_pars(void)
+{
+ /*
+ * PARs 11 and 12 are 2MB SRAM @ 0x19000000
+ *
+ * These are setup now because older version of U-Boot have them
+ * mapped to a different PAR which gets clobbered which prevents
+ * using SRAM for warm-booting a new image
+ */
+ writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
+ writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
+
+ /* PARs 0 and 1 are Compact Flash slots (4kB each) */
+ writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
+ writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
+
+ /* PAR 2 is used for Cache-As-RAM */
+
+ /*
+ * PARs 5 through 8 are additional NS16550 UARTS
+ * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
+ */
+ writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
+ writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
+ writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
+ writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
+
+ /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
+ writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
+ writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
+
+ /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
+ writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
+
+ /*
+ * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
+ * Already configured in board_init16 (eNET_start16.S)
+ *
+ * PAR 15 is Boot ROM
+ * Already configured in board_init16 (eNET_start16.S)
+ */
+}
+
+
int board_early_init_r(void)
{
/* CPU Speed to 100MHz */
return 0;
}
-int dram_init(void)
-{
- init_sc520_dram();
- return 0;
-}
-
void show_boot_progress(int val)
{
uchar led_mask;
outb(0x00, LED_LATCH_ADDRESS);
- register_timer_isr (enet_timer_isr);
+ register_timer_isr(enet_timer_isr);
printf("Serck Controls eNET\n");
return 0;
}
-ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
if (banknum == 0) { /* non-CFI boot flash */
info->portwidth = FLASH_CFI_8BIT;
info->chipwidth = FLASH_CFI_BY8;
info->interface = FLASH_CFI_X8;
return 1;
- } else
+ } else {
return 0;
+ }
}
int board_eth_init(bd_t *bis)
*/
writew(0x0000,&sc520_mmcr->intpinpol);
- /* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */
+ /*
+ * PIT 0 -> IRQ0
+ * RTC -> IRQ8
+ * FP error -> IRQ13
+ * UART1 -> IRQ4
+ * UART2 -> IRQ3
+ */
writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
+ writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
+ writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
/* Disable all other interrupt sources */
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]); /* disable PCI INT A */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]); /* disable PCI INT B */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]); /* disable PCI INT C */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]); /* disable PCI INT D */
- writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap); /* disable DMA INT */
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
/* No 32-bit board specific initialisation */
jmp early_board_init_ret
-.globl cpu_halt_asm
-cpu_halt_asm:
- movb $0x0f, %al
- movw $LED_LATCH_ADDRESS, %dx
- outb %al, %dx
- hlt
- jmp cpu_halt_asm
/* #include <asm/ic/sc520_defs.h> */
+#include "config.h"
#include "hardware.h"
+#include <asm/ic/sc520.h>
.text
.section .start16, "ax"
movw %ax, %ds
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
- movl $0x00c0, %edi /* SC520_PAR14 */
- movl $0x8bfff800, %eax /* TODO: Check this */
+ movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi
+ movl $CONFIG_SYS_SC520_BOOTCS_PAR, %eax
movl %eax, (%di)
/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
- movl $0x00c4, %edi /* SC520_PAR15 */
- movl $0x38201000, %eax
+ movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi
+ movl $CONFIG_SYS_SC520_LLIO_PAR, %eax
movl %eax, (%di)
- /* Disable SDRAM write buffer */
- movw $0x0040, %di /* SC520_DBCTL */
- xorw %ax, %ax
- movb %al, (%di)
-
/* Disabe MMCR alias */
movw $0xfffc, %dx
movl $0x000000cb, %eax
#else
memcpy(e.id, "CCID", sizeof(e.id));
#endif
+ update_crc();
return 0;
}
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
+#include <asm/global_data.h>
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
#define REFLECTION_TESTPATTERN 0xdede
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
+DECLARE_GLOBAL_DATA_PTR;
+
+int get_fpga_state(unsigned dev)
+{
+ return gd->fpga_state[dev];
+}
+
+void print_fpga_state(unsigned dev)
+{
+ if (gd->fpga_state[dev] & FPGA_STATE_DONE_FAILED)
+ puts(" Waiting for FPGA-DONE timed out.\n");
+ if (gd->fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED)
+ puts(" FPGA reflection test failed.\n");
+}
+
int board_early_init_f(void)
{
+ unsigned k;
+ unsigned ctr;
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ gd->fpga_state[k] = 0;
+
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical */
/*
* wait for fpga-done
- * fail ungraceful if fpga is not configuring properly
*/
- while (!(in_le16((void *)LATCH2_BASE) & 0x0010))
- ;
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ctr = 0;
+ while (!(in_le16((void *)LATCH2_BASE)
+ & CONFIG_SYS_FPGA_DONE(k))) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |= FPGA_STATE_DONE_FAILED;
+ break;
+ }
+ }
+ }
/*
* setup io-latches for boot (stop reset)
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
- /*
- * wait for fpga out of reset
- * fail ungraceful if fpga is not working properly
- */
- while (1) {
- fpga_set_reg(CONFIG_SYS_FPGA_RFL_LOW, REFLECTION_TESTPATTERN);
- if (fpga_get_reg(CONFIG_SYS_FPGA_RFL_HIGH) ==
- REFLECTION_TESTPATTERN_INV)
- break;
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(k);
+ /*
+ * wait for fpga out of reset
+ */
+ ctr = 0;
+ while (1) {
+ out_le16(&fpga->reflection_low,
+ REFLECTION_TESTPATTERN);
+ if (in_le16(&fpga->reflection_high) ==
+ REFLECTION_TESTPATTERN_INV)
+ break;
+ udelay(100000);
+ if (ctr++ > 5) {
+ gd->fpga_state[k] |=
+ FPGA_STATE_REFLECTION_FAILED;
+ break;
+ }
+ }
}
return 0;
COBJS-$(CONFIG_IO) += io.o
COBJS-$(CONFIG_IOCON) += iocon.o
+COBJS-$(CONFIG_DLVISION_10G) += dlvision-10g.o
COBJS := $(BOARD).o $(COBJS-y)
SOBJS =
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/ppc4xx-gpio.h>
+
+#include <gdsys_fpga.h>
+
+#include "../common/osd.h"
+
+enum {
+ UNITTYPE_VIDEO_USER = 0,
+ UNITTYPE_MAIN_USER = 1,
+ UNITTYPE_VIDEO_SERVER = 2,
+ UNITTYPE_MAIN_SERVER = 3,
+};
+
+enum {
+ HWVER_101 = 0,
+ HWVER_110 = 1,
+};
+
+enum {
+ AUDIO_NONE = 0,
+ AUDIO_TX = 1,
+ AUDIO_RX = 2,
+ AUDIO_RXTX = 3,
+};
+
+enum {
+ SYSCLK_156250 = 2,
+};
+
+enum {
+ RAM_NONE = 0,
+ RAM_DDR2_32 = 1,
+ RAM_DDR2_64 = 2,
+};
+
+static void print_fpga_info(unsigned dev)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(dev);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
+ unsigned unit_type;
+ unsigned hardware_version;
+ unsigned feature_compression;
+ unsigned feature_rs232;
+ unsigned feature_audio;
+ unsigned feature_sysclock;
+ unsigned feature_ramconfig;
+ unsigned feature_carrier_speed;
+ unsigned feature_carriers;
+ unsigned feature_video_channels;
+ int fpga_state = get_fpga_state(dev);
+
+ printf("FPGA%d: ", dev);
+
+ hardware_version = versions & 0x000f;
+
+ if (fpga_state
+ && !((hardware_version == HWVER_101)
+ && (fpga_state == FPGA_STATE_DONE_FAILED))) {
+ puts("not available\n");
+ print_fpga_state(dev);
+ return;
+ }
+
+ unit_type = (versions >> 4) & 0x000f;
+ hardware_version = versions & 0x000f;
+ feature_compression = (fpga_features >> 13) & 0x0003;
+ feature_rs232 = fpga_features & (1<<11);
+ feature_audio = (fpga_features >> 9) & 0x0003;
+ feature_sysclock = (fpga_features >> 7) & 0x0003;
+ feature_ramconfig = (fpga_features >> 5) & 0x0003;
+ feature_carrier_speed = fpga_features & (1<<4);
+ feature_carriers = (fpga_features >> 2) & 0x0003;
+ feature_video_channels = fpga_features & 0x0003;
+
+ switch (unit_type) {
+ case UNITTYPE_VIDEO_USER:
+ printf("Videochannel Userside");
+ break;
+
+ case UNITTYPE_MAIN_USER:
+ printf("Mainchannel Userside");
+ break;
+
+ case UNITTYPE_VIDEO_SERVER:
+ printf("Videochannel Serverside");
+ break;
+
+ case UNITTYPE_MAIN_SERVER:
+ printf("Mainchannel Serverside");
+ break;
+
+ default:
+ printf("UnitType %d(not supported)", unit_type);
+ break;
+ }
+
+ switch (hardware_version) {
+ case HWVER_101:
+ printf(" HW-Ver 1.01\n");
+ break;
+
+ case HWVER_110:
+ printf(" HW-Ver 1.10\n");
+ break;
+
+ default:
+ printf(" HW-Ver %d(not supported)\n",
+ hardware_version);
+ break;
+ }
+
+ printf(" FPGA V %d.%02d, features:",
+ fpga_version / 100, fpga_version % 100);
+
+ printf(" %sRS232", feature_rs232 ? "" : "no ");
+
+ switch (feature_audio) {
+ case AUDIO_NONE:
+ printf(", no audio");
+ break;
+
+ case AUDIO_TX:
+ printf(", audio tx");
+ break;
+
+ case AUDIO_RX:
+ printf(", audio rx");
+ break;
+
+ case AUDIO_RXTX:
+ printf(", audio rx+tx");
+ break;
+
+ default:
+ printf(", audio %d(not supported)", feature_audio);
+ break;
+ }
+
+ switch (feature_sysclock) {
+ case SYSCLK_156250:
+ printf(", clock 156.25 MHz");
+ break;
+
+ default:
+ printf(", clock %d(not supported)", feature_sysclock);
+ break;
+ }
+
+ puts(",\n ");
+
+ switch (feature_ramconfig) {
+ case RAM_NONE:
+ printf("no RAM");
+ break;
+
+ case RAM_DDR2_32:
+ printf("RAM 32 bit DDR2");
+ break;
+
+ case RAM_DDR2_64:
+ printf("RAM 64 bit DDR2");
+ break;
+
+ default:
+ printf("RAM %d(not supported)", feature_ramconfig);
+ break;
+ }
+
+ printf(", %d carrier(s) %s", feature_carriers,
+ feature_carrier_speed ? "10 Gbit/s" : "of unknown speed");
+
+ printf(", %d video channel(s)\n", feature_video_channels);
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ unsigned k;
+ char *s = getenv("serial#");
+
+ printf("Board: ");
+
+ printf("DLVision 10G");
+
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+
+ puts("\n");
+
+ for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
+ print_fpga_info(k);
+
+ return 0;
+}
+
+int last_stage_init(void)
+{
+ unsigned k;
+
+ for (k = 0; k < CONFIG_SYS_OSD_SCREENS; ++k)
+ if (!get_fpga_state(k)
+ || (get_fpga_state(k) == FPGA_STATE_DONE_FAILED))
+ osd_probe(k);
+
+ return 0;
+}
#include <miiphy.h>
-#include "../common/fpga.h"
+#include <gdsys_fpga.h>
#define PHYREG_CONTROL 0
#define PHYREG_PAGE_ADDRESS 22
#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
-enum {
- REG_VERSIONS = 0x0002,
- REG_FPGA_FEATURES = 0x0004,
- REG_FPGA_VERSION = 0x0006,
- REG_QUAD_SERDES_RESET = 0x0012,
-};
-
enum {
UNITTYPE_CCD_SWITCH = 1,
};
*/
int checkboard(void)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
char *s = getenv("serial#");
- u16 versions = fpga_get_reg(REG_VERSIONS);
- u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
- u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
unsigned unit_type;
unsigned hardware_version;
unsigned feature_channels;
*/
int last_stage_init(void)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
unsigned int k;
miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
configure_gbit_phy(k);
/* take fpga serdes blocks out of reset */
- fpga_set_reg(REG_QUAD_SERDES_RESET, 0);
+ out_le16(&fpga->quad_serdes_reset, 0);
return 0;
}
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
-#include "../common/fpga.h"
-#include "../common/osd.h"
+#include <gdsys_fpga.h>
-enum {
- REG_VERSIONS = 0x0002,
- REG_FPGA_VERSION = 0x0004,
- REG_FPGA_FEATURES = 0x0006,
-};
+#include "../common/osd.h"
enum {
UNITTYPE_MAIN_SERVER = 0,
*/
int checkboard(void)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(0);
char *s = getenv("serial#");
- u16 versions = fpga_get_reg(REG_VERSIONS);
- u16 fpga_version = fpga_get_reg(REG_FPGA_VERSION);
- u16 fpga_features = fpga_get_reg(REG_FPGA_FEATURES);
+ u16 versions = in_le16(&fpga->versions);
+ u16 fpga_version = in_le16(&fpga->fpga_version);
+ u16 fpga_features = in_le16(&fpga->fpga_features);
unsigned unit_type;
unsigned hardware_version;
unsigned feature_compression;
int last_stage_init(void)
{
- return osd_probe();
+ return osd_probe(0);
}
/*
*/
void fpga_gpio_set(int pin)
{
- out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x18), pin);
+ out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
}
void fpga_gpio_clear(int pin)
{
- out_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x16), pin);
+ out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
}
int fpga_gpio_get(int pin)
{
- return in_le16((void *)(CONFIG_SYS_FPGA_BASE + 0x14)) & pin;
+ return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
}
COBJS-$(CONFIG_IO) += miiphybb.o
COBJS-$(CONFIG_IOCON) += osd.o
+COBJS-$(CONFIG_DLVISION_10G) += osd.o
COBJS := $(COBJS-y)
SOBJS =
+++ /dev/null
-/*
- * (C) Copyright 2010
- * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _FPGA_H_
-#define _FPGA_H_
-
-static inline u16 fpga_get_reg(unsigned reg)
-{
- return in_le16((void *)(CONFIG_SYS_FPGA_BASE + reg));
-}
-
-static inline void fpga_set_reg(unsigned reg, u16 val)
-{
- return out_le16((void *)(CONFIG_SYS_FPGA_BASE + reg), val);
-}
-
-#endif
#include <i2c.h>
#include <asm/io.h>
-#include "fpga.h"
+#include <gdsys_fpga.h>
#define CH7301_I2C_ADDR 0x75
+#define ICS8N3QV01_I2C_ADDR 0x6E
+#define ICS8N3QV01_FREF 114285
+
+#define SIL1178_MASTER_I2C_ADDRESS 0x38
+#define SIL1178_SLAVE_I2C_ADDRESS 0x39
+
#define PIXCLK_640_480_60 25180000
#define BASE_WIDTH 32
#define BASE_HEIGHT 16
#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
-enum {
- REG_CONTROL = 0x0010,
- REG_MPC3W_CONTROL = 0x001a,
- REG_VIDEOCONTROL = 0x0042,
- REG_OSDVERSION = 0x0100,
- REG_OSDFEATURES = 0x0102,
- REG_OSDCONTROL = 0x0104,
- REG_XY_SIZE = 0x0106,
- REG_VIDEOMEM = 0x0800,
-};
-
enum {
CH7301_CM = 0x1c, /* Clock Mode Register */
CH7301_IC = 0x1d, /* Input Clock Register */
CH7301_DSP = 0x56, /* DVI Sync polarity Register */
};
+#if defined(CONFIG_SYS_ICS8N3QV01) || defined(CONFIG_SYS_SIL1178)
+static void fpga_iic_write(unsigned screen, u8 slave, u8 reg, u8 data)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+ ihs_i2c_t *i2c = &fpga->i2c;
+
+ while (in_le16(&fpga->extended_interrupt) & (1 << 12))
+ ;
+ out_le16(&i2c->write_mailbox_ext, reg | (data << 8));
+ out_le16(&i2c->write_mailbox, 0xc400 | (slave << 1));
+}
+
+static u8 fpga_iic_read(unsigned screen, u8 slave, u8 reg)
+{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+ ihs_i2c_t *i2c = &fpga->i2c;
+ unsigned int ctr = 0;
+
+ while (in_le16(&fpga->extended_interrupt) & (1 << 12))
+ ;
+ out_le16(&fpga->extended_interrupt, 1 << 14);
+ out_le16(&i2c->write_mailbox_ext, reg);
+ out_le16(&i2c->write_mailbox, 0xc000 | (slave << 1));
+ while (!(in_le16(&fpga->extended_interrupt) & (1 << 14))) {
+ udelay(100000);
+ if (ctr++ > 5) {
+ printf("iic receive timeout\n");
+ break;
+ }
+ }
+ return in_le16(&i2c->read_mailbox_ext) >> 8;
+}
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
unsigned int *post_div, unsigned int *feedback_div)
{
*feedback_div = m;
}
-static void mpc92469ac_set(unsigned int fout)
+static void mpc92469ac_set(unsigned screen, unsigned int fout)
{
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
unsigned int n;
unsigned int m;
unsigned int bitval = 0;
break;
}
- fpga_set_reg(REG_MPC3W_CONTROL, (bitval << 9) | m);
+ out_le16(&fpga->mpc3w_control, (bitval << 9) | m);
}
+#endif
-static int osd_write_videomem(unsigned offset, u16 *data, size_t charcount)
+#ifdef CONFIG_SYS_ICS8N3QV01
+static void ics8n3qv01_calc_parameters(unsigned int fout,
+ unsigned int *_mint, unsigned int *_mfrac,
+ unsigned int *_n)
{
+ unsigned int n;
+ unsigned int foutiic;
+ unsigned int fvcoiic;
+ unsigned int mint;
+ unsigned long long mfrac;
+
+ n = 2550000000U / fout;
+ if ((n & 1) && (n > 5))
+ n -= 1;
+
+ foutiic = fout - (fout / 10000);
+ fvcoiic = foutiic * n;
+
+ mint = fvcoiic / 114285000;
+ if ((mint < 17) || (mint > 63))
+ printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
+
+ mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
+ / 114285000LL;
+
+ *_mint = mint;
+ *_mfrac = mfrac;
+ *_n = n;
+}
+
+static void ics8n3qv01_set(unsigned screen, unsigned int fout)
+{
+ unsigned int n;
+ unsigned int mint;
+ unsigned int mfrac;
+ u8 reg0, reg4, reg8, reg12, reg18, reg20;
+
+ ics8n3qv01_calc_parameters(fout, &mint, &mfrac, &n);
+
+ reg0 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
+ reg0 |= (mint & 0x1f) << 1;
+ reg0 |= (mfrac >> 17) & 0x01;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 0, reg0);
+
+ reg4 = mfrac >> 9;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 4, reg4);
+
+ reg8 = mfrac >> 1;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 8, reg8);
+
+ reg12 = mfrac << 7;
+ reg12 |= n & 0x7f;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 12, reg12);
+
+ reg18 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 18) & 0x03;
+ reg18 |= 0x20;
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 18, reg18);
+
+ reg20 = fpga_iic_read(screen, ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
+ reg20 |= mint & (1 << 5);
+ fpga_iic_write(screen, ICS8N3QV01_I2C_ADDR, 20, reg20);
+}
+#endif
+
+static int osd_write_videomem(unsigned screen, unsigned offset,
+ u16 *data, size_t charcount)
+{
+ ihs_fpga_t *fpga =
+ (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
unsigned int k;
for (k = 0; k < charcount; ++k) {
if (offset + k >= BUFSIZE)
return -1;
- fpga_set_reg(REG_VIDEOMEM + 2 * (offset + k), data[k]);
+ out_le16(&fpga->videomem + offset + k, data[k]);
}
return charcount;
static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned x;
- unsigned y;
- unsigned charcount;
- unsigned len;
- u8 color;
- unsigned int k;
- u16 buf[BUFSIZE];
- char *text;
-
- if (argc < 5) {
- return cmd_usage(cmdtp);
+ unsigned screen;
+
+ for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+ unsigned x;
+ unsigned y;
+ unsigned charcount;
+ unsigned len;
+ u8 color;
+ unsigned int k;
+ u16 buf[BUFSIZE];
+ char *text;
+ int res;
+
+ if (argc < 5) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ color = simple_strtoul(argv[3], NULL, 16);
+ text = argv[4];
+ charcount = strlen(text);
+ len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+
+ for (k = 0; k < len; ++k)
+ buf[k] = (text[k] << 8) | color;
+
+ res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
+ if (res < 0)
+ return res;
}
- x = simple_strtoul(argv[1], NULL, 16);
- y = simple_strtoul(argv[2], NULL, 16);
- color = simple_strtoul(argv[3], NULL, 16);
- text = argv[4];
- charcount = strlen(text);
- len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
-
- for (k = 0; k < len; ++k)
- buf[k] = (text[k] << 8) | color;
-
- return osd_write_videomem(y * BASE_WIDTH + x, buf, len);
+ return 0;
}
-int osd_probe(void)
+int osd_probe(unsigned screen)
{
- u8 value;
- u16 version = fpga_get_reg(REG_OSDVERSION);
- u16 features = fpga_get_reg(REG_OSDFEATURES);
+ ihs_fpga_t *fpga = (ihs_fpga_t *) CONFIG_SYS_FPGA_BASE(screen);
+ ihs_osd_t *osd = &fpga->osd;
+ u16 version = in_le16(&osd->version);
+ u16 features = in_le16(&osd->features);
unsigned width;
unsigned height;
+ u8 value;
width = ((features & 0x3f00) >> 8) + 1;
height = (features & 0x001f) + 1;
- printf("OSD: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
- version/100, version%100, width, height);
+ printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+ screen, version/100, version%100, width, height);
+#ifdef CONFIG_SYS_CH7301
value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
if (value != 0x17) {
printf(" Probing CH7301 failed, DID %02x\n", value);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
+#endif
+
+#ifdef CONFIG_SYS_MPC92469AC
+ mpc92469ac_set(screen, PIXCLK_640_480_60);
+#endif
- mpc92469ac_set(PIXCLK_640_480_60);
- fpga_set_reg(REG_VIDEOCONTROL, 0x0002);
- fpga_set_reg(REG_OSDCONTROL, 0x0049);
+#ifdef CONFIG_SYS_ICS8N3QV01
+ ics8n3qv01_set(screen, PIXCLK_640_480_60);
+#endif
- fpga_set_reg(REG_XY_SIZE, ((32 - 1) << 8) | (16 - 1));
+#ifdef CONFIG_SYS_SIL1178
+ value = fpga_iic_read(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x02);
+ if (value != 0x06) {
+ printf(" Probing CH7301 SIL1178, DEV_IDL %02x\n", value);
+ return -1;
+ }
+ /* magic initialization sequence adapted from datasheet */
+ fpga_iic_write(screen, SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
+ fpga_iic_write(screen, SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
+#endif
+
+ out_le16(&fpga->videocontrol, 0x0002);
+ out_le16(&osd->control, 0x0049);
+
+ out_le16(&osd->xy_size, ((32 - 1) << 8) | (16 - 1));
return 0;
}
int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- unsigned x;
- unsigned y;
- unsigned k;
- u16 buffer[BASE_WIDTH];
- char *rp;
- u16 *wp = buffer;
- unsigned count = (argc > 4) ? simple_strtoul(argv[4], NULL, 16) : 1;
-
- if ((argc < 4) || (strlen(argv[3]) % 4)) {
- return cmd_usage(cmdtp);
- }
-
- x = simple_strtoul(argv[1], NULL, 16);
- y = simple_strtoul(argv[2], NULL, 16);
- rp = argv[3];
-
-
- while (*rp) {
- char substr[5];
-
- memcpy(substr, rp, 4);
- substr[4] = 0;
- *wp = simple_strtoul(substr, NULL, 16);
-
- rp += 4;
- wp++;
- if (wp - buffer > BASE_WIDTH)
- break;
- }
-
- for (k = 0; k < count; ++k) {
- unsigned offset = y * BASE_WIDTH + x + k * (wp - buffer);
- osd_write_videomem(offset, buffer, wp - buffer);
+ unsigned screen;
+
+ for (screen = 0; screen < CONFIG_SYS_OSD_SCREENS; ++screen) {
+ unsigned x;
+ unsigned y;
+ unsigned k;
+ u16 buffer[BASE_WIDTH];
+ char *rp;
+ u16 *wp = buffer;
+ unsigned count = (argc > 4) ?
+ simple_strtoul(argv[4], NULL, 16) : 1;
+
+ if ((argc < 4) || (strlen(argv[3]) % 4)) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ x = simple_strtoul(argv[1], NULL, 16);
+ y = simple_strtoul(argv[2], NULL, 16);
+ rp = argv[3];
+
+
+ while (*rp) {
+ char substr[5];
+
+ memcpy(substr, rp, 4);
+ substr[4] = 0;
+ *wp = simple_strtoul(substr, NULL, 16);
+
+ rp += 4;
+ wp++;
+ if (wp - buffer > BASE_WIDTH)
+ break;
+ }
+
+ for (k = 0; k < count; ++k) {
+ unsigned offset =
+ y * BASE_WIDTH + x + k * (wp - buffer);
+ osd_write_videomem(screen, offset, buffer,
+ wp - buffer);
+ }
}
return 0;
#ifndef _OSD_H_
#define _OSD_H_
-int osd_probe(void);
+int osd_probe(unsigned screen);
#endif
ip04 blackfin blackfin
tcm-bf518 blackfin blackfin
tcm-bf537 blackfin blackfin
-eNET i386 i386 - - sc520
+eNET i386 i386 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000
+eNET_SRAM i386 i386 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000
idmr m68k mcf52x2
TASREG m68k mcf52x2 tasreg esd
M5208EVBE m68k mcf52x2 m5208evbe freescale
MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS
MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT
MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND
-P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011
-P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,NAND
-P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SDCARD
-P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011,SPIFLASH
+P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB
+P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND
+P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD
+P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH
P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB
P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND
P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD
-P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020,SPIFLASH
+P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH
P1022DS powerpc mpc85xx p1022ds freescale
-P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010
-P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,NAND
-P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SDCARD
-P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010,SPIFLASH
+P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB
+P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND
+P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD
+P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH
P2020DS powerpc mpc85xx p2020ds freescale
P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT
P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2
-P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020
-P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,NAND
-P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD
-P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SPIFLASH
+P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB
+P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND
+P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD
+P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH
P4080DS powerpc mpc85xx corenet_ds freescale
mpq101 powerpc mpc85xx mpq101 mercury - mpq101
stxgp3 powerpc mpc85xx stxgp3 stx
WUH405 powerpc ppc4xx wuh405 esd
devconcenter powerpc ppc4xx intip gdsys - intip:DEVCONCENTER
dlvision powerpc ppc4xx - gdsys
+dlvision-10g powerpc ppc4xx 405ep gdsys
gdppc440etx powerpc ppc4xx - gdsys
intip powerpc ppc4xx intip gdsys - intip:INTIB
io powerpc ppc4xx 405ep gdsys
return NULL;
}
- puts("Gzipped BMP image detected!\n");
+ debug("Gzipped BMP image detected!\n");
return bmp;
}
return 0;
}
+
#ifdef CONFIG_ENV_OFFSET_REDUND
+static unsigned char env_flags;
+
int saveenv(void)
{
env_t env_new;
return 1;
}
env_new.crc = crc32(0, env_new.data, ENV_SIZE);
- ++env_new.flags; /* increase the serial */
+ env_new.flags = ++env_flags; /* increase the serial */
if(gd->env_valid == 1) {
puts("Erasing redundant NAND...\n");
else
ep = tmp_env2;
+ env_flags = ep->flags;
env_import((char *)ep, 0);
free(tmp_env1);
#include <asm/4xx_pci.h>
#endif
-#undef USB_DEBUG
+#ifdef DEBUG
+#define USB_DEBUG
+#define USB_HUB_DEBUG
+#endif
#ifdef USB_DEBUG
#define USB_PRINTF(fmt, args...) printf(fmt , ##args)
* Probes device for being a hub and configurate it
*/
-#undef USB_HUB_DEBUG
-
#ifdef USB_HUB_DEBUG
#define USB_HUB_PRINTF(fmt, args...) printf(fmt , ##args)
#else
hub->desc.DeviceRemovable[i] = descriptor->DeviceRemovable[i];
for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
- hub->desc.DeviceRemovable[i] = descriptor->PortPowerCtrlMask[i];
+ hub->desc.PortPowerCtrlMask[i] = descriptor->PortPowerCtrlMask[i];
dev->maxchild = descriptor->bNbrPorts;
USB_HUB_PRINTF("%d ports detected\n", dev->maxchild);
if (timeout < 0)
timeout = 0;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+ if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+ timeout++;
+#endif
+
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
return 0;
#include <command.h>
#include <rtc.h>
+#ifdef __I386__
+#include <asm/io.h>
+#define in8(p) inb(p)
+#define out8(p, v) outb(v, p)
+#endif
+
#if defined(CONFIG_CMD_DATE)
static uchar rtc_read (uchar reg);
{
}
+void spi_set_speed(struct spi_slave *slave, uint hz)
+{
+ /* altera spi core does not support programmable speed */
+}
+
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
*/
#include <config_cmd_default.h>
+#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET 0x3000
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_BUS_NUM 1
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_405EP 1 /* this is a PPC405 CPU */
+#define CONFIG_4xx 1 /* member of PPC4xx family */
+#define CONFIG_DLVISION_10G 1 /* on a DLVision-10G board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
+
+/*
+ * Include common defines/options for all AMCC eval boards
+ */
+#define CONFIG_HOSTNAME dlvsion-10g
+#define CONFIG_IDENT_STRING " dlvision-10g 0.01"
+#include "amcc-common.h"
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f */
+#define CONFIG_LAST_STAGE_INIT
+
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+
+/*
+ * Configure PLL
+ */
+#define PLLMR0_DEFAULT PLLMR0_266_133_66
+#define PLLMR1_DEFAULT PLLMR1_266_133_66
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
+
+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
+
+/*
+ * Default environment variables
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_AMCC_DEF_ENV \
+ CONFIG_AMCC_DEF_ENV_POWERPC \
+ CONFIG_AMCC_DEF_ENV_NOR_UPD \
+ "kernel_addr=fc000000\0" \
+ "fdt_addr=fc1e0000\0" \
+ "ramdisk_addr=fc200000\0" \
+ ""
+
+#define CONFIG_PHY_ADDR 4 /* PHY address */
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
+#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
+
+/*
+ * Commands additional to the ones defined in amcc-common.h
+ */
+#define CONFIG_CMD_CACHE
+#undef CONFIG_CMD_EEPROM
+
+/*
+ * SDRAM configuration (please see cpu/ppc/sdram.[ch])
+ */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
+/* SDRAM timings used in datasheet */
+#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
+#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
+#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
+#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
+#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
+
+/*
+ * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
+ * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
+ * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
+ * The Linux BASE_BAUD define should match this configuration.
+ * baseBaud = cpuClock/(uartDivisor*16)
+ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
+ * set Linux BASE_BAUD to 403200.
+ */
+#define CONFIG_CONS_INDEX 1 /* Use UART0 */
+#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
+#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
+#define CONFIG_SYS_BASE_BAUD 691200
+
+/*
+ * I2C stuff
+ */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* Temp sensor/hwmon/dtt */
+#define CONFIG_DTT_LM63 1 /* National LM63 */
+#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
+#define CONFIG_DTT_PWM_LOOKUPTABLE \
+ { { 40, 10 }, { 50, 20 }, { 60, 40 } }
+#define CONFIG_DTT_TACH_LIMIT 0xa10
+
+/* EBC peripherals */
+
+#define CONFIG_SYS_FLASH_BASE 0xFC000000
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
+#define CONFIG_SYS_FPGA1_BASE 0x7f200000
+#define CONFIG_SYS_LATCH_BASE 0x7f300000
+
+#define CONFIG_SYS_FPGA_BASE(k) \
+ (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
+
+#define CONFIG_SYS_FPGA_DONE(k) \
+ (k ? 0x2000 : 0x1000)
+
+#define CONFIG_SYS_FPGA_COUNT 2
+
+#define CONFIG_SYS_LATCH0_RESET 0xffff
+#define CONFIG_SYS_LATCH0_BOOT 0xffff
+#define CONFIG_SYS_LATCH1_RESET 0xffcf
+#define CONFIG_SYS_LATCH1_BOOT 0xffff
+
+/*
+ * FLASH organization
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
+#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protect */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
+#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif
+
+/*
+ * PPC405 GPIO Configuration
+ */
+#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
+{ \
+/* GPIO Core 0 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
+{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
+{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
+{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
+} \
+}
+
+/*
+ * Definitions for initial stack pointer and data area (in data cache)
+ */
+/* use on chip memory (OCM) for temperary stack until sdram is tested */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+
+/* On Chip Memory location */
+#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
+#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
+#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (NOR-flash) */
+#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(7) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(2) | \
+ EBC_BXAP_WBF_ENCODE(2) | \
+ EBC_BXAP_TH_ENCODE(4) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
+ EBC_BXCR_BS_64MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 1 (FPGA0) */
+#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(5) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 2 (FPGA1) */
+#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
+ EBC_BXAP_TWT_ENCODE(6) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(2) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(0) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/* Memory Bank 3 (Latches) */
+#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
+ EBC_BXAP_FWT_ENCODE(8) | \
+ EBC_BXAP_BWT_ENCODE(4) | \
+ EBC_BXAP_BCE_DISABLE | \
+ EBC_BXAP_BCT_2TRANS | \
+ EBC_BXAP_CSN_ENCODE(0) | \
+ EBC_BXAP_OEN_ENCODE(1) | \
+ EBC_BXAP_WBN_ENCODE(1) | \
+ EBC_BXAP_WBF_ENCODE(1) | \
+ EBC_BXAP_TH_ENCODE(2) | \
+ EBC_BXAP_RE_DISABLED | \
+ EBC_BXAP_SOR_NONDELAYED | \
+ EBC_BXAP_BEM_WRITEONLY | \
+ EBC_BXAP_PEN_DISABLED)
+#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
+ EBC_BXCR_BS_1MB | \
+ EBC_BXCR_BU_RW | \
+ EBC_BXCR_BW_16BIT)
+
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_ICS8N3QV01
+#define CONFIG_SYS_SIL1178
+#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
+
+#endif /* __CONFIG_H */
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * Stuff still to be dealt with -
- */
-#define CONFIG_RTC_MC146818
-
/*
* High Level Configuration Options
* (easy to change)
*/
-#define DEBUG_PARSER
-
-#define CONFIG_X86 1 /* Intel X86 CPU */
-#define CONFIG_SYS_SC520 1 /* AMD SC520 */
+#define CONFIG_X86
+#define CONFIG_SYS_SC520
#define CONFIG_SYS_SC520_SSI
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-#define CONFIG_LAST_STAGE_INIT 1
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_LAST_STAGE_INIT
-/*
- * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
+/*-----------------------------------------------------------------------
+ * Watchdog Configuration
+ * NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
* bottom (processor) board MUST be removed!
*/
#undef CONFIG_WATCHDOG
#define CONFIG_HW_WATCHDOG
- /*-----------------------------------------------------------------------
- * Serial Configuration
- */
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
#define CONFIG_SERIAL_MULTI
-#define CONFIG_CONS_INDEX 1
+#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 1843200
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 UART0_BASE
-#define CONFIG_SYS_NS16550_COM2 UART1_BASE
-#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
-#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 1843200
+#define CONFIG_BAUDRATE 9600
+#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
+ 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_COM1 UART0_BASE
+#define CONFIG_SYS_NS16550_COM2 UART1_BASE
+#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
+#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
#define CONFIG_SYS_NS16550_PORT_MAPPED
- /*-----------------------------------------------------------------------
- * Video Configuration
- */
-#undef CONFIG_VIDEO /* No Video Hardware */
-#undef CONFIG_CFB_CONSOLE
-
-/*
- * Size of malloc() pool
+/*-----------------------------------------------------------------------
+ * Video Configuration
*/
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
/*-----------------------------------------------------------------------
* Command line configuration.
*/
#include <config_cmd_default.h>
-#define CONFIG_CMD_BDI /* bdinfo */
-#define CONFIG_CMD_BOOTD /* bootd */
-#define CONFIG_CMD_CONSOLE /* coninfo */
-#define CONFIG_CMD_ECHO /* echo arguments */
-#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
-#define CONFIG_CMD_FPGA /* FPGA configuration Support */
-#define CONFIG_CMD_IMI /* iminfo */
-#define CONFIG_CMD_IMLS /* List all found images */
-#define CONFIG_CMD_IRQ /* IRQ Information */
-#define CONFIG_CMD_ITEST /* Integer (and string) test */
-#define CONFIG_CMD_LOADB /* loadb */
-#define CONFIG_CMD_LOADS /* loads */
-#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
-#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
-#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
-#undef CONFIG_CMD_NFS /* NFS support */
-#define CONFIG_CMD_PCI /* PCI support */
-#define CONFIG_CMD_PING /* ICMP echo support */
-#define CONFIG_CMD_RUN /* run command in env variable */
-#define CONFIG_CMD_SAVEENV /* saveenv */
-#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
-#define CONFIG_CMD_SOURCE /* "source" command Support */
-#define CONFIG_CMD_XIMG /* Load part of Multi Image */
-
-#define CONFIG_BOOTDELAY 15
-#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
-/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_IMI
+#define CONFIG_CMD_IMLS
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_XIMG
+
+#define CONFIG_BOOTDELAY 15
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#define CONFIG_KGDB_BAUDRATE 115200
+#define CONFIG_KGDB_SER_INDEX 2
#endif
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + \
- 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1kHz */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "boot > "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x01000000
+#define CONFIG_SYS_LOAD_ADDR 0x100000
+#define CONFIG_SYS_HZ 1000
/*-----------------------------------------------------------------------
* SDRAM Configuration
*/
-#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
-#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
+#define CONFIG_SYS_SDRAM_REFRESH_RATE 156
+#define CONFIG_NR_DRAM_BANKS 4
/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_REFRESH_RATE
#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
/*-----------------------------------------------------------------------
* CPU Features
*/
-#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
-#define CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
-#define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
-#undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */
-#undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
-#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
- * in the SC520 on the CDP */
+#define CONFIG_SYS_SC520_HIGH_SPEED 0
+#define CONFIG_SYS_SC520_RESET
+#define CONFIG_SYS_SC520_TIMER
+#undef CONFIG_SYS_GENERIC_TIMER
#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_NUM_IRQS 16
+#define CONFIG_SYS_NUM_IRQS 16
/*-----------------------------------------------------------------------
- * Memory organization
+ * Memory organization:
+ * 32kB Stack
+ * 256kB Monitor
*/
-#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
-#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
-#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
-#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
-#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
+#define CONFIG_SYS_STACK_SIZE 0x8000
+#define CONFIG_SYS_CAR_ADDR 0x19200000
+#define CONFIG_SYS_CAR_SIZE 0x00004000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_CAR_ADDR + \
+ CONFIG_SYS_CAR_SIZE)
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+/* Address of temporary Global Data */
+#define CONFIG_SYS_INIT_GD_ADDR CONFIG_SYS_CAR_ADDR
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
- /*-----------------------------------------------------------------------
- * FLASH configuration
- */
-#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
+/*-----------------------------------------------------------------------
+ * FLASH configuration
+ * 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
+ * 16MB StrataFlash #1 @ 0x10000000
+ * 16MB StrataFlash #2 @ 0x11000000
+ */
+#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_FLASH_CFI_LEGACY
-#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
-#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
- CONFIG_SYS_FLASH_BASE_1, \
- CONFIG_SYS_FLASH_BASE_2}
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_MAX_FLASH_BANKS 3
+#define CONFIG_SYS_FLASH_BASE 0x38000000
+#define CONFIG_SYS_FLASH_BASE_1 0x10000000
+#define CONFIG_SYS_FLASH_BASE_2 0x11000000
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
+ CONFIG_SYS_FLASH_BASE_1, \
+ CONFIG_SYS_FLASH_BASE_2}
#define CONFIG_SYS_FLASH_EMPTY_INFO
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
#define CONFIG_SYS_FLASH_LEGACY_512Kx8
-
- /*-----------------------------------------------------------------------
- * Environment configuration
- */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
+#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
/* Redundant Copy */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
- CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
-
-
- /*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* pci plug-and-play */
-#define CONFIG_SYS_FIRST_PCI_IRQ 10
-#define CONFIG_SYS_SECOND_PCI_IRQ 9
-#define CONFIG_SYS_THIRD_PCI_IRQ 11
-#define CONFIG_SYS_FORTH_PCI_IRQ 15
-
- /*
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
+ CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_SYS_FIRST_PCI_IRQ 10
+#define CONFIG_SYS_SECOND_PCI_IRQ 9
+#define CONFIG_SYS_THIRD_PCI_IRQ 11
+#define CONFIG_SYS_FORTH_PCI_IRQ 15
+
+/*-----------------------------------------------------------------------
* Network device (TRL8100B) support
*/
#define CONFIG_NET_MULTI
#define CONFIG_RTL8139
/*-----------------------------------------------------------------------
- * FPGA configuration
- */
-#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
-#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
-#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
-#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
-#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
-#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
-#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
-#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
-#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
-#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
-#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
-
-#ifndef __ASSEMBLER__
-extern unsigned long ip;
-
-#define PRINTIP asm ("call 0\n" \
- "0:\n" \
- "pop %%eax\n" \
- "movl %%eax, %0\n" \
- :"=r"(ip) \
- : /* No Input Registers */ \
- :"%eax"); \
- printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
+ * BOOTCS Control (for AM29LV040B-120JC)
+ *
+ * 000 0 00 0 000 11 0 011 }- 0x0033
+ * \ / | \| | \ / \| | \ /
+ * | | | | | | | |
+ * | | | | | | | +---- 3 Wait States (First Access)
+ * | | | | | | +------- Reserved
+ * | | | | | +--------- 3 Wait States (Subsequent Access)
+ * | | | | +------------- Reserved
+ * | | | +---------------- Non-Paged Mode
+ * | | +------------------ 8 Bit Wide
+ * | +--------------------- GP Bus
+ * +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
+
+/*-----------------------------------------------------------------------
+ * ROMCS Control (for E28F128J3A-150 StrataFlash)
+ *
+ * 000 0 01 1 000 01 0 101 }- 0x0615
+ * \ / | \| | \ / \| | \ /
+ * | | | | | | | |
+ * | | | | | | | +---- 5 Wait States (First Access)
+ * | | | | | | +------- Reserved
+ * | | | | | +--------- 1 Wait State (Subsequent Access)
+ * | | | | +------------- Reserved
+ * | | | +---------------- Paged Mode
+ * | | +------------------ 16 Bit Wide
+ * | +--------------------- GP Bus
+ * +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
+#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
+
+/*-----------------------------------------------------------------------
+ * SC520 General Purpose Bus configuration
+ *
+ * Chip Select Offset 1 Clock Cycle
+ * Chip Select Pulse Width 8 Clock Cycles
+ * Chip Select Read Offset 2 Clock Cycles
+ * Chip Select Read Width 6 Clock Cycles
+ * Chip Select Write Offset 2 Clock Cycles
+ * Chip Select Write Width 6 Clock Cycles
+ * Chip Select Recovery Time 2 Clock Cycles
+ *
+ * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
+ *
+ * |<-------------General Purpose Bus Cycle---------------->|
+ * | |
+ * ----------------------\__________________/------------------
+ * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
+ *
+ * ------------------------\_______________/-------------------
+ * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
+ *
+ * --------------------------\_______________/-----------------
+ * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
+ *
+ * ________/-----------\_______________________________________
+ * |<--->|<--------->|
+ * ^ ^
+ * (GPALEOFF + 1) |
+ * |
+ * (GPALEW + 1)
+ */
+#define CONFIG_SYS_SC520_GPCSOFF 0x00
+#define CONFIG_SYS_SC520_GPCSPW 0x07
+#define CONFIG_SYS_SC520_GPRDOFF 0x01
+#define CONFIG_SYS_SC520_GPRDW 0x05
+#define CONFIG_SYS_SC520_GPWROFF 0x01
+#define CONFIG_SYS_SC520_GPWRW 0x05
+#define CONFIG_SYS_SC520_GPCSRT 0x01
+
+/*-----------------------------------------------------------------------
+ * SC520 Programmable I/O configuration
+ *
+ * Pin Mode Dir. Description
+ * ----------------------------------------------------------------------
+ * PIO0 PIO Output Unused
+ * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
+ * PIO2 PIO Output Auxiliary power output enable
+ * PIO3 GPAEN Output GP Bus Address Enable
+ * PIO4 PIO Output Top Board Enable (active low)
+ * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
+ * PIO6 PIO Input Data output of Power Supply ADC
+ * PIO7 PIO Output Clock input to Power Supply ADC
+ * PIO8 PIO Output Chip Select input of Power Supply ADC
+ * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
+ * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
+ * PIO11 PIO Input StrataFlash 1 Status
+ * PIO12 PIO Input StrataFlash 2 Status
+ * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
+ * PIO14 PIO Input Low Input Voltage Warning (active low)
+ * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
+ * PIO16 PIO Input Power Fail
+ * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
+ * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
+ * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
+ * PIO20 GPIRQ3 Input UART D IRQ
+ * PIO21 GPIRQ2 Input UART C IRQ
+ * PIO22 GPIRQ1 Input UART B IRQ
+ * PIO23 GPIRQ0 Input UART A IRQ
+ * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
+ * PIO25 PIO Input Battery OK Indication
+ * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
+ * PIO27 GPCS0# Output SRAM 1 Chip Select
+ * PIO28 PIO Input Top Board UART CTS
+ * PIO29 PIO Output FPGA Program Mode (active low)
+ * PIO30 PIO Input FPGA Initialised (active low)
+ * PIO31 PIO Input FPGA Done (active low)
+ */
+#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
+#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
+#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
+#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
+
+/*-----------------------------------------------------------------------
+ * PIO Pin defines
+ */
+#define CONFIG_SYS_ENET_AUX_PWR 0x0004
+#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
+#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
+#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
+#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
+#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
+#define CONFIG_SYS_ENET_SF1_MODE 0x0200
+#define CONFIG_SYS_ENET_SF2_MODE 0x0400
+#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
+#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
+#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
+#define CONFIG_SYS_ENET_WATCHDOG 0x8000
+
+#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
+#define CONFIG_SYS_ENET_BAT_OK 0x0200
+#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
+#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
+#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
+#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
+
+/*-----------------------------------------------------------------------
+ * Chip Select Pin Function Select
+ *
+ * 1 1 1 1 1 0 0 0 }- 0xf8
+ * | | | | | | | |
+ * | | | | | | | +--- Reserved
+ * | | | | | | +----- GPCS1_SEL = ROMCS1#
+ * | | | | | +------- GPCS2_SEL = ROMCS2#
+ * | | | | +--------- GPCS3_SEL = GPCS3
+ * | | | +----------- GPCS4_SEL = GPCS4
+ * | | +------------- GPCS5_SEL = GPCS5
+ * | +--------------- GPCS6_SEL = GPCS6
+ * +----------------- GPCS7_SEL = GPCS7
+ */
+#define CONFIG_SYS_SC520_CSPFS 0xf8
+
+/*-----------------------------------------------------------------------
+ * Clock Select (CLKTIMER[CLKTEST] pin)
+ *
+ * 0 111 00 1 0 }- 0x72
+ * | \ / \| | |
+ * | | | | +--- Pin Disabled
+ * | | | +----- Pin is an output
+ * | | +------- Reserved
+ * | +----------- Disabled (pin stays Low)
+ * +-------------- Reserved
+ */
+#define CONFIG_SYS_SC520_CLKSEL 0x72
+
+/*-----------------------------------------------------------------------
+ * Address Decode Control
+ *
+ * 0 00 0 0 0 0 0 }- 0x00
+ * | \| | | | | |
+ * | | | | | | +--- Integrated UART 1 is enabled
+ * | | | | | +----- Integrated UART 2 is enabled
+ * | | | | +------- Integrated RTC is enabled
+ * | | | +--------- Reserved
+ * | | +----------- I/O Hole accesses are forwarded to the external GP bus
+ * | +------------- Reserved
+ * +---------------- Write-protect violations do not generate an IRQ
+ */
+#define CONFIG_SYS_SC520_ADDDECCTL 0x00
+
+/*-----------------------------------------------------------------------
+ * UART Control
+ *
+ * 00000 1 1 1 }- 0x07
+ * \___/ | | |
+ * | | | +--- Transmit TC interrupt enable
+ * | | +----- Receive TC interrupt enable
+ * | +------- 1.8432 MHz
+ * +----------- Reserved
+ */
+#define CONFIG_SYS_SC520_UART1CTL 0x07
+#define CONFIG_SYS_SC520_UART2CTL 0x07
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Control
+ *
+ * 00000 1 1 0 }- 0x06
+ * \___/ | | |
+ * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
+ * | | +----- The system arbiter operates in concurrent mode
+ * | +------- Park the PCI bus on the last master that acquired the bus
+ * +----------- Reserved
+ */
+#define CONFIG_SYS_SC520_SYSARBCTL 0x06
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Master Enable
+ *
+ * 00000000000 0 0 0 1 1 }- 0x06
+ * \_________/ | | | | |
+ * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
+ * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
+ * | | | +------- PCI master REQ2 disabled
+ * | | +--------- PCI master REQ3 disabled
+ * | +----------- PCI master REQ4 disabled
+ * +------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Master Enable
+ *
+ * 0 0000 0 00 0000 1 000 }- 0x06
+ * | \__/ | \| \__/ | \_/
+ * | | | | | | +---- Reserved
+ * | | | | | +------- Enable CPU-to-PCI bus write posting
+ * | | | | +---------- Reserved
+ * | | | +-------------- PCI bus reads to SDRAM are not automatically
+ * | | | retried
+ * | | +----------------- Target read FIFOs are not snooped during write
+ * | | transactions
+ * | +-------------------- Reserved
+ * +------------------------ Deassert the PCI bus reset signal
+ */
+#define CONFIG_SYS_SC520_HBCTL 0x08
+
+/*-----------------------------------------------------------------------
+ * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
+ * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x38000000
+ * | | | | | +----------------------- 512kB Region Size
+ * | | | | | ((7 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled (So it can be
+ * | | | reprogrammed!)
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
+
+/*-----------------------------------------------------------------------
+ * Cache-As-RAM (Targets Boot Flash)
+ *
+ * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
+ * \ / | | | | \--+--/ \-------+--------/
+ * | | | | | | +------------ Start at 0x19200000
+ * | | | | | +------------------------- 64k Region Size
+ * | | | | | ((15 + 1) * 4kB)
+ * | | | | +------------------------------ 4kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Enabled
+ * | +------------------------------------ Execution Prevented
+ * +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_CAR_PAR 0x903d9200
+
+/*-----------------------------------------------------------------------
+ * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
+ *
+ * 001 110 0 000100000 0001000000000000 }- 0x38201000
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x00001000
+ * | | | +------------------------ 33 Bytes (0x20 + 1)
+ * | | +------------------------------ Ignored
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
+
+/*-----------------------------------------------------------------------
+ * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
+ * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
+ *
+ * 010 101 0 0000000 100000000000000000 }- 0x54020000
+ * 010 111 0 0000000 100000000000000001 }- 0x5c020001
+ * \ / \ / | \--+--/ \-------+--------/
+ * | | | | +------------ Start at 0x200000000
+ * | | | | 0x200010000
+ * | | | +------------------------- 4kB Region Size
+ * | | | ((0 + 1) * 4kB)
+ * | | +------------------------------ 4k Page Size
+ * | +--------------------------------- GPCS5
+ * | GPCS7
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
+#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
+
+/*-----------------------------------------------------------------------
+ * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
+ * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
+ * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
+ * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
+ *
+ * 001 000 0 000000111 0001001111111000 }- 0x200713f8
+ * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
+ * 001 011 0 000000111 0001001011111000 }- 0x300711f8
+ * 001 011 0 000000111 0001001011111000 }- 0x340710f8
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x013f8
+ * | | | | 0x012f8
+ * | | | | 0x011f8
+ * | | | | 0x010f8
+ * | | | +------------------------ 33 Bytes (32 + 1)
+ * | | +------------------------------ Ignored
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
+#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
+#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
+#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
+
+/*-----------------------------------------------------------------------
+ * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
+ * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
+ *
+ * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
+ * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x10000000
+ * | | | | | | 0x11000000
+ * | | | | | +----------------------- 16MB Region Size
+ * | | | | | ((255 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- ROMCS1
+ * ROMCS2
+ */
+#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
+#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
+
+/*-----------------------------------------------------------------------
+ * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
+ * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
+ *
+ * 010 000 1 00000001111 01100100000000 }- 0x4203d900
+ * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
+ * \ / \ / | \----+----/ \-----+------/
+ * | | | | +---------- Start at 0x19000000
+ * | | | | 0x19100000
+ * | | | +----------------------- 1MB Region Size
+ * | | | ((15 + 1) * 64kB)
+ * | | +------------------------------ 64kB Page Size
+ * | +--------------------------------- GPCS0
+ * | GPCS3
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
+#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
+
+/*-----------------------------------------------------------------------
+ * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
+ *
+ * 010 100 0 00000000 11000000100000000 }- 0x50018100
+ * \ / \ / | \---+--/ \-------+-------/
+ * | | | | +----------- Start at 0x18100000
+ * | | | +------------------------ 4kB Region Size
+ * | | | ((0 + 1) * 4kB)
+ * | | +------------------------------ 4kB Page Size
+ * | +--------------------------------- GPCS4
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
-#endif
#endif /* __CONFIG_H */
#define CONFIG_SYS_EBC_PB1CR 0x7f318000
/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE 0x7f100000
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x02025080
/* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
-#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH 0x3ffe
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k) 0x0010
+
+#define CONFIG_SYS_FPGA_COUNT 1
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
else fpga_gpio_clear(0x0020)
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
+/*
+ * OSD hardware
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+
/*
* FLASH organization
*/
#define CONFIG_SYS_EBC_PB1AP 0x92015480
#define CONFIG_SYS_EBC_PB1CR 0xFB858000
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE 0x7f100000
+/* Memory Bank 2 (FPGA0) initialization */
+#define CONFIG_SYS_FPGA0_BASE 0x7f100000
#define CONFIG_SYS_EBC_PB2AP 0x02825080
-#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE | 0x1a000)
+#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k) 0x0010
-#define CONFIG_SYS_FPGA_RFL_LOW 0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH 0x00fe
+#define CONFIG_SYS_FPGA_COUNT 1
/* Memory Bank 3 (Latches) initialization */
#define CONFIG_SYS_LATCH_BASE 0x7f200000
#define CONFIG_SYS_LATCH1_RESET 0xffff
#define CONFIG_SYS_LATCH1_BOOT 0xffff
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
+
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2010
+ * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __GDSYS_FPGA_H
+#define __GDSYS_FPGA_H
+
+enum {
+ FPGA_STATE_DONE_FAILED = 1 << 0,
+ FPGA_STATE_REFLECTION_FAILED = 1 << 1,
+};
+
+int get_fpga_state(unsigned dev);
+void print_fpga_state(unsigned dev);
+
+typedef struct ihs_gpio {
+ u16 read;
+ u16 clear;
+ u16 set;
+} ihs_gpio_t;
+
+typedef struct ihs_i2c {
+ u16 write_mailbox;
+ u16 write_mailbox_ext;
+ u16 read_mailbox;
+ u16 read_mailbox_ext;
+} ihs_i2c_t;
+
+typedef struct ihs_osd {
+ u16 version;
+ u16 features;
+ u16 control;
+ u16 xy_size;
+} ihs_osd_t;
+
+#ifdef CONFIG_IO
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_features; /* 0x0004 */
+ u16 fpga_version; /* 0x0006 */
+ u16 reserved_0[5]; /* 0x0008 */
+ u16 quad_serdes_reset; /* 0x0012 */
+ u16 reserved_1[8181]; /* 0x0014 */
+ u16 reflection_high; /* 0x3ffe */
+} ihs_fpga_t;
+#endif
+
+#ifdef CONFIG_IOCON
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_version; /* 0x0004 */
+ u16 fpga_features; /* 0x0006 */
+ u16 reserved_0[6]; /* 0x0008 */
+ ihs_gpio_t gpio; /* 0x0014 */
+ u16 mpc3w_control; /* 0x001a */
+ u16 reserved_1[19]; /* 0x001c */
+ u16 videocontrol; /* 0x0042 */
+ u16 reserved_2[93]; /* 0x0044 */
+ u16 reflection_high; /* 0x00fe */
+ ihs_osd_t osd; /* 0x0100 */
+ u16 reserved_3[892]; /* 0x0108 */
+ u16 videomem; /* 0x0800 */
+} ihs_fpga_t;
+#endif
+
+#ifdef CONFIG_DLVISION_10G
+typedef struct ihs_fpga {
+ u16 reflection_low; /* 0x0000 */
+ u16 versions; /* 0x0002 */
+ u16 fpga_version; /* 0x0004 */
+ u16 fpga_features; /* 0x0006 */
+ u16 reserved_0[10]; /* 0x0008 */
+ u16 extended_interrupt; /* 0x001c */
+ u16 reserved_1[9]; /* 0x001e */
+ ihs_i2c_t i2c; /* 0x0030 */
+ u16 reserved_2[35]; /* 0x0038 */
+ u16 reflection_high; /* 0x007e */
+ u16 reserved_3[15]; /* 0x0080 */
+ u16 videocontrol; /* 0x009e */
+ u16 reserved_4[176]; /* 0x00a0 */
+ ihs_osd_t osd; /* 0x0200 */
+ u16 reserved_5[764]; /* 0x0208 */
+ u16 videomem; /* 0x0800 */
+} ihs_fpga_t;
+#endif
+
+#endif
/* SPMR - System PLL Mode Register
*/
#define SPMR_LBIUCM 0x80000000
+#define SPMR_LBIUCM_SHIFT 31
#define SPMR_DDRCM 0x40000000
+#define SPMR_DDRCM_SHIFT 30
#define SPMR_SPMF 0x0F000000
+#define SPMR_SPMF_SHIFT 24
#define SPMR_CKID 0x00800000
#define SPMR_CKID_SHIFT 23
#define SPMR_COREPLL 0x007F0000
+#define SPMR_COREPLL_SHIFT 16
#define SPMR_CEVCOD 0x000000C0
+#define SPMR_CEVCOD_SHIFT 6
#define SPMR_CEPDF 0x00000020
+#define SPMR_CEPDF_SHIFT 5
#define SPMR_CEPMF 0x0000001F
+#define SPMR_CEPMF_SHIFT 0
/* OCCR - Output Clock Control Register
*/
/* Used by ppc405 autoconfig*/
struct pci_region *pci_fb;
int current_busno;
+
+ void *priv_data;
};
extern __inline__ void pci_set_ops(struct pci_controller *hose,
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