Merge with /home/sr/git/u-boot/denx

diff --combined CHANGELOG
index 67824926e51eaf8f48644d306d2233821b9c50bc,e451b517a4a86803478b0509a9429021e3351cde..24499c5621a3c7c11680a82fe9843ce212299eed
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -2,23 -2,19 +2,36 @@@
  Changes since U-Boot 1.1.4:
  ======================================================================
  
+ * Fix control-c handing in CONFIG_CMDLINE_EDITING
+   Properly pass break code back from readline.
+   Patch by Roger Blofeld, 31 Jul 2006
+ 
+ * Add commandline history support to all AMCC eval boards
+   Patch by Stefan Roese, 07 Aug 2006
+ 
+ * Add Macronix MXLV320T flash support for AMCC Bamboo
+   Patch by Stefan Roese, 07 Aug 2006
+ 
+ * Change "mii info" to not print an error upon missing PHY at address
+   Patch by Stefan Roese, 07 Aug 2006
+ 
 +* Fix PCI-Express on PPC440SPe rev. A.
 +
 +* Fix preboot message on TQM85xx after switching to hush parser.
 +
 +* Adapt TQM85xx ramdisk address to Linux kernel memory map
 +
 +* Add initial support for PCI-Express on PPC440SPe (Yucca board).
 +
 +* Fix compiler warning for TRAB board.
 +  Patch by Martin Krause, 07 Aug 2006
 +
 +* Prevent USB commands from working when USB is stopped.
 +
 +* Add rudimentary handling of alternate settings of USB interfaces.
 +  This is in order to fix issues with some USB sticks timing out
 +  during initialization. Some code readability improvements.
 +
  * PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance
    AMCC suggested to set the PMU bit to 0 for best performace on
    the PPC440 DDR controller.

diff --combined include/configs/yucca.h
index 26a330eea7120d2baa3f5c6f6d573abf42d497d6,f027d72d65e13c3f6b11939f2d1a6e92e8c8ffa7..884f85c31e9fbfce420d3511c885d738d0021bae
--- 1/include/configs/yucca.h
--- 2/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@@ -63,20 -63,17 +63,20 @@@
  #define CFG_PERIPHERAL_BASE   0xa0000000      /* internal peripherals */
  #define CFG_ISRAM_BASE                0x90000000      /* internal SRAM        */
  
 -#define CFG_PCI_MEMBASE               0x80000000      /* mapped pci memory    */
 -#define CFG_PCI_MEMBASE1      0x90000000      /* mapped pci memory    */
 -#define CFG_PCI_MEMBASE2      0xa0000000      /* mapped pci memory    */
 -#define CFG_PCI_MEMBASE3      0xb0000000      /* mapped pci memory    */
 -
 +#define CFG_PCI_MEMBASE               0x80000000      /* mapped PCI memory    */
  #define CFG_PCI_BASE          0xd0000000      /* internal PCI regs    */
 -#define CFG_PCI_TARGBASE      0x80000000      /*PCIaddr mapped to CFG_PCI_MEMBASE*/
 +#define CFG_PCI_TARGBASE      CFG_PCI_MEMBASE
 +
 +#define CFG_PCIE_MEMBASE      0xb0000000      /* mapped PCIe memory   */
 +#define CFG_PCIE_MEMSIZE      0x01000000
 +#define CFG_PCIE_BASE         0xe0000000      /* PCIe UTL regs */
  
 -/* #define CFG_PCI_BASE_IO    0xB8000000 */   /* internal PCI I-O     */
 -/* #define CFG_PCI_BASE_REGS  0xBEC00000 */   /* internal PCI regs    */
 -/* #define CFG_PCI_BASE_CYCLE 0xBED00000 */   /* internal PCI regs    */
 +#define CFG_PCIE0_CFGBASE     0xc0000000
 +#define CFG_PCIE0_XCFGBASE    0xc0000400
 +#define CFG_PCIE1_CFGBASE     0xc0001000
 +#define CFG_PCIE1_XCFGBASE    0xc0001400
 +#define CFG_PCIE2_CFGBASE     0xc0002000
 +#define CFG_PCIE2_XCFGBASE    0xc0002400
  
  /* System RAM mapped to PCI space */
  #define CONFIG_PCI_SYS_MEM_BUS        CFG_SDRAM_BASE
@@@ -223,6 -220,9 +223,9 @@@
  #define CONFIG_PHY_GIGE               1       /* Include GbE speed/duplex detection */
  #define CFG_RX_ETH_BUFFER     32      /* Number of ethernet rx buffers & descriptors */
  
+ #define CONFIG_NETCONSOLE             /* include NetConsole support   */
+ #define CONFIG_NET_MULTI              /* needed for NetConsole        */
+ 
  #undef CONFIG_WATCHDOG                        /* watchdog disabled            */
  
  /*
@@@ -248,6 -248,12 +251,12 @@@
  
  #define CFG_HZ                        1000            /* decrementer freq: 1 ms ticks */
  
+ #define CONFIG_CMDLINE_EDITING        1       /* add command line history     */
+ #define CONFIG_LOOPW            1       /* enable loopw command         */
+ #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
+ #define CONFIG_ZERO_BOOTDELAY_CHECK   /* check for keypress on bootdelay==0 */
+ #define CONFIG_VERSION_VARIABLE 1     /* include version env variable */
+ 
  /*-----------------------------------------------------------------------
   * FLASH related
   *----------------------------------------------------------------------*/
@@@ -295,7 -301,6 +304,7 @@@
   */
  /* Support for Intel 82557/82559/82559ER chips. */
  #define CONFIG_EEPRO100
 +
  /*
   * For booting Linux, the board info and command line data
   * have to be in the first 8 MB of memory, since this is
@@@ -510,8 -515,8 +519,8 @@@
  #define FPGA_REG1C_PE1_WAKE           0x0040
  #define FPGA_REG1C_PE2_WAKE           0x0020
  #define FPGA_REG1C_PE0_PERST          0x0010
 -#define FPGA_REG1C_PE1_PERST          0x0080
 -#define FPGA_REG1C_PE2_PERST          0x0040
 +#define FPGA_REG1C_PE1_PERST          0x0008
 +#define FPGA_REG1C_PE2_PERST          0x0004
  
  /*----------------------------------------------------------------------------+
  | Defines