ARM i.MX6Q: Fix IOMUXC GPR1 defines for ENET_CLK_SEL and IPU1/2_MUX

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index dab34a1deb2c156ecdb8a67328d6cfbb6b0d5c8d..b1521e82fecf0c6562da7d2af779ea932b1640be 100644 (file)
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -103,15 +103,15 @@
 #define IMX6Q_GPR1_EXC_MON_MASK                        BIT(22)
 #define IMX6Q_GPR1_EXC_MON_OKAY                        0x0
 #define IMX6Q_GPR1_EXC_MON_SLVE                        BIT(22)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK          BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET                0x0
-#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX         BIT(21)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK          BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET                0x0
-#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX         BIT(20)
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK          BIT(19)
+#define IMX6Q_GPR1_ENET_CLK_SEL_MASK           BIT(21)
+#define IMX6Q_GPR1_ENET_CLK_SEL_PAD            0
+#define IMX6Q_GPR1_ENET_CLK_SEL_ANATOP         BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK          BIT(20)
 #define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET                0x0
-#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX         BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX         BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK          BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET                0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX         BIT(19)
 #define IMX6Q_GPR1_PCIE_TEST_PD                        BIT(18)
 #define IMX6Q_GPR1_IPU_VPU_MUX_MASK            BIT(17)
 #define IMX6Q_GPR1_IPU_VPU_MUX_IPU1            0x0