ARM: dts: ls1021a: Add the eTSEC controller nodes

Add basic support for all the eTSEC controllers on the
ls1021a SoC.  Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.

Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 71ea37d11228bd5a627d9fb3aac11ba3efca947d..973a496207fc069bc8af040e16cbb74febcf1c5c 100644 (file)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -53,6 +53,9 @@
        interrupt-parent = <&gic>;
 
        aliases {
+               ethernet0 = &enet0;
+               ethernet1 = &enet1;
+               ethernet2 = &enet2;
                serial0 = &lpuart0;
                serial1 = &lpuart1;
                serial2 = &lpuart2;
@@ -393,6 +396,91 @@
                        reg = <0x0 0x2d24000 0x0 0x4000>;
                };
 
+               enet0: ethernet@2d10000 {
+                       compatible = "fsl,etsec2";
+                       device_type = "network";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       interrupt-parent = <&gic>;
+                       model = "eTSEC";
+                       fsl,magic-packet;
+                       ranges;
+
+                       queue-group@2d10000 {
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x2d10000 0x0 0x1000>;
+                               interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       queue-group@2d14000  {
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x2d14000 0x0 0x1000>;
+                               interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               enet1: ethernet@2d50000 {
+                       compatible = "fsl,etsec2";
+                       device_type = "network";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       interrupt-parent = <&gic>;
+                       model = "eTSEC";
+                       ranges;
+
+                       queue-group@2d50000  {
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x2d50000 0x0 0x1000>;
+                               interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       queue-group@2d54000  {
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x2d54000 0x0 0x1000>;
+                               interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
+               enet2: ethernet@2d90000 {
+                       compatible = "fsl,etsec2";
+                       device_type = "network";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       interrupt-parent = <&gic>;
+                       model = "eTSEC";
+                       ranges;
+
+                       queue-group@2d90000  {
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x2d90000 0x0 0x1000>;
+                               interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+
+                       queue-group@2d94000  {
+                               #address-cells = <2>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x2d94000 0x0 0x1000>;
+                               interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+                       };
+               };
+
                usb@8600000 {
                        compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
                        reg = <0x0 0x8600000 0x0 0x1000>;