Merge tag 'tegra-for-4.12-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel...

dt-bindings: Updates for v4.12-rc1

This contains an update for the flow controller device tree binding as
well as the addition of the binding for the GP10B GPU found on the new
Tegra186 (Parker) SoC.

* tag 'tegra-for-4.12-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: Add documentation for GP10B GPU
  dt-bindings: tegra: Update compatible strings for Tegra flowctrl

Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
index ccf0adddc8205e3f47df8ff99af43271f7792a99..a855c1bffc0f6695d5c0cd3f032019ea32d9d5e8 100644 (file)
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt
@@ -1,7 +1,13 @@
 NVIDIA Tegra Flow Controller
 
 Required properties:
-- compatible: Should be "nvidia,tegra<chip>-flowctrl"
+- compatible: Should contain one of the following:
+  - "nvidia,tegra20-flowctrl": for Tegra20
+  - "nvidia,tegra30-flowctrl": for Tegra30
+  - "nvidia,tegra114-flowctrl": for Tegra114
+  - "nvidia,tegra124-flowctrl": for Tegra124
+  - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132
+  - "nvidia,tegra210-flowctrl": for Tegra210
 - reg: Should contain one register range (address and length)
 
 Example:

diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
index ff3db65e50def8224096107eaf05827df884ca25..b7e4c74445108dcd2c966529a85a4a930b40e831 100644 (file)
--- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
+++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
@@ -5,6 +5,7 @@ Required properties:
   Currently recognized values:
   - nvidia,gk20a
   - nvidia,gm20b
+  - nvidia,gp10b
 - reg: Physical base address and length of the controller's registers.
   Must contain two entries:
   - first entry for bar0
@@ -14,7 +15,8 @@ Required properties:
 - interrupt-names: Must include the following entries:
   - stall
   - nonstall
-- vdd-supply: regulator for supply voltage.
+- vdd-supply: regulator for supply voltage. Only required for GPUs not using
+  power domains.
 - clocks: Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
@@ -27,6 +29,8 @@ is also required:
   See ../reset/reset.txt for details.
 - reset-names: Must include the following entries:
   - gpu
+- power-domains: GPUs that make use of power domains can define this property
+  instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
 
 Optional properties:
 - iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
@@ -68,3 +72,22 @@ Example for GM20B:
                iommus = <&mc TEGRA_SWGROUP_GPU>;
                status = "disabled";
        };
+
+Example for GP10B:
+
+       gpu@17000000 {
+               compatible = "nvidia,gp10b";
+               reg = <0x0 0x17000000 0x0 0x1000000>,
+                     <0x0 0x18000000 0x0 0x1000000>;
+               interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+                             GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "stall", "nonstall";
+               clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
+                        <&bpmp TEGRA186_CLK_GPU>;
+               clock-names = "gpu", "pwr";
+               resets = <&bpmp TEGRA186_RESET_GPU>;
+               reset-names = "gpu";
+               power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
+               iommus = <&smmu TEGRA186_SID_GPU>;
+               status = "disabled";
+       };