ARM: dts: imx6qdl-sabreauto: Allow HDMI and LVDS to work simultaneously

Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.

Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.

With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 6b17b8519f36493fb6a906f84111c67bb327d43f..8d52481a81b4f75003a49593e8a4fe0bdea573ed 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -93,9 +93,13 @@
 &clks {
        assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
                          <&clks IMX6QDL_PLL4_BYPASS>,
-                         <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
+                         <&clks IMX6QDL_CLK_PLL4_POST_DIV>,
+                         <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
        assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
-                               <&clks IMX6QDL_PLL4_BYPASS_SRC>;
+                                <&clks IMX6QDL_PLL4_BYPASS_SRC>,
+                                <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                                <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
        assigned-clock-rates = <0>, <0>, <24576000>;
 };