From: Ben Skeggs <bskeggs@redhat.com>
Date: Mon, 13 May 2013 02:57:10 +0000 (+1000)
Subject: drm/nvc0/gr: update initial register/context values
X-Git-Tag: v3.11-rc1~65^2~23^2~15
X-Git-Url: https://git.kernelconcepts.de/?a=commitdiff_plain;h=d8b02dbbc37de874728181963b1ec9ef874cc81d;p=karo-tx-linux.git

drm/nvc0/gr: update initial register/context values

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
---

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 31a84162632b..416dc9b16978 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1325,6 +1325,7 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
 	nv_mthd(priv, 0x9097, 0x0214, 0x00000000);
 
 	switch (nv_device(priv)->chipset) {
+	case 0xc0:
 	case 0xd9:
 	case 0xd7:
 		break;
@@ -1471,6 +1472,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x40402c, 0x00000000);
 		break;
+	case 0xc0:
 	default:
 		break;
 	}
@@ -1490,6 +1492,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
 	nv_wr32(priv, 0x4040c4, 0x00000000);
 	nv_wr32(priv, 0x4040c8, 0xf0000087);
 	switch (nv_device(priv)->chipset) {
+	case 0xc0:
 	case 0xd9:
 	case 0xd7:
 		nv_wr32(priv, 0x4040d0, 0x00000000);
@@ -1516,6 +1519,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
 	case 0xd9:
 	case 0xd7:
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x404174, 0x00000000);
 		break;
@@ -1645,20 +1649,24 @@ nvc0_grctx_generate_unk47xx(struct nvc0_graph_priv *priv)
 static void
 nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
 {
-
-	if (nv_device(priv)->chipset >= 0xd0) {
+	switch (nv_device(priv)->chipset) {
+	case 0xc1:
 		nv_wr32(priv, 0x405800, 0x0f8000bf);
 		nv_wr32(priv, 0x405830, 0x02180218);
-		nv_wr32(priv, 0x405834, 0x08000000);
-	} else
-	if (nv_device(priv)->chipset == 0xc1) {
+		nv_wr32(priv, 0x405834, 0x00000000);
+		break;
+	case 0xd9:
+	case 0xd7:
 		nv_wr32(priv, 0x405800, 0x0f8000bf);
 		nv_wr32(priv, 0x405830, 0x02180218);
-		nv_wr32(priv, 0x405834, 0x00000000);
-	} else {
+		nv_wr32(priv, 0x405834, 0x08000000);
+		break;
+	case 0xc0:
+	default:
 		nv_wr32(priv, 0x405800, 0x078000bf);
 		nv_wr32(priv, 0x405830, 0x02180000);
 		nv_wr32(priv, 0x405834, 0x00000000);
+		break;
 	}
 	nv_wr32(priv, 0x405838, 0x00000000);
 	nv_wr32(priv, 0x405854, 0x00000000);
@@ -1694,6 +1702,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x4064bc, 0x00000000);
 		break;
+	case 0xc0:
 	default:
 		break;
 	}
@@ -1704,6 +1713,7 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
 		nv_wr32(priv, 0x4064c0, 0x80140078);
 		nv_wr32(priv, 0x4064c4, 0x0086ffff);
 		break;
+	case 0xc0:
 	default:
 		break;
 	}
@@ -1742,6 +1752,12 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
 	nv_wr32(priv, 0x408800, 0x02802a3c);
 	nv_wr32(priv, 0x408804, 0x00000040);
 	switch (nv_device(priv)->chipset) {
+	case 0xc0:
+		nv_wr32(priv, 0x408808, 0x0003e00d);
+		nv_wr32(priv, 0x408900, 0x3080b801);
+		nv_wr32(priv, 0x408904, 0x02000001);
+		nv_wr32(priv, 0x408908, 0x00c80929);
+		break;
 	case 0xc1:
 		nv_wr32(priv, 0x408808, 0x1003e005);
 		nv_wr32(priv, 0x408900, 0x3080b801);
@@ -1780,6 +1796,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
 	case 0xd9:
 	case 0xd7:
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x418408, 0x00000000);
 		break;
@@ -1791,6 +1808,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x418414, 0x02200fff);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x418414, 0x00200fff);
 		break;
@@ -1814,6 +1832,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x41870c, 0x00000000);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x41870c, 0x07c80000);
 		break;
@@ -1824,6 +1843,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x418800, 0x7006860a);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x418800, 0x0006860a);
 		break;
@@ -1838,6 +1858,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x418830, 0x10000001);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x418830, 0x00000001);
 		break;
@@ -1857,6 +1878,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x4188fc, 0x20100008);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x4188fc, 0x00100000);
 		break;
@@ -1879,6 +1901,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x418b00, 0x00000006);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x418b00, 0x00000000);
 		break;
@@ -1905,6 +1928,7 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x418c6c, 0x00000001);
 		break;
+	case 0xc0:
 	default:
 		break;
 	}
@@ -1929,6 +1953,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x419864, 0x00000129);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x419864, 0x0000012a);
 		break;
@@ -1940,8 +1965,14 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
 	nv_wr32(priv, 0x419a0c, 0x00020000);
 	nv_wr32(priv, 0x419a10, 0x00000000);
 	nv_wr32(priv, 0x419a14, 0x00000200);
-	nv_wr32(priv, 0x419a1c, 0x00000000);
-	nv_wr32(priv, 0x419a20, 0x00000800);
+	switch (nv_device(priv)->chipset) {
+	case 0xc0:
+		break;
+	default:
+		nv_wr32(priv, 0x419a1c, 0x00000000);
+		nv_wr32(priv, 0x419a20, 0x00000800);
+		break;
+	}
 	switch (nv_device(priv)->chipset) {
 	case 0xc0:
 	case 0xc8:
@@ -1967,6 +1998,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x419be0, 0x00400001);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x419be0, 0x00000001);
 		break;
@@ -1977,6 +2009,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x419c00, 0x0000000a);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x419c00, 0x00000002);
 		break;
@@ -1995,6 +2028,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
 		nv_wr32(priv, 0x419c28, 0x3cf3cf3c);
 		nv_wr32(priv, 0x419cb0, 0x00020048);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x419cb0, 0x00060048);
 		break;
@@ -2007,6 +2041,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x419d20, 0x12180000);
 		break;
+	case 0xc0:
 	default:
 		nv_wr32(priv, 0x419d20, 0x02180000);
 		break;
@@ -2018,6 +2053,7 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_wr32(priv, 0x419d44, 0x02180218);
 		break;
+	case 0xc0:
 	default:
 		break;
 	}
@@ -2399,6 +2435,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
 		for (i = 0x400; i <= 0x417; i++)
 			nv_icmd(priv, i, 0x00000040);
 		break;
+	case 0xc0:
 	default:
 		break;
 	}
@@ -2416,6 +2453,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
 		for (i = 0x440; i <= 0x457; i++)
 			nv_icmd(priv, i, 0x0000c080);
 		break;
+	case 0xc0:
+		break;
 	default:
 		break;
 	}
@@ -2986,6 +3025,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_icmd(priv, 0x0000057b, 0x00000059);
 		break;
+	case 0xc0:
 	default:
 		break;
 	}
@@ -3094,6 +3134,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
 	case 0xd7:
 		nv_icmd(priv, 0x0000097d, 0x00000020);
 		break;
+	case 0xc0:
 	default:
 		break;
 	}
@@ -3240,6 +3281,9 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
 	nvc0_grctx_generate_90c0(priv);
 
 	switch (nv_device(priv)->chipset) {
+	case 0xc0:
+		nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
+		break;
 	case 0xd9:
 	case 0xd7:
 		nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
index a9f499c6729b..1034ff15b032 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
@@ -48,10 +48,10 @@ cmd_queue:		queue_init
 // chipset descriptions
 chipsets:
 .b8  0xc0 0 0 0
-.b16 #nvc0_gpc_mmio_head
-.b16 #nvc0_gpc_mmio_tail
-.b16 #nvc0_tpc_mmio_head
-.b16 #nvc0_tpc_mmio_tail
+.b16 #nnvc0_gpc_mmio_head
+.b16 #nnvc0_gpc_mmio_tail
+.b16 #nnvc0_tpc_mmio_head
+.b16 #nnvc0_tpc_mmio_tail
 .b8  0xc1 0 0 0
 .b16 #nvc0_gpc_mmio_head
 .b16 #nvc1_gpc_mmio_tail
@@ -124,6 +124,33 @@ nvc0_gpc_mmio_tail:
 mmctx_data(0x000c6c, 1);
 nvc1_gpc_mmio_tail:
 
+nnvc0_gpc_mmio_head:
+mmctx_data(0x000380, 1)
+mmctx_data(0x000400, 6)
+mmctx_data(0x000450, 9)
+mmctx_data(0x000600, 1)
+mmctx_data(0x000684, 1)
+mmctx_data(0x000700, 5)
+mmctx_data(0x000800, 1)
+mmctx_data(0x000808, 3)
+mmctx_data(0x000828, 1)
+mmctx_data(0x000830, 1)
+mmctx_data(0x0008d8, 1)
+mmctx_data(0x0008e0, 1)
+mmctx_data(0x0008e8, 6)
+mmctx_data(0x00091c, 1)
+mmctx_data(0x000924, 3)
+mmctx_data(0x000b00, 1)
+mmctx_data(0x000b08, 6)
+mmctx_data(0x000bb8, 1)
+mmctx_data(0x000c08, 1)
+mmctx_data(0x000c10, 8)
+mmctx_data(0x000c80, 1)
+mmctx_data(0x000c8c, 1)
+mmctx_data(0x001000, 3)
+mmctx_data(0x001014, 1)
+nnvc0_gpc_mmio_tail:
+
 nvd9_gpc_mmio_head:
 mmctx_data(0x000380, 1)
 mmctx_data(0x000400, 2)
@@ -185,6 +212,28 @@ nvc3_tpc_mmio_tail:
 mmctx_data(0x000544, 1)
 nvc1_tpc_mmio_tail:
 
+nnvc0_tpc_mmio_head:
+mmctx_data(0x000018, 1)
+mmctx_data(0x00003c, 1)
+mmctx_data(0x000048, 1)
+mmctx_data(0x000064, 1)
+mmctx_data(0x000088, 1)
+mmctx_data(0x000200, 6)
+mmctx_data(0x000300, 6)
+mmctx_data(0x0003d0, 1)
+mmctx_data(0x0003e0, 2)
+mmctx_data(0x000400, 3)
+mmctx_data(0x000420, 1)
+mmctx_data(0x0004b0, 1)
+mmctx_data(0x0004e8, 1)
+mmctx_data(0x0004f4, 1)
+mmctx_data(0x000520, 2)
+mmctx_data(0x000604, 4)
+mmctx_data(0x000644, 20)
+mmctx_data(0x000698, 1)
+mmctx_data(0x000750, 2)
+nnvc0_tpc_mmio_tail:
+
 nvd9_tpc_mmio_head:
 mmctx_data(0x000018, 1)
 mmctx_data(0x00003c, 1)
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
index b8c9fc3b32bd..427ddf06316c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@@ -34,32 +34,32 @@ uint32_t nvc0_grgpc_data[] = {
 	0x00000000,
 /* 0x0064: chipsets */
 	0x000000c0,
-	0x013400d4,
-	0x01f001a0,
+	0x01980138,
+	0x02b00264,
 	0x000000c1,
 	0x013800d4,
-	0x020401a0,
+	0x02640200,
 	0x000000c3,
 	0x013400d4,
-	0x020001a0,
+	0x02600200,
 	0x000000c4,
 	0x013400d4,
-	0x020001a0,
+	0x02600200,
 	0x000000c8,
 	0x013400d4,
-	0x01f001a0,
+	0x02500200,
 	0x000000ce,
 	0x013400d4,
-	0x020001a0,
+	0x02600200,
 	0x000000cf,
 	0x013400d4,
-	0x01fc01a0,
+	0x025c0200,
 	0x000000d9,
-	0x01a00138,
-	0x02600204,
+	0x02000198,
+	0x030c02b0,
 	0x000000d7,
-	0x01a00138,
-	0x02600204,
+	0x02000198,
+	0x030c02b0,
 	0x00000000,
 /* 0x00d4: nvc0_gpc_mmio_head */
 	0x00000380,
@@ -89,7 +89,33 @@ uint32_t nvc0_grgpc_data[] = {
 /* 0x0134: nvc0_gpc_mmio_tail */
 	0x00000c6c,
 /* 0x0138: nvc1_gpc_mmio_tail */
-/* 0x0138: nvd9_gpc_mmio_head */
+/* 0x0138: nnvc0_gpc_mmio_head */
+	0x00000380,
+	0x14000400,
+	0x20000450,
+	0x00000600,
+	0x00000684,
+	0x10000700,
+	0x00000800,
+	0x08000808,
+	0x00000828,
+	0x00000830,
+	0x000008d8,
+	0x000008e0,
+	0x140008e8,
+	0x0000091c,
+	0x08000924,
+	0x00000b00,
+	0x14000b08,
+	0x00000bb8,
+	0x00000c08,
+	0x1c000c10,
+	0x00000c80,
+	0x00000c8c,
+	0x08001000,
+	0x00001014,
+/* 0x0198: nnvc0_gpc_mmio_tail */
+/* 0x0198: nvd9_gpc_mmio_head */
 	0x00000380,
 	0x04000400,
 	0x0800040c,
@@ -116,8 +142,8 @@ uint32_t nvc0_grgpc_data[] = {
 	0x00000c8c,
 	0x08001000,
 	0x00001014,
-/* 0x01a0: nvd9_gpc_mmio_tail */
-/* 0x01a0: nvc0_tpc_mmio_head */
+/* 0x0200: nvd9_gpc_mmio_tail */
+/* 0x0200: nvc0_tpc_mmio_head */
 	0x00000018,
 	0x0000003c,
 	0x00000048,
@@ -138,16 +164,37 @@ uint32_t nvc0_grgpc_data[] = {
 	0x4c000644,
 	0x00000698,
 	0x04000750,
-/* 0x01f0: nvc0_tpc_mmio_tail */
+/* 0x0250: nvc0_tpc_mmio_tail */
 	0x00000758,
 	0x000002c4,
 	0x000006e0,
-/* 0x01fc: nvcf_tpc_mmio_tail */
+/* 0x025c: nvcf_tpc_mmio_tail */
 	0x000004bc,
-/* 0x0200: nvc3_tpc_mmio_tail */
+/* 0x0260: nvc3_tpc_mmio_tail */
 	0x00000544,
-/* 0x0204: nvc1_tpc_mmio_tail */
-/* 0x0204: nvd9_tpc_mmio_head */
+/* 0x0264: nvc1_tpc_mmio_tail */
+/* 0x0264: nnvc0_tpc_mmio_head */
+	0x00000018,
+	0x0000003c,
+	0x00000048,
+	0x00000064,
+	0x00000088,
+	0x14000200,
+	0x14000300,
+	0x000003d0,
+	0x040003e0,
+	0x08000400,
+	0x00000420,
+	0x000004b0,
+	0x000004e8,
+	0x000004f4,
+	0x04000520,
+	0x0c000604,
+	0x4c000644,
+	0x00000698,
+	0x04000750,
+/* 0x02b0: nnvc0_tpc_mmio_tail */
+/* 0x02b0: nvd9_tpc_mmio_head */
 	0x00000018,
 	0x0000003c,
 	0x00000048,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index 56735d0654bf..9f0768e2719d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -37,10 +37,19 @@ hub_mmio_list_tail:	.b32 0
 
 ctx_current:		.b32 0
 
+.align 256
+chan_data:
+chan_mmio_count:	.b32 0
+chan_mmio_address:	.b32 0
+
+.align 256
+xfer_data: 		.b32 0
+
+.align 256
 chipsets:
 .b8  0xc0 0 0 0
-.b16 #nvc0_hub_mmio_head
-.b16 #nvc0_hub_mmio_tail
+.b16 #nnvc0_hub_mmio_head
+.b16 #nnvc0_hub_mmio_tail
 .b8  0xc1 0 0 0
 .b16 #nvc0_hub_mmio_head
 .b16 #nvc1_hub_mmio_tail
@@ -111,6 +120,48 @@ nvc0_hub_mmio_tail:
 mmctx_data(0x4064c0, 2)
 nvc1_hub_mmio_tail:
 
+nnvc0_hub_mmio_head:
+mmctx_data(0x17e91c, 2)
+mmctx_data(0x400204, 2)
+mmctx_data(0x404004, 11)
+mmctx_data(0x404044, 1)
+mmctx_data(0x404094, 14)
+mmctx_data(0x4040d0, 7)
+mmctx_data(0x4040f8, 1)
+mmctx_data(0x404130, 3)
+mmctx_data(0x404150, 3)
+mmctx_data(0x404164, 2)
+mmctx_data(0x404174, 3)
+mmctx_data(0x404200, 8)
+mmctx_data(0x404404, 14)
+mmctx_data(0x404460, 4)
+mmctx_data(0x404480, 1)
+mmctx_data(0x404498, 1)
+mmctx_data(0x404604, 4)
+mmctx_data(0x404618, 32)
+mmctx_data(0x404698, 21)
+mmctx_data(0x4046f0, 2)
+mmctx_data(0x404700, 22)
+mmctx_data(0x405800, 1)
+mmctx_data(0x405830, 3)
+mmctx_data(0x405854, 1)
+mmctx_data(0x405870, 4)
+mmctx_data(0x405a00, 2)
+mmctx_data(0x405a18, 1)
+mmctx_data(0x406020, 1)
+mmctx_data(0x406028, 4)
+mmctx_data(0x4064a8, 2)
+mmctx_data(0x4064b4, 2)
+mmctx_data(0x407804, 1)
+mmctx_data(0x40780c, 6)
+mmctx_data(0x4078bc, 1)
+mmctx_data(0x408000, 7)
+mmctx_data(0x408064, 1)
+mmctx_data(0x408800, 3)
+mmctx_data(0x408900, 3)
+mmctx_data(0x408980, 1)
+nnvc0_hub_mmio_tail:
+
 nvd9_hub_mmio_head:
 mmctx_data(0x17e91c, 2)
 mmctx_data(0x400204, 2)
@@ -153,14 +204,6 @@ mmctx_data(0x408900, 3)
 mmctx_data(0x408980, 1)
 nvd9_hub_mmio_tail:
 
-.align 256
-chan_data:
-chan_mmio_count:	.b32 0
-chan_mmio_address:	.b32 0
-
-.align 256
-xfer_data: 		.b32 0
-
 .section #nvc0_grhub_code
 bra #init
 define(`include_code')
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index eb59892bc488..fc5f9727ae76 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -28,27 +28,200 @@ uint32_t nvc0_grhub_data[] = {
 	0x00000000,
 /* 0x0058: ctx_current */
 	0x00000000,
-/* 0x005c: chipsets */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+/* 0x0100: chan_data */
+/* 0x0100: chan_mmio_count */
+	0x00000000,
+/* 0x0104: chan_mmio_address */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+/* 0x0200: xfer_data */
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+	0x00000000,
+/* 0x0300: chipsets */
 	0x000000c0,
-	0x014400a8,
+	0x048803ec,
 	0x000000c1,
-	0x014800a8,
+	0x03ec034c,
 	0x000000c3,
-	0x014400a8,
+	0x03e8034c,
 	0x000000c4,
-	0x014400a8,
+	0x03e8034c,
 	0x000000c8,
-	0x014400a8,
+	0x03e8034c,
 	0x000000ce,
-	0x014400a8,
+	0x03e8034c,
 	0x000000cf,
-	0x014400a8,
+	0x03e8034c,
 	0x000000d9,
-	0x01e40148,
+	0x05240488,
 	0x000000d7,
-	0x01e40148,
+	0x05240488,
 	0x00000000,
-/* 0x00a8: nvc0_hub_mmio_head */
+/* 0x034c: nvc0_hub_mmio_head */
 	0x0417e91c,
 	0x04400204,
 	0x28404004,
@@ -88,10 +261,51 @@ uint32_t nvc0_grhub_data[] = {
 	0x08408800,
 	0x0c408900,
 	0x00408980,
-/* 0x0144: nvc0_hub_mmio_tail */
+/* 0x03e8: nvc0_hub_mmio_tail */
 	0x044064c0,
-/* 0x0148: nvc1_hub_mmio_tail */
-/* 0x0148: nvd9_hub_mmio_head */
+/* 0x03ec: nvc1_hub_mmio_tail */
+/* 0x03ec: nnvc0_hub_mmio_head */
+	0x0417e91c,
+	0x04400204,
+	0x28404004,
+	0x00404044,
+	0x34404094,
+	0x184040d0,
+	0x004040f8,
+	0x08404130,
+	0x08404150,
+	0x04404164,
+	0x08404174,
+	0x1c404200,
+	0x34404404,
+	0x0c404460,
+	0x00404480,
+	0x00404498,
+	0x0c404604,
+	0x7c404618,
+	0x50404698,
+	0x044046f0,
+	0x54404700,
+	0x00405800,
+	0x08405830,
+	0x00405854,
+	0x0c405870,
+	0x04405a00,
+	0x00405a18,
+	0x00406020,
+	0x0c406028,
+	0x044064a8,
+	0x044064b4,
+	0x00407804,
+	0x1440780c,
+	0x004078bc,
+	0x18408000,
+	0x00408064,
+	0x08408800,
+	0x08408900,
+	0x00408980,
+/* 0x0488: nnvc0_hub_mmio_tail */
+/* 0x0488: nvd9_hub_mmio_head */
 	0x0417e91c,
 	0x04400204,
 	0x24404004,
@@ -131,83 +345,6 @@ uint32_t nvc0_grhub_data[] = {
 	0x08408800,
 	0x08408900,
 	0x00408980,
-/* 0x01e4: nvd9_hub_mmio_tail */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0200: chan_data */
-/* 0x0200: chan_mmio_count */
-	0x00000000,
-/* 0x0204: chan_mmio_address */
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-	0x00000000,
-/* 0x0300: xfer_data */
-	0x00000000,
 };
 
 uint32_t nvc0_grhub_code[] = {
@@ -443,7 +580,7 @@ uint32_t nvc0_grhub_code[] = {
 	0x0017f100,
 	0x0227f012,
 	0xf10012d0,
-	0xfe05b917,
+	0xfe05ba17,
 	0x17f10010,
 	0x10d00400,
 	0x0437f1c0,
@@ -477,403 +614,403 @@ uint32_t nvc0_grhub_code[] = {
 	0x4021d000,
 	0x080027f1,
 	0xcf0624b6,
-	0xf7f00022,
-/* 0x03a9: init_find_chipset */
-	0x08f0b654,
-	0xb800f398,
-	0x0bf40432,
-	0x0034b00b,
-	0xf8f11bf4,
-/* 0x03bd: init_context */
-	0x0017f100,
-	0x02fe5801,
-	0xf003ff58,
-	0x0e8000e3,
-	0x150f8014,
-	0x013d21f5,
-	0x070037f1,
-	0x950634b6,
-	0x34d00814,
-	0x4034d000,
-	0x130030b7,
-	0xb6001fbb,
-	0x3fd002f5,
-	0x0815b600,
-	0xb60110b6,
-	0x1fb90814,
-	0x6321f502,
-	0x001fbb02,
-	0xf1000398,
-	0xf0200047,
-/* 0x040e: init_gpc */
-	0x4ea05043,
-	0x1fb90804,
-	0x8d21f402,
-	0x08004ea0,
-	0xf4022fb9,
-	0x4ea08d21,
-	0xf4bd010c,
+	0xf7f10022,
+/* 0x03aa: init_find_chipset */
+	0xf0b602f8,
+	0x00f39808,
+	0xf40432b8,
+	0x34b00b0b,
+	0xf11bf400,
+/* 0x03be: init_context */
+	0x17f100f8,
+	0xfe580100,
+	0x03ff5802,
+	0x8000e3f0,
+	0x0f80140e,
+	0x3d21f515,
+	0x0037f101,
+	0x0634b607,
+	0xd0081495,
+	0x34d00034,
+	0x0030b740,
+	0x001fbb13,
+	0xd002f5b6,
+	0x15b6003f,
+	0x0110b608,
+	0xb90814b6,
+	0x21f5021f,
+	0x1fbb0263,
+	0x00039800,
+	0x200047f1,
+/* 0x040f: init_gpc */
+	0xa05043f0,
+	0xb908044e,
+	0x21f4021f,
+	0x004ea08d,
+	0x022fb908,
 	0xa08d21f4,
-	0xf401044e,
-	0x4ea08d21,
-	0xf7f00100,
-	0x8d21f402,
-	0x08004ea0,
-/* 0x0440: init_gpc_wait */
-	0xc86821f4,
-	0x0bf41fff,
-	0x044ea0fa,
+	0xbd010c4e,
+	0x8d21f4f4,
+	0x01044ea0,
+	0xa08d21f4,
+	0xf001004e,
+	0x21f402f7,
+	0x004ea08d,
+/* 0x0441: init_gpc_wait */
 	0x6821f408,
-	0xb7001fbb,
-	0xb6800040,
-	0x1bf40132,
-	0x0027f1b4,
-	0x0624b608,
-	0xb74021d0,
-	0xbd080020,
-	0x1f19f014,
-/* 0x0473: main */
-	0xf40021d0,
-	0x28f40031,
-	0x08d7f000,
-	0xf43921f4,
-	0xe4b1f401,
-	0x1bf54001,
-	0x87f100d1,
-	0x84b6083c,
-	0xf094bd06,
-	0x89d00499,
-	0x0017f100,
-	0x0614b60b,
-	0xcf4012cf,
-	0x13c80011,
-	0x7e0bf41f,
-	0xf41f23c8,
-	0x20f95a0b,
-	0xf10212b9,
+	0xf41fffc8,
+	0x4ea0fa0b,
+	0x21f40804,
+	0x001fbb68,
+	0x800040b7,
+	0xf40132b6,
+	0x27f1b41b,
+	0x24b60800,
+	0x4021d006,
+	0x080020b7,
+	0x19f014bd,
+	0x0021d01f,
+/* 0x0474: main */
+	0xf40031f4,
+	0xd7f00028,
+	0x3921f408,
+	0xb1f401f4,
+	0xf54001e4,
+	0xf100d11b,
 	0xb6083c87,
 	0x94bd0684,
-	0xd00799f0,
-	0x32f40089,
-	0x0231f401,
-	0x082921f5,
-	0x085c87f1,
+	0xd00499f0,
+	0x17f10089,
+	0x14b60b00,
+	0x4012cf06,
+	0xc80011cf,
+	0x0bf41f13,
+	0x1f23c87e,
+	0xf95a0bf4,
+	0x0212b920,
+	0x083c87f1,
 	0xbd0684b6,
 	0x0799f094,
-	0xfc0089d0,
-	0x3c87f120,
+	0xf40089d0,
+	0x31f40132,
+	0x2a21f502,
+	0x5c87f108,
 	0x0684b608,
 	0x99f094bd,
-	0x0089d006,
-	0xf50131f4,
-	0xf1082921,
-	0xb6085c87,
-	0x94bd0684,
-	0xd00699f0,
-	0x0ef40089,
-/* 0x0509: chsw_prev_no_next */
-	0xb920f931,
-	0x32f40212,
-	0x0232f401,
-	0x082921f5,
-	0x17f120fc,
-	0x14b60b00,
-	0x0012d006,
-/* 0x0527: chsw_no_prev */
-	0xc8130ef4,
-	0x0bf41f23,
-	0x0131f40d,
-	0xf50232f4,
-/* 0x0537: chsw_done */
-	0xf1082921,
-	0xb60b0c17,
-	0x27f00614,
-	0x0012d001,
+	0x0089d007,
+	0x87f120fc,
+	0x84b6083c,
+	0xf094bd06,
+	0x89d00699,
+	0x0131f400,
+	0x082a21f5,
 	0x085c87f1,
 	0xbd0684b6,
-	0x0499f094,
-	0xf50089d0,
-/* 0x0557: main_not_ctx_switch */
-	0xb0ff200e,
-	0x1bf401e4,
-	0x02f2b90d,
-	0x07b521f5,
-/* 0x0567: main_not_ctx_chan */
-	0xb0420ef4,
-	0x1bf402e4,
-	0x3c87f12e,
+	0x0699f094,
+	0xf40089d0,
+/* 0x050a: chsw_prev_no_next */
+	0x20f9310e,
+	0xf40212b9,
+	0x32f40132,
+	0x2a21f502,
+	0xf120fc08,
+	0xb60b0017,
+	0x12d00614,
+	0x130ef400,
+/* 0x0528: chsw_no_prev */
+	0xf41f23c8,
+	0x31f40d0b,
+	0x0232f401,
+	0x082a21f5,
+/* 0x0538: chsw_done */
+	0x0b0c17f1,
+	0xf00614b6,
+	0x12d00127,
+	0x5c87f100,
 	0x0684b608,
 	0x99f094bd,
-	0x0089d007,
-	0xf40132f4,
-	0x21f50232,
-	0x87f10829,
-	0x84b6085c,
+	0x0089d004,
+	0xff200ef5,
+/* 0x0558: main_not_ctx_switch */
+	0xf401e4b0,
+	0xf2b90d1b,
+	0xb621f502,
+	0x420ef407,
+/* 0x0568: main_not_ctx_chan */
+	0xf402e4b0,
+	0x87f12e1b,
+	0x84b6083c,
 	0xf094bd06,
 	0x89d00799,
-	0x110ef400,
-/* 0x0598: main_not_ctx_save */
-	0xf010ef94,
-	0x21f501f5,
-	0x0ef502ec,
-/* 0x05a6: main_done */
-	0x17f1fed1,
-	0x14b60820,
-	0xf024bd06,
-	0x12d01f29,
-	0xbe0ef500,
-/* 0x05b9: ih */
-	0xfe80f9fe,
-	0x80f90188,
-	0xa0f990f9,
-	0xd0f9b0f9,
-	0xf0f9e0f9,
-	0xc4800acf,
-	0x0bf404ab,
-	0x00b7f11d,
-	0x08d7f019,
-	0xcf40becf,
-	0x21f400bf,
-	0x00b0b704,
-	0x01e7f004,
-/* 0x05ef: ih_no_fifo */
-	0xe400bed0,
-	0xf40100ab,
-	0xd7f00d0b,
-	0x01e7f108,
-	0x0421f440,
-/* 0x0600: ih_no_ctxsw */
-	0x0104b7f1,
-	0xabffb0bd,
-	0x0d0bf4b4,
-	0x0c1ca7f1,
-	0xd006a4b6,
-/* 0x0616: ih_no_other */
-	0x0ad000ab,
-	0xfcf0fc40,
-	0xfcd0fce0,
-	0xfca0fcb0,
-	0xfe80fc90,
-	0x80fc0088,
-	0xf80032f4,
-/* 0x0631: ctx_4160s */
-	0x60e7f101,
-	0x40e3f041,
-	0xf401f7f0,
-/* 0x063e: ctx_4160s_wait */
-	0x21f48d21,
-	0x04ffc868,
-	0xf8fa0bf4,
-/* 0x0649: ctx_4160c */
-	0x60e7f100,
-	0x40e3f041,
-	0x21f4f4bd,
-/* 0x0657: ctx_4170s */
-	0xf100f88d,
-	0xf04170e7,
-	0xf5f040e3,
-	0x8d21f410,
-/* 0x0666: ctx_4170w */
+	0x0132f400,
+	0xf50232f4,
+	0xf1082a21,
+	0xb6085c87,
+	0x94bd0684,
+	0xd00799f0,
+	0x0ef40089,
+/* 0x0599: main_not_ctx_save */
+	0x10ef9411,
+	0xf501f5f0,
+	0xf502ec21,
+/* 0x05a7: main_done */
+	0xf1fed10e,
+	0xb6082017,
+	0x24bd0614,
+	0xd01f29f0,
+	0x0ef50012,
+/* 0x05ba: ih */
+	0x80f9febe,
+	0xf90188fe,
+	0xf990f980,
+	0xf9b0f9a0,
+	0xf9e0f9d0,
+	0x800acff0,
+	0xf404abc4,
+	0xb7f11d0b,
+	0xd7f01900,
+	0x40becf08,
+	0xf400bfcf,
+	0xb0b70421,
+	0xe7f00400,
+	0x00bed001,
+/* 0x05f0: ih_no_fifo */
+	0x0100abe4,
+	0xf00d0bf4,
+	0xe7f108d7,
+	0x21f44001,
+/* 0x0601: ih_no_ctxsw */
+	0x04b7f104,
+	0xffb0bd01,
+	0x0bf4b4ab,
+	0x1ca7f10d,
+	0x06a4b60c,
+/* 0x0617: ih_no_other */
+	0xd000abd0,
+	0xf0fc400a,
+	0xd0fce0fc,
+	0xa0fcb0fc,
+	0x80fc90fc,
+	0xfc0088fe,
+	0x0032f480,
+/* 0x0632: ctx_4160s */
+	0xe7f101f8,
+	0xe3f04160,
+	0x01f7f040,
+/* 0x063f: ctx_4160s_wait */
+	0xf48d21f4,
+	0xffc86821,
+	0xfa0bf404,
+/* 0x064a: ctx_4160c */
 	0xe7f100f8,
-	0xe3f04170,
-	0x6821f440,
-	0xf410f4f0,
-	0x00f8f31b,
-/* 0x0678: ctx_redswitch */
-	0x0614e7f1,
-	0xf106e4b6,
-	0xd00270f7,
-	0xf7f000ef,
-/* 0x0689: ctx_redswitch_delay */
-	0x01f2b608,
-	0xf1fd1bf4,
-	0xd00770f7,
-	0x00f800ef,
-/* 0x0698: ctx_86c */
-	0x086ce7f1,
-	0xd006e4b6,
-	0xe7f100ef,
-	0xe3f08a14,
-	0x8d21f440,
-	0xa86ce7f1,
-	0xf441e3f0,
+	0xe3f04160,
+	0xf4f4bd40,
 	0x00f88d21,
-/* 0x06b8: ctx_load */
-	0x083c87f1,
-	0xbd0684b6,
-	0x0599f094,
-	0xf00089d0,
-	0x21f40ca7,
-	0x2417f1c9,
-	0x0614b60a,
-	0xf10010d0,
-	0xb60b0037,
-	0x32d00634,
-	0x0c17f140,
-	0x0614b60a,
-	0xd00747f0,
-	0x14d00012,
-/* 0x06f1: ctx_chan_wait_0 */
-	0x4014cf40,
-	0xf41f44f0,
-	0x32d0fa1b,
-	0x000bfe00,
-	0xb61f2af0,
-	0x20b60424,
-	0x3c87f102,
+/* 0x0658: ctx_4170s */
+	0x4170e7f1,
+	0xf040e3f0,
+	0x21f410f5,
+/* 0x0667: ctx_4170w */
+	0xf100f88d,
+	0xf04170e7,
+	0x21f440e3,
+	0x10f4f068,
+	0xf8f31bf4,
+/* 0x0679: ctx_redswitch */
+	0x14e7f100,
+	0x06e4b606,
+	0x0270f7f1,
+	0xf000efd0,
+/* 0x068a: ctx_redswitch_delay */
+	0xf2b608f7,
+	0xfd1bf401,
+	0x0770f7f1,
+	0xf800efd0,
+/* 0x0699: ctx_86c */
+	0x6ce7f100,
+	0x06e4b608,
+	0xf100efd0,
+	0xf08a14e7,
+	0x21f440e3,
+	0x6ce7f18d,
+	0x41e3f0a8,
+	0xf88d21f4,
+/* 0x06b9: ctx_load */
+	0x3c87f100,
 	0x0684b608,
 	0x99f094bd,
-	0x0089d008,
-	0x0a0417f1,
+	0x0089d005,
+	0xf40ca7f0,
+	0x17f1c921,
+	0x14b60a24,
+	0x0010d006,
+	0x0b0037f1,
+	0xd00634b6,
+	0x17f14032,
+	0x14b60a0c,
+	0x0747f006,
+	0xd00012d0,
+/* 0x06f2: ctx_chan_wait_0 */
+	0x14cf4014,
+	0x1f44f040,
+	0xd0fa1bf4,
+	0x0bfe0032,
+	0x1f2af000,
+	0xb60424b6,
+	0x87f10220,
+	0x84b6083c,
+	0xf094bd06,
+	0x89d00899,
+	0x0417f100,
+	0x0614b60a,
+	0xf10012d0,
+	0xb60a2017,
+	0x27f00614,
+	0x0023f102,
+	0x0012d080,
+	0xf11017f0,
+	0xf0020027,
+	0x12fa0223,
+	0xf103f805,
+	0xb6085c87,
+	0x94bd0684,
+	0xd00899f0,
+	0x01980089,
+	0x1814b681,
+	0xb6800298,
+	0x12fd0825,
+	0x16018005,
+	0x083c87f1,
+	0xbd0684b6,
+	0x0999f094,
+	0xf10089d0,
+	0xb60a0427,
+	0x21d00624,
+	0x0127f000,
+	0x0a2017f1,
 	0xd00614b6,
 	0x17f10012,
-	0x14b60a20,
-	0x0227f006,
-	0x800023f1,
-	0xf00012d0,
-	0x27f11017,
-	0x23f00300,
-	0x0512fa02,
+	0x13f00100,
+	0x0501fa06,
 	0x87f103f8,
 	0x84b6085c,
 	0xf094bd06,
-	0x89d00899,
-	0xc1019800,
-	0x981814b6,
-	0x25b6c002,
-	0x0512fd08,
-	0xf1160180,
-	0xb6083c87,
-	0x94bd0684,
-	0xd00999f0,
-	0x27f10089,
-	0x24b60a04,
-	0x0021d006,
-	0xf10127f0,
-	0xb60a2017,
-	0x12d00614,
-	0x0017f100,
-	0x0613f002,
-	0xf80501fa,
-	0x5c87f103,
+	0x89d00999,
+	0x5c87f100,
 	0x0684b608,
 	0x99f094bd,
-	0x0089d009,
-	0x085c87f1,
-	0xbd0684b6,
-	0x0599f094,
-	0xf80089d0,
-/* 0x07b5: ctx_chan */
-	0x3121f500,
-	0xb821f506,
-	0x0ca7f006,
-	0xf1c921f4,
-	0xb60a1017,
-	0x27f00614,
-	0x0012d005,
-/* 0x07d0: ctx_chan_wait */
-	0xfd0012cf,
-	0x1bf40522,
-	0x4921f5fa,
-/* 0x07df: ctx_mmio_exec */
-	0x9800f806,
-	0x27f18103,
-	0x24b60a04,
-	0x0023d006,
-/* 0x07ee: ctx_mmio_loop */
-	0x34c434bd,
-	0x0f1bf4ff,
-	0x030057f1,
-	0xfa0653f0,
-	0x03f80535,
-/* 0x0800: ctx_mmio_pull */
-	0x98c04e98,
-	0x21f4c14f,
-	0x0830b68d,
-	0xf40112b6,
-/* 0x0812: ctx_mmio_done */
-	0x0398df1b,
-	0x0023d016,
-	0xf1800080,
-	0xf0020017,
-	0x01fa0613,
-	0xf803f806,
-/* 0x0829: ctx_xfer */
-	0x00f7f100,
-	0x06f4b60c,
-	0xd004e7f0,
-/* 0x0836: ctx_xfer_idle */
-	0xfecf80fe,
-	0x00e4f100,
-	0xf91bf420,
-	0xf40611f4,
-/* 0x0846: ctx_xfer_pre */
-	0xf7f01102,
-	0x9821f510,
-	0x3121f506,
-	0x1c11f406,
-/* 0x0854: ctx_xfer_pre_load */
-	0xf502f7f0,
-	0xf5065721,
-	0xf5066621,
-	0xbd067821,
-	0x5721f5f4,
-	0xb821f506,
-/* 0x086d: ctx_xfer_exec */
-	0x16019806,
-	0x041427f1,
-	0xd00624b6,
-	0xe7f10020,
-	0xe3f0a500,
-	0x021fb941,
-	0xb68d21f4,
-	0xfcf004e0,
-	0x022cf001,
-	0xfd0124b6,
-	0x21f405f2,
-	0xfc17f18d,
-	0x0213f04a,
-	0xd00c27f0,
-	0x21f50012,
-	0x27f10207,
-	0x23f047fc,
-	0x0020d002,
-	0xb6012cf0,
-	0x12d00320,
-	0x01acf000,
-	0xf006a5f0,
-	0x0c9800b7,
-	0x150d9814,
-	0xf500e7f0,
-	0xf0015c21,
-	0x21f508a7,
-	0x21f50103,
-	0x01f40207,
-	0x0ca7f022,
-	0xf1c921f4,
-	0xb60a1017,
-	0x27f00614,
-	0x0012d005,
-/* 0x08f4: ctx_xfer_post_save_wait */
-	0xfd0012cf,
-	0x1bf40522,
-	0x3202f4fa,
-/* 0x0900: ctx_xfer_post */
-	0xf502f7f0,
-	0xbd065721,
-	0x9821f5f4,
-	0x2621f506,
-	0x6621f502,
-	0xf5f4bd06,
-	0xf4065721,
-	0x01981011,
-	0x0511fd80,
-	0xf5070bf4,
-/* 0x092b: ctx_xfer_no_post_mmio */
-	0xf507df21,
-/* 0x092f: ctx_xfer_done */
-	0xf8064921,
-	0x00000000,
+	0x0089d005,
+/* 0x07b6: ctx_chan */
+	0x21f500f8,
+	0x21f50632,
+	0xa7f006b9,
+	0xc921f40c,
+	0x0a1017f1,
+	0xf00614b6,
+	0x12d00527,
+/* 0x07d1: ctx_chan_wait */
+	0x0012cf00,
+	0xf40522fd,
+	0x21f5fa1b,
+	0x00f8064a,
+/* 0x07e0: ctx_mmio_exec */
+	0xf1410398,
+	0xb60a0427,
+	0x23d00624,
+/* 0x07ef: ctx_mmio_loop */
+	0xc434bd00,
+	0x1bf4ff34,
+	0x0057f10f,
+	0x0653f002,
+	0xf80535fa,
+/* 0x0801: ctx_mmio_pull */
+	0x804e9803,
+	0xf4814f98,
+	0x30b68d21,
+	0x0112b608,
+/* 0x0813: ctx_mmio_done */
+	0x98df1bf4,
+	0x23d01603,
+	0x40008000,
+	0x010017f1,
+	0xfa0613f0,
+	0x03f80601,
+/* 0x082a: ctx_xfer */
+	0xf7f100f8,
+	0xf4b60c00,
+	0x04e7f006,
+/* 0x0837: ctx_xfer_idle */
+	0xcf80fed0,
+	0xe4f100fe,
+	0x1bf42000,
+	0x0611f4f9,
+/* 0x0847: ctx_xfer_pre */
+	0xf01102f4,
+	0x21f510f7,
+	0x21f50699,
+	0x11f40632,
+/* 0x0855: ctx_xfer_pre_load */
+	0x02f7f01c,
+	0x065821f5,
+	0x066721f5,
+	0x067921f5,
+	0x21f5f4bd,
+	0x21f50658,
+/* 0x086e: ctx_xfer_exec */
+	0x019806b9,
+	0x1427f116,
+	0x0624b604,
+	0xf10020d0,
+	0xf0a500e7,
+	0x1fb941e3,
+	0x8d21f402,
+	0xf004e0b6,
+	0x2cf001fc,
+	0x0124b602,
+	0xf405f2fd,
+	0x17f18d21,
+	0x13f04afc,
+	0x0c27f002,
+	0xf50012d0,
+	0xf1020721,
+	0xf047fc27,
+	0x20d00223,
+	0x012cf000,
+	0xd00320b6,
+	0xacf00012,
+	0x06a5f001,
+	0x9800b7f0,
+	0x0d98140c,
+	0x00e7f015,
+	0x015c21f5,
+	0xf508a7f0,
+	0xf5010321,
+	0xf4020721,
+	0xa7f02201,
+	0xc921f40c,
+	0x0a1017f1,
+	0xf00614b6,
+	0x12d00527,
+/* 0x08f5: ctx_xfer_post_save_wait */
+	0x0012cf00,
+	0xf40522fd,
+	0x02f4fa1b,
+/* 0x0901: ctx_xfer_post */
+	0x02f7f032,
+	0x065821f5,
+	0x21f5f4bd,
+	0x21f50699,
+	0x21f50226,
+	0xf4bd0667,
+	0x065821f5,
+	0x981011f4,
+	0x11fd4001,
+	0x070bf405,
+	0x07e021f5,
+/* 0x092c: ctx_xfer_no_post_mmio */
+	0x064a21f5,
+/* 0x0930: ctx_xfer_done */
+	0x000000f8,
 	0x00000000,
 	0x00000000,
 	0x00000000,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index 766870c4a27c..9d705bab9dcd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -745,9 +745,17 @@ nvc0_graph_init_unk60xx(struct nvc0_graph_priv *priv)
 static void
 nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
 {
-	nv_wr32(priv, 0x4064f0, 0x00000000);
-	nv_wr32(priv, 0x4064f4, 0x00000000);
-	nv_wr32(priv, 0x4064f8, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x4064f0, 0x00000000);
+		nv_wr32(priv, 0x4064f4, 0x00000000);
+		nv_wr32(priv, 0x4064f8, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 }
 
 static void
@@ -755,10 +763,26 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
 {
 	nv_wr32(priv, 0x405844, 0x00ffffff);
 	nv_wr32(priv, 0x405850, 0x00000000);
-	nv_wr32(priv, 0x405900, 0x00002834);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x405900, 0x00002834);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x405908, 0x00000000);
-	nv_wr32(priv, 0x405928, 0x00000000);
-	nv_wr32(priv, 0x40592c, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x405928, 0x00000000);
+		nv_wr32(priv, 0x40592c, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 }
 
 static void
@@ -770,19 +794,53 @@ nvc0_graph_init_unk80xx(struct nvc0_graph_priv *priv)
 static void
 nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
 {
-	nv_wr32(priv, 0x418408, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x418408, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x4184a0, 0x00000000);
-	nv_wr32(priv, 0x4184a4, 0x00000000);
-	nv_wr32(priv, 0x4184a8, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x4184a4, 0x00000000);
+		nv_wr32(priv, 0x4184a8, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x418604, 0x00000000);
 	nv_wr32(priv, 0x418680, 0x00000000);
-	nv_wr32(priv, 0x418714, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x418714, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		nv_wr32(priv, 0x418714, 0x80000000);
+		break;
+	}
 	nv_wr32(priv, 0x418384, 0x00000000);
 	nv_wr32(priv, 0x418814, 0x00000000);
 	nv_wr32(priv, 0x418818, 0x00000000);
 	nv_wr32(priv, 0x41881c, 0x00000000);
 	nv_wr32(priv, 0x418b04, 0x00000000);
-	nv_wr32(priv, 0x4188c8, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x4188c8, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		nv_wr32(priv, 0x4188c8, 0x80000000);
+		break;
+	}
 	nv_wr32(priv, 0x4188cc, 0x00000000);
 	nv_wr32(priv, 0x4188d0, 0x00010000);
 	nv_wr32(priv, 0x4188d4, 0x00000001);
@@ -794,22 +852,63 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
 	nv_wr32(priv, 0x418988, 0x77777777);
 	nv_wr32(priv, 0x41898c, 0x77777777);
 	nv_wr32(priv, 0x418c04, 0x00000000);
-	nv_wr32(priv, 0x418c64, 0x00000000);
-	nv_wr32(priv, 0x418c68, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x418c64, 0x00000000);
+		nv_wr32(priv, 0x418c68, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x418c88, 0x00000000);
-	nv_wr32(priv, 0x418cb4, 0x00000000);
-	nv_wr32(priv, 0x418cb8, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x418cb4, 0x00000000);
+		nv_wr32(priv, 0x418cb8, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x418d00, 0x00000000);
-	nv_wr32(priv, 0x418d28, 0x00000000);
-	nv_wr32(priv, 0x418d2c, 0x00000000);
-	nv_wr32(priv, 0x418f00, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x418d28, 0x00000000);
+		nv_wr32(priv, 0x418d2c, 0x00000000);
+		nv_wr32(priv, 0x418f00, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x418f08, 0x00000000);
-	nv_wr32(priv, 0x418f20, 0x00000000);
-	nv_wr32(priv, 0x418f24, 0x00000000);
-	nv_wr32(priv, 0x418e00, 0x00000003);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x418f20, 0x00000000);
+		nv_wr32(priv, 0x418f24, 0x00000000);
+		nv_wr32(priv, 0x418e00, 0x00000003);
+		break;
+	case 0xc0:
+	default:
+		nv_wr32(priv, 0x418e00, 0x00000050);
+		break;
+	}
 	nv_wr32(priv, 0x418e08, 0x00000000);
-	nv_wr32(priv, 0x418e1c, 0x00000000);
-	nv_wr32(priv, 0x418e20, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x418e1c, 0x00000000);
+		nv_wr32(priv, 0x418e20, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x41900c, 0x00000000);
 	nv_wr32(priv, 0x419018, 0x00000000);
 }
@@ -821,21 +920,64 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
 	nv_wr32(priv, 0x419d0c, 0x00000000);
 	nv_wr32(priv, 0x419d10, 0x00000014);
 	nv_wr32(priv, 0x419ab0, 0x00000000);
-	nv_wr32(priv, 0x419ac8, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x419ac8, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x419ab8, 0x000000e7);
 	nv_wr32(priv, 0x419abc, 0x00000000);
 	nv_wr32(priv, 0x419ac0, 0x00000000);
-	nv_wr32(priv, 0x419ab4, 0x00000000);
-	nv_wr32(priv, 0x41980c, 0x00000010);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x419ab4, 0x00000000);
+		nv_wr32(priv, 0x41980c, 0x00000010);
+		break;
+	case 0xc0:
+	default:
+		nv_wr32(priv, 0x41980c, 0x00000000);
+		break;
+	}
 	nv_wr32(priv, 0x419810, 0x00000000);
-	nv_wr32(priv, 0x419814, 0x00000004);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x419814, 0x00000004);
+		break;
+	case 0xc0:
+	default:
+		nv_wr32(priv, 0x419814, 0x00000000);
+		break;
+	}
 	nv_wr32(priv, 0x419844, 0x00000000);
-	nv_wr32(priv, 0x41984c, 0x0000a918);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x41984c, 0x0000a918);
+		break;
+	case 0xc0:
+	default:
+		nv_wr32(priv, 0x41984c, 0x00005bc5);
+		break;
+	}
 	nv_wr32(priv, 0x419850, 0x00000000);
 	nv_wr32(priv, 0x419854, 0x00000000);
 	nv_wr32(priv, 0x419858, 0x00000000);
 	nv_wr32(priv, 0x41985c, 0x00000000);
-	nv_wr32(priv, 0x419880, 0x00000002);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x419880, 0x00000002);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x419c98, 0x00000000);
 	nv_wr32(priv, 0x419ca8, 0x80000000);
 	nv_wr32(priv, 0x419cb4, 0x00000000);
@@ -845,25 +987,60 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
 	nv_wr32(priv, 0x419cc4, 0x00000000);
 	nv_wr32(priv, 0x419bd4, 0x00800000);
 	nv_wr32(priv, 0x419bdc, 0x00000000);
-	nv_wr32(priv, 0x419bf8, 0x00000000);
-	nv_wr32(priv, 0x419bfc, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x419bf8, 0x00000000);
+		nv_wr32(priv, 0x419bfc, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x419d2c, 0x00000000);
-	nv_wr32(priv, 0x419d48, 0x00000000);
-	nv_wr32(priv, 0x419d4c, 0x00000000);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x419d48, 0x00000000);
+		nv_wr32(priv, 0x419d4c, 0x00000000);
+		break;
+	case 0xc0:
+	default:
+		break;
+	}
 	nv_wr32(priv, 0x419c0c, 0x00000000);
 	nv_wr32(priv, 0x419e00, 0x00000000);
 	nv_wr32(priv, 0x419ea0, 0x00000000);
 	nv_wr32(priv, 0x419ea4, 0x00000100);
-	nv_wr32(priv, 0x419ea8, 0x02001100);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x419ea8, 0x02001100);
+		break;
+	case 0xc0:
+	default:
+		nv_wr32(priv, 0x419ea8, 0x00001100);
+		break;
+	}
 	nv_wr32(priv, 0x419eac, 0x11100702);
 	nv_wr32(priv, 0x419eb0, 0x00000003);
 	nv_wr32(priv, 0x419eb4, 0x00000000);
 	nv_wr32(priv, 0x419eb8, 0x00000000);
 	nv_wr32(priv, 0x419ebc, 0x00000000);
 	nv_wr32(priv, 0x419ec0, 0x00000000);
-	nv_wr32(priv, 0x419ec8, 0x0e063818);
-	nv_wr32(priv, 0x419ecc, 0x0e060e06);
-	nv_wr32(priv, 0x419ed0, 0x00003818);
+	switch (nv_device(priv)->chipset) {
+	case 0xd9:
+	case 0xd7:
+		nv_wr32(priv, 0x419ec8, 0x0e063818);
+		nv_wr32(priv, 0x419ecc, 0x0e060e06);
+		nv_wr32(priv, 0x419ed0, 0x00003818);
+		break;
+	case 0xc0:
+	default:
+		nv_wr32(priv, 0x419ec8, 0x06060618);
+		nv_wr32(priv, 0x419ed0, 0x0eff0e38);
+		break;
+	}
 	nv_wr32(priv, 0x419ed4, 0x011104f1);
 	nv_wr32(priv, 0x419edc, 0x00000000);
 	nv_wr32(priv, 0x419f00, 0x00000000);
@@ -1133,6 +1310,7 @@ nvc0_graph_init(struct nouveau_object *object)
 	nvc0_graph_init_regs(priv);
 
 	switch (nv_device(priv)->chipset) {
+	case 0xc0:
 	case 0xd9:
 	case 0xd7:
 		nvc0_graph_init_unk40xx(priv);