Just always take ours, same as git merge -X ours, but done by hand
because I didn't trust git: It's confusing that it doesn't show any
conflicts in the merge diff at all.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
In Indirect context w/a batch buffer,
+WaFlushCoherentL3CacheLinesAtContextSwitch:bdw
v2: Add LRI commands to set/reset bit that invalidates coherent lines,
update WA to include programming restrictions and exclude CHV as
it is not required (Ville)
v3: Avoid unnecessary read when it can be done by reading register once (Chris).
Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
In Indirect and Per context w/a batch buffer,
+WaDisableCtxRestoreArbitration
Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Arun Siluvery [Fri, 19 Jun 2015 17:37:11 +0000 (18:37 +0100)]
drm/i915/gen8: Re-order init pipe_control in lrc mode
Some of the WA applied using WA batch buffers perform writes to scratch page.
In the current flow WA are initialized before scratch obj is allocated.
This patch reorders intel_init_pipe_control() to have a valid scratch obj
before we initialize WA.
v2: Check for valid scratch page before initializing WA as some of them
perform writes to it.
Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Michel Thierry <michel.thierry@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Arun Siluvery [Fri, 19 Jun 2015 18:07:01 +0000 (19:07 +0100)]
drm/i915/gen8: Add infrastructure to initialize WA batch buffers
Some of the WA are to be applied during context save but before restore and
some at the end of context save/restore but before executing the instructions
in the ring, WA batch buffers are created for this purpose and these WA cannot
be applied using normal means. Each context has two registers to load the
offsets of these batch buffers. If they are non-zero, HW understands that it
need to execute these batches.
v1: In this version two separate ring_buffer objects were used to load WA
instructions for indirect and per context batch buffers and they were part
of every context.
v2: Chris suggested to include additional page in context and use it to load
these WA instead of creating separate objects. This will simplify lot of things
as we need not explicity pin/unpin them. Thomas Daniel further pointed that GuC
is planning to use a similar setup to share data between GuC and driver and
WA batch buffers can probably share that page. However after discussions with
Dave who is implementing GuC changes, he suggested to use an independent page
for the reasons - GuC area might grow and these WA are initialized only once and
are not changed afterwards so we can share them share across all contexts.
The page is updated with WA during render ring init. This has an advantage of
not adding more special cases to default_context.
We don't know upfront the number of WA we will applying using these batch buffers.
For this reason the size was fixed earlier but it is not a good idea. To fix this,
the functions that load instructions are modified to report the no of commands
inserted and the size is now calculated after the batch is updated. A macro is
introduced to add commands to these batch buffers which also checks for overflow
and returns error.
We have a full page dedicated for these WA so that should be sufficient for
good number of WA, anything more means we have major issues.
The list for Gen8 is small, same for Gen9 also, maybe few more gets added
going forward but not close to filling entire page. Chris suggested a two-pass
approach but we agreed to go with single page setup as it is a one-off routine
and simpler code wins.
One additional option is offset field which is helpful if we would like to
have multiple batches at different offsets within the page and select them
based on some criteria. This is not a requirement at this point but could
help in future (Dave).
Chris provided some helpful macros and suggestions which further simplified
the code, they will also help in reducing code duplication when WA for
other Gen are added. Add detailed comments explaining restrictions.
Use do {} while(0) for wa_ctx_emit() macro.
(Many thanks to Chris, Dave and Thomas for their reviews and inputs)
Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dave Gordon <david.s.gordon@intel.com> Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Thu, 18 Jun 2015 10:42:08 +0000 (11:42 +0100)]
drm/i915: Report an error when i915.reset prevents a reset
If the user disables the GPU reset using the i915.reset parameter and
one occurs, report that we failed to reset the GPU. If we return early,
as we currently do, then we leave all state intact (with a hung GPU)
and clients block forever waiting for their requests to complete.
Testcase: igt/gem_eio Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Mark i915.reset as an unsafe modoption, as discussed with
Chris.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Dave Airlie [Mon, 22 Jun 2015 04:40:44 +0000 (14:40 +1000)]
drm/dp/mst: take lock around looking up the branch device on hpd irq
If we are doing an MST transaction and we've gotten HPD and we
lookup the device from the incoming msg, we should take the mgr
lock around it, so that mst_primary and mstb->ports are valid.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
Daniel Vetter [Mon, 22 Jun 2015 07:31:59 +0000 (17:31 +1000)]
drm/dp/mst: make sure mst_primary mstb is valid in work function
This validates the mst_primary under the lock, and then calls
into the check and send function. This makes the code a lot
easier to understand the locking rules in.
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 23 Jun 2015 00:22:19 +0000 (10:22 +1000)]
Merge tag 'drm-intel-next-fixes-2015-06-22' of git://anongit.freedesktop.org/drm-intel into drm-next
fix warning introduced in last -fixes
* tag 'drm-intel-next-fixes-2015-06-22' of git://anongit.freedesktop.org/drm-intel:
drm/i915: Silence compiler warning
Dave Airlie [Tue, 23 Jun 2015 00:13:18 +0000 (10:13 +1000)]
Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
Summary:
. Add atomic feature support
- Exynos also now supports atomic feature. However, it doesn't
guarantee atomic operation yet, and is required for more cleanups.
This time we just modified for Exynos drm driver to use atomic
interfaces instead of legacy ones. Next time, we will enhance
Exynos drm driver to support the atomic operation.
. Add iommu support
- This is a patch series according to below Exynos iommu integration
work with DT and dma-mapping subsystem,
http://lwn.net/Articles/607626/
. Consolidate Exynos drm driver initialization.
- This patch sereis resolves the issue that only the first compoments
was bound when happened deferred probing for other pipelines and
also makes the driver to be more cleanned up by moving the dispered
codes for registering kms drivers to one place.
. Add new MIC, DECON drivers, and MIPI-DSI support for Exynos5433.
- Add MIC(Mobile image compressor) driver. MIC is a new IP for Exynos5433
and later, which is used to transfer frame data to MIPI-DSI controller
compressing the data to reduce memory bandwidth.
- Add DECON driver for Exynos5433 SoC. This IP is a dislay controller
similar to Exynos7's one but this controller has much different registers
from Exynos7's ones so this driver has been implemented separately.
We will implement a helper modules for FIMD and two DECON controllers
to remove duplicated codes later.
- Add Exynos5433 SoC support to MIPI-DSI driver, and device tree
relevant patches.
* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos: (50 commits)
ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi'
drm/exynos: dsi: do not set TE GPIO direction by input
drm/exynos: dsi: add support for MIC driver as a bridge
drm/exynos: dsi: add support for Exynos5433
drm/exynos: dsi: make use of array for clock access
drm/exynos: dsi: make use of driver data for static values
drm/exynos: dsi: add macros for register access
drm/exynos: dsi: rename pll_clk to sclk_clk
drm/exynos: mic: add MIC driver
of: add helper for getting endpoint node of specific identifiers
drm/exynos: add Exynos5433 decon driver
drm/exynos: fix the input prompt of Exynos7 DECON
drm/exynos: add drm_iommu_attach_device_if_possible()
drm/exynos: Add the dependency for DRM_EXYNOS to DPI/DSI/DP
drm/exynos: remove the dependency of DP driver for ARCH_EXYNOS
drm/exynos: do not wait for vblank at atomic operation
drm/exynos: Remove unused vma field of exynos_drm_gem_obj
drm/exynos: fimd: fix page fault issue with iommu
drm/exynos: iommu: improve a check for non-iommu dma_ops
drm/exynos: iommu: detach from default dma-mapping domain on init
...
Dave Airlie [Tue, 23 Jun 2015 00:12:40 +0000 (10:12 +1000)]
Merge tag 'topic/drm-misc-2015-06-22' of git://anongit.freedesktop.org/drm-intel into drm-next
One more drm-misc pull for 4.2. The important one is the fix from Laurent
for Daniel Stone's mode_blob work.
* tag 'topic/drm-misc-2015-06-22' of git://anongit.freedesktop.org/drm-intel:
drm/atomic: Don't set crtc_state->enable manually
drm: prime: Document gem_prime_mmap
drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()
drm/atomic: Extract needs_modeset function
drm/cma: Fix 64-bit size_t build warnings
Documentation/drm: Update rotation property
Chris Wilson [Fri, 19 Jun 2015 19:27:27 +0000 (20:27 +0100)]
drm/i915: Remove KMS Kconfig option
Since we only support modesetting by default (disabling modesetting on
the command line prevents i915.ko from loading), having a parameter to
disable modesstting by default is superfluous, i.e. saying
CONFIG_DRM_I915_KMS=n is equivalent to CONFIG_DRM_I915=n.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Veter <daniel.vetter@ffwll.ch> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Fri, 19 Jun 2015 12:57:43 +0000 (13:57 +0100)]
drm/i915: Ignore LVDS presence in VBT flag if the LVDS is enabled by BIOS
On older gen, pre-Ironlake, parts there is no hardwired pin to report
the presence of an LVDS panel. Instead, we have to rely on the VBT to
declare whether the machine has a panel or not. Though notoriously
unreliable, so far we have erred on the side of false-positives and have
required a list of machines which end up falsely reporting a panel as
present. However, we now have reports of false-negatives, machines with
an LVDS that are being ignored due to the VBT not declaring the panel.
This patch ignores the VBT setting if the BIOS has already enabled the
LVDS panel (and on Ironlake+ we also have the hardware presence pin).
It fixes the Samsung NP680Z5E-X01FR in the bug report, but is likely to
result in more false-positives, and since we rely on the BIOS to enable
the panel, there are likely different circumstances where the BIOS will
not enable that panel (and so we may see the same machine with and
without a panel all on the whim of the BIOS).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90979 Reported-and-tested-by: lysxia@gmail.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Chris Wilson [Fri, 19 Jun 2015 12:59:46 +0000 (13:59 +0100)]
drm/i915: Enforce execobject.alignment to be a power-of-two
Internal requirement for the alignment is that it must be a
power-of-two, so enforce rejection at the user interface to execbuffer
(which allows the caller to specify a stricter-than-expected alignment
criterion).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Ville Syrjälä [Thu, 18 Jun 2015 10:47:22 +0000 (13:47 +0300)]
drm/i915: Factor out p2 divider selection for pre-ilk platforms
The same dpll p2 divider selection is repeated three times in the
gen2-4 .find_dpll() functions. Factor it out.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Thu, 18 Jun 2015 10:06:16 +0000 (13:06 +0300)]
drm/i915: move generic hotplug code into new intel_hotplug.c file
We have enough generic hotplug functions sprinkled all over i915_irq.c
to warrant moving them to a file of their own. This should further
underline the distinction between generic code in the new file and
platform specific hotplug and irq code that remains in i915_irq.c.
Add new intel_hpd_init_work to keep work functions static, and rename
get_port_from_pin to intel_hpd_pin_to_port while increasing its
visibility, but keep everything else the same.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Thu, 18 Jun 2015 10:06:15 +0000 (13:06 +0300)]
drm/i915/irq: clarify irq storm related function naming
We'll have three functions:
intel_hpd_irq_storm_detect for detecting irq storms,
intel_hpd_irq_storm_disable for disabling hotplugs after detected storms,
intel_hpd_irq_storm_reenable_work for re-enabling hotplug.
No functional changes.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Continue abstracting hotplug storm related functions to clarify the
code. This time, abstract hotplug irq storm related hotplug
disabling. While at it, clean up the loop iterating over connectors for
readability.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Jani Nikula [Thu, 18 Jun 2015 10:06:13 +0000 (13:06 +0300)]
drm/i915/irq: move hotplug even debug print to second connector loop
The hotplug work function has two loops iterating over connectors, the
first for handling hotplug disabling due to irq storms and the second
for actually handling the hotplug events. Move the debug printing into
the second one, so we can abstract the storm handling better. This may
change the output ordering slightly when there are multiple simultaneous
hotplug events.
Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
The skylake scalers depend on the cdclk freq, but that frequency can
change during a modeset. So when a modeset happens calculate the new
cdclk in the atomic state. With the transitional helpers gone the
cached value can be used in the scaler, and committed after all
crtc's are disabled.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90874 Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by(IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Now that all planes are added during a modeset we can use the
calculated changes before disabling a plane, and then either commit
or force disable a plane before disabling the crtc.
The code is shared with atomic_begin/flush, except watermark updating
and vblank evasion are not used.
This is needed for proper atomic suspend/resume support.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90868 Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by(IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Read out the initial state, and add a quirk to force add all planes
to crtc_state->plane_mask during initial commit. This will disable
all planes during the initial modeset.
The initial plane quirk is temporary, and will go away when hardware
readout is fully atomic, and the watermark updates in intel_sprite.c
are removed.
Changes since v1:
- Unset state->visible on !primary planes.
- Do not rely on the plane->crtc pointer in intel_atomic_plane,
instead assume planes are invisible until modeset.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by(IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: remove force argument from disable_plane
The idea was good, but planes can have a fb even though
they're disabled. This makes the force argument useless
and always true, because only the commit function updates
state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by(IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: clean up atomic plane check functions, v2.
By passing crtc_state to the check_plane functions a lot of duplicated
code can be removed. There are still some transitional helper calls,
they will be removed later.
Changes since v1:
- Revert state->visible changes.
- Use plane->state->crtc instead of plane->crtc.
- Use drm_atomic_get_existing_crtc_state.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by(IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
It's easier to read separate functions for crtc and plane scaler state.
Changes since v1:
- Update documentation.
Changes since v2:
- Get rid of parameters to skl_update_scaler only used for traces.
This avoids needing to document the other parameters.
Changes since v3:
- Rename scaler_idx to scaler_user.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by(IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drm/i915: Move scaler setup to check crtc function, v2.
The scaler setup may add planes, but since they're unchanged we only
have to wait for primary flips. Also set planes_changed to indicate
at least 1 plane is modified.
Changes since v1:
- Instead of removing planes, do minimal validation needed.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Tested-by(IVB): Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Laurent Pinchart [Mon, 22 Jun 2015 10:37:46 +0000 (13:37 +0300)]
drm/atomic: Don't set crtc_state->enable manually
The enable field needs to be kept in sync with the mode_blob field. Call
drm_atomic_set_mode_prop_for_crtc() instead of setting enable to false
in order to dereference the mode blob correctly.
v2:
- Check the return value of drm_atomic_set_mode_prop_for_crtc()
- Drop the num_connectors local variable
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Hyungwon Hwang [Fri, 12 Jun 2015 12:59:09 +0000 (21:59 +0900)]
drm/exynos: dsi: do not set TE GPIO direction by input
On some board, TE GPIO should be configured properly thoughout pinctrl driver
as an wakeup interrupt. So this gpio should be configurable in the board's DT,
not being requested as a input pin.
Hyungwon Hwang [Fri, 12 Jun 2015 12:59:06 +0000 (21:59 +0900)]
drm/exynos: dsi: make use of array for clock access
This patch make the driver to use an array for clock access. The number
of clocks are different from the existing MIPI DSI driver and Exynos5433
MIPI DSI driver. So this patch is needed before adding support for
Exynos5433 MIPI DSI driver.
Hyungwon Hwang [Fri, 12 Jun 2015 12:59:05 +0000 (21:59 +0900)]
drm/exynos: dsi: make use of driver data for static values
Exynos MIPI DSI driver uses some static values such as address offsets,
register setting values, and etc. This patch makes the driver get those
values from the driver data.
Hyungwon Hwang [Fri, 12 Jun 2015 12:59:04 +0000 (21:59 +0900)]
drm/exynos: dsi: add macros for register access
This patch adds macros for register writing/reading. This is needed for
adding support Exynos5433 MIPI DSI driver, not by using if statement, but
by using driver data.
Hyungwon Hwang [Fri, 12 Jun 2015 12:59:03 +0000 (21:59 +0900)]
drm/exynos: dsi: rename pll_clk to sclk_clk
This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
is actually not the pll input clock for dsi. The pll input clock comes
from the board's oscillator directly. But for the backward
compatibility, the old clock name "pll_clk" is also OK.
Hyungwon Hwang [Fri, 12 Jun 2015 12:59:02 +0000 (21:59 +0900)]
drm/exynos: mic: add MIC driver
MIC(Mobile image compressor) is newly added IP in Exynos5433. MIC
resides between decon and mipi dsim, and compresses frame data by 50%.
With dsi, not display port, to send frame data to the panel, the
bandwidth is not enough. That is why this compressor is introduced.
Hyungwon Hwang [Fri, 12 Jun 2015 12:59:01 +0000 (21:59 +0900)]
of: add helper for getting endpoint node of specific identifiers
When there are multiple ports or multiple endpoints in a port, they have to be
distinguished by the value of reg property. It is common. The drivers can get
the specific endpoint in the specific port via this function. Now the drivers
have to implement this code in themselves or have to force the order of dt nodes
to get the right node.
Every CRTC drivers in Exynos DRM implements the code which checks
whether IOMMU is supported or not, and if supported enable it.
Making new helper for it generalize each CRTC drivers.
Hyungwon Hwang [Fri, 12 Jun 2015 12:58:57 +0000 (21:58 +0900)]
drm/exynos: Add the dependency for DRM_EXYNOS to DPI/DSI/DP
Without this dependency, Kbuild is confused and the configs below
them are not placed under Exynos DRM. This patch fixes it, so the
configs below them become to be placed under Exynos DRM.
Hyungwon Hwang [Fri, 12 Jun 2015 12:58:56 +0000 (21:58 +0900)]
drm/exynos: remove the dependency of DP driver for ARCH_EXYNOS
This dependency is a historical thing. It is added when this DP driver is
under media subsystem. Now because it is under Exynos DRM, this dependency
is not needed anymore.
Silence the following -Wmaybe-uninitialized warnings and make the code
more clear.
drivers/gpu/drm/i915/intel_display.c: In function ‘__intel_set_mode’:
drivers/gpu/drm/i915/intel_display.c:11844:14: warning: ‘crtc_state’ may be used uninitialized in this function [-Wmaybe-uninitialized]
return state->mode_changed || state->active_changed;
^
drivers/gpu/drm/i915/intel_display.c:11854:25: note: ‘crtc_state’ was declared here
struct drm_crtc_state *crtc_state;
^
drivers/gpu/drm/i915/intel_display.c:11868:6: warning: ‘crtc’ may be used uninitialized in this function [-Wmaybe-uninitialized]
if (crtc != intel_encoder->base.crtc)
^
drivers/gpu/drm/i915/intel_display.c:11853:19: note: ‘crtc’ was declared here
struct drm_crtc *crtc;
Reported-by: Chris Wilson <chris@chris-wilson.co.uk> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Inki Dae [Fri, 19 Jun 2015 11:53:03 +0000 (20:53 +0900)]
drm/exynos: do not wait for vblank at atomic operation
This patch resolves the issue that refresh rate got low
at extension mode test with fimd and vidi combination.
The problem was because atomic_commit callback waited
for the completion of vblank to gaurantee crtc relevant
registers are updated from shadow registers to real ones.
However, the waiting there is really unnecessary because
page flip operation does already it.
drm/exynos: Remove unused vma field of exynos_drm_gem_obj
The field 'vma' of 'exynos_drm_gem_obj' structure was introduced in 2a3098ff6c21 ("drm/exynos: add userptr feature for g2d module") but is
not referenced anywhere.
One instance of 'exynos_drm_gem_obj' may be mapped to multiple
user-space VMAs so 'vma' field does not look useful anyway.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Inki Dae [Fri, 12 Jun 2015 13:19:22 +0000 (22:19 +0900)]
drm/exynos: fimd: fix page fault issue with iommu
This patch resolves page fault issue with iommu and atomic feature
when modetest test application is terminated.
ENWIN_F field of WINCONx register enables or disable a dma channel to
each hardware overlay - the value of the field will be updated to real
register after vsync.
So this patch makes sure the dma channel is disabled by waiting for vsync
one time after clearing shadow registers to all dma channels.
Below shows the page fault issue:
setting mode 720x1280-60Hz@XR24 on connectors 31, crtc 29
freq: 59.99Hz
[ 34.831025] PAGE FAULT occurred at 0x20400000 by 11e20000.sysmmu(Page
table base: 0x6e324000)
[ 34.838072] Lv1 entry: 0x6e92dc01
[ 34.841489] ------------[ cut here ]------------
[ 34.846058] kernel BUG at drivers/iommu/exynos-iommu.c:364!
[ 34.851614] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[ 34.857428] Modules linked in:
<--snip-->
[ 35.210894] [<c02880d0>] (exynos_sysmmu_irq) from [<c00608f8>]
(handle_irq_event_percpu+0x78/0x134)
[ 35.219914] [<c00608f8>] (handle_irq_event_percpu) from [<c00609f0>]
(handle_irq_event+0x3c/0x5c)
[ 35.228768] [<c00609f0>] (handle_irq_event) from [<c0063698>]
(handle_level_irq+0xc4/0x13c)
[ 35.237101] [<c0063698>] (handle_level_irq) from [<c005ff7c>]
(generic_handle_irq+0x2c/0x3c)
[ 35.245521] [<c005ff7c>] (generic_handle_irq) from [<c02214ec>]
(combiner_handle_cascade_irq+0x94/0x100)
[ 35.254980] [<c02214ec>] (combiner_handle_cascade_irq) from
[<c005ff7c>] (generic_handle_irq+0x2c/0x3c)
[ 35.264353] [<c005ff7c>] (generic_handle_irq) from [<c0060248>]
(__handle_domain_irq+0x7c/0xec)
[ 35.273034] [<c0060248>] (__handle_domain_irq) from [<c0009434>]
(gic_handle_irq+0x30/0x68)
[ 35.281366] [<c0009434>] (gic_handle_irq) from [<c0012ec0>]
(__irq_svc+0x40/0x74)
drm/exynos: iommu: improve a check for non-iommu dma_ops
DRM Exynos driver is relying on dma-mapping internal structures when used
with IOMMU enabled. This patch partially hides dma-mapping internal things
by using proper get_dma_ops/set_dma_ops calls.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
drm/exynos: iommu: detach from default dma-mapping domain on init
This patch adds code, which detach sub-device nodes from default iommu
domain if such has been configured. This lets Exynos DRM driver to properly
attach sub-devices to its own, common for all sub-devices domain.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Marek Szyprowski [Fri, 12 Jun 2015 09:07:17 +0000 (11:07 +0200)]
drm/exynos: fimd: ensure proper hw state in fimd_clear_channel()
One should not do any assumptions on the stare of the fimd hardware
during driver initialization, so to properly reset fimd before enabling
IOMMU, one should ensure that all power domains and clocks are really
enabled. This patch adds pm_runtime and clocks management in the
fimd_clear_channel() function to ensure that any access to fimd
registers will be performed with clocks and power domains enabled.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Joonyoung Shim [Fri, 12 Jun 2015 08:27:16 +0000 (17:27 +0900)]
drm/exynos: initialize VIDCON0 when fimd is disabled
When the fimd is disabled by fimd_disable(), enabled overlay layers also
are disabled. If clocks for fimd are enabled by fimd_enable() on this
case, it can lead IOMMU page fault. The reason is that VIDCON0_ENVID and
VIDCON0_ENVID_F bits of VIDCON0 register are set still even though fimd
is disabled, so it may continue display output of prior when clocks for
fimd are enabled again.
Joonyoung Shim [Fri, 12 Jun 2015 11:34:28 +0000 (20:34 +0900)]
drm/exynos: remove chained calls to enable
With atomic modesetting all the control for CRTC, Planes, Encoders and
Connectors should come from DRM core, so the driver is not allowed to
enable or disable planes from inside the crtc_enable()/disable() call.
But it needs to disable planes with crtc_disable in exynos driver
internally. Because crtc is disabled before plane is disabled, it means
plane_disable just returns without any register changes, then we cannot
be sure setting register to disable plane when crtc is disable.
This patch removes this chainned calls to enable plane from exynos hw
drivers code letting only DRM core touch planes except to disable plane.
Also it leads eliminable enabled and resume of struct exynos_drm_plane.
Joonyoung Shim [Fri, 12 Jun 2015 08:27:14 +0000 (17:27 +0900)]
drm/exynos: remove to call mixer_wait_for_vblank
The reason waiting vblank is to be power gated and disabled clocks after
dma operation is completed. The dma operation is stopped already before
be power gated and clocks are disabled when mixer is disabled by commit 381be025ac1a6("drm/exynos: stop mixer before gating clocks during
poweroff"). Don't need to wait vblank anymore.
Hyungwon Hwang [Tue, 9 Jun 2015 03:45:15 +0000 (12:45 +0900)]
drm/exynos: ipp: validate a GEM handle with multiple planes
FIMC & GSC driver can calculate the offset of planes. So there are
use cases which IPP receives just one GEM handle of an image with
multiple plane. This patch extends ipp_validate_mem_node() to validate
this case.
Hyungwon Hwang [Thu, 11 Jun 2015 14:40:30 +0000 (23:40 +0900)]
drm/exynos: dsi: check whether dsi is enabled before sending data
exynos_dsi_host_transfer() can be called through a panel driver while
DSI is turning down. It is possible because the function checks only
whether DSI is initialized or not, and there is a moment which DSI is
set by uninitialized, but DSI is still turning down. To prevent it,
DSI must be set by disabled before starting to be turned down, and
exynos_dsi_host_transfer() must check whether DSI is enabled or not.
Andrzej Hajda [Mon, 8 Jun 2015 10:15:42 +0000 (12:15 +0200)]
drm/exynos: remove SoC checking code
SoC checking code is not necessary anymore, as exynos_drm_match_add and
exynos_drm_platform_probe already properly handles situation when there are
no Exynos DRM components.
Andrzej Hajda [Thu, 11 Jun 2015 14:23:37 +0000 (23:23 +0900)]
drm/exynos: fix broken component binding in case of multiple pipelines
In case there are multiple pipelines and deferred probe occurs, only components
of the first pipeline were bound. As a result only one pipeline was available.
The main cause of this issue was dynamic generation of component match table -
every component driver during probe registered itself on helper list, if there
was at least one pipeline present on this list component match table were
created without deferred components.
This patch removes this helper list, instead it creates match table from
existing devices requiring exynos_drm KMS drivers. This way match table do not
depend on probe/deferral order and contains all KMS components.
As a side effect patch makes the code cleaner and significantly smaller.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Code registering different drivers and simple platform devices was dispersed
across multiple sub-modules. This patch moves it to one place. As a result
initialization code is shorter and cleaner and should simplify further
development.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Gustavo Padovan [Mon, 1 Jun 2015 15:04:53 +0000 (12:04 -0300)]
drm/exynos: atomic dpms support
Run dpms operations through the atomic intefaces. This basically removes
the .dpms() callback from econders and crtcs and use .disable() and
.enable() to turn the crtc on and off.
v2: Address comments by Joonyoung:
- make hdmi code call ->disable() instead of ->dpms()
- do not use WARN_ON on crtc enable/disable
v3: - Fix build failure after the hdmi change in v2
- Change dpms helper of ptn3460 bridge
v4: - remove win_commit() call from .enable()
v5: - move .atomic_check() to the atomic PageFlip patch, and transform it
in .atomic_begin()
Gustavo Padovan [Mon, 1 Jun 2015 15:04:52 +0000 (12:04 -0300)]
drm/exynos: add exynos specific .atomic_commit()
exynos needs to update planes with the crtc enabled (mainly for the FIMD
case) so this specific atomic commit changes the order of
drm_atomic_helper_commit_modeset_enables() and
drm_atomic_helper_commit_planes() to commit planes after we enable crtc
and encoders.
Gustavo Padovan [Mon, 1 Jun 2015 15:04:51 +0000 (12:04 -0300)]
drm/exynos: move exynos_drm_crtc_disable()
This is a preparation commit to move exynos_drm_crtc_disable() together
with the future exynos_drm_crtc_enable() that will come from the split of
exynos_drm_crtc_dpms() callback.
Gustavo Padovan [Mon, 1 Jun 2015 15:04:49 +0000 (12:04 -0300)]
drm/exynos: remove exported functions from exynos_drm_plane
Now that no one is using the functions exported by exynos_drm_plane due
to the atomic conversion we can make remove some of the them or make them
static.
Gustavo Padovan [Mon, 1 Jun 2015 15:04:44 +0000 (12:04 -0300)]
drm/exynos: atomic phase 2: wire up state reset(), duplicate() and destroy()
Set CRTC, planes and connectors to use the default implementations from
the atomic helper library. The helpers will work to keep track of state
for each DRM object.
Gustavo Padovan [Mon, 1 Jun 2015 15:04:41 +0000 (12:04 -0300)]
drm/exynos: atomic phase 1: use drm_plane_helper_update()
Rip out the check from exynos_update_plane() and create
exynos_check_plane() for the check phase enabling use to use
the atomic helpers to call our check and update phases when updating
planes.
Update all users of exynos_update_plane() accordingly to call
exynos_check_plane() before.
Chris Wilson [Wed, 10 Jun 2015 14:58:01 +0000 (15:58 +0100)]
drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range()
As the clflush operates on cache lines, and we can flush any byte
address, in order to flush all bytes given in the range we issue an
extra clflush on the last byte to ensure the last cacheline is flushed.
We can can the iteration to be over the actual cache lines to avoid this
double clflush on the last byte.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Dave Airlie [Fri, 19 Jun 2015 02:01:39 +0000 (12:01 +1000)]
Merge tag 'drm-intel-next-fixes-2015-06-18' of git://anongit.freedesktop.org/drm-intel into drm-next
i915 fixes for stuff in next
* tag 'drm-intel-next-fixes-2015-06-18' of git://anongit.freedesktop.org/drm-intel:
drm/i915: Don't set enabled value of all CRTCs when restoring the mode
drm/i915: Don't update staged config during force restore modesets
drm/i915: Don't check modeset state in the hw state force restore path
drm/i915: Add SCRATCH1 and ROW_CHICKEN3 to the register whitelist.
drm/i915: Extend the parser to check register writes against a mask/value pair.
drm/i915: Fix command parser to validate multiple register access with the same command.
drm/i915: Don't skip request retirement if the active list is empty
Mika Kuoppala [Thu, 18 Jun 2015 09:51:40 +0000 (12:51 +0300)]
drm/i915: Reset request handling for gen8+
In order for gen8+ hardware to guarantee that no context switch
takes place during engine reset and that current context is properly
saved, the driver needs to notify and query hw before commencing
with reset.
There are gpu hangs where the engine gets so stuck that it never will
report to be ready for reset. We could proceed with reset anyway, but
with some hangs with skl, the forced gpu reset will result in a system
hang. By inspecting the unreadiness for reset seems to correlate with
the probable system hang.
We will only proceed with reset if all engines report that they
are ready for reset. If root cause for system hang is found and
can be worked around with another means, we can reconsider if
we can reinstate full reset for unreadiness case.
References: https://bugs.freedesktop.org/show_bug.cgi?id=89959
References: https://bugs.freedesktop.org/show_bug.cgi?id=90854
Testcase: igt/gem_concurrent_blit/prw-blt-overwrite-source-read-rcs-forked
Testcase: igt/gem_concurrent_blit/gtt-blt-overwrite-source-read-rcs-forked Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Tomas Elf <tomas.elf@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
projects / karo-tx-linux.git / log