Sandor Yu [Fri, 23 Jan 2015 06:18:01 +0000 (14:18 +0800)]
MLK-10137:csi: Return physical address in querybuffer call
GST application want to use physical address even video buffer
allocated with type of V4L2_MEMORY_MMAP.
So add a trick in querybuffer function, if video buffer flags
is setting to V4L2_BUF_FLAG_MAPPED, overwirte m.offset with
physical address.
Bai Ping [Thu, 29 Jan 2015 11:09:39 +0000 (19:09 +0800)]
MLK-10175 arm: imx6: Skip gating QSPI2 clk when M4 is enabled
When the M4 core is enabled on i.MX6, the QSPI2 clk can't be gated,
otherwise, the M4 will hang. This patch add a check to make sure when
M4 is enabled, just skip the QSPI2 clk gating operations.
Li Jun [Wed, 10 Sep 2014 09:49:33 +0000 (17:49 +0800)]
ENGR00325832 usb: chipidea: usb vbus glitch check logic change
This patch changes the vbus glitch check to cover usb otg certification
case, so the possible cases of vbus rise:
- USB vbus can reach AVV(4.4v), valid vbus.
- USB vbus keeps above BSV(0.8v) but lower than AVV(4.4v) for
more than 300ms, we think it's valid vbus event, this can meet
usb otg certificataion case(B device can do connection in 1s when
vbus is 4.0v).
- USB vbus cannot be kept above BSV(0.8v) for more than 300ms,
it's a vbus glitch.
In case of vbus drop: if the vbus on flag is not set, it's a vbus glitch,
otherwise it's a valid vbus drop event.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit de5ab444839b6d1492d697256ea2b8a1dcaffc62)
We add vbus glitch handling for both BSV rise and drop interruptes.
If it is a vbus glitch (higher than BSV but cannot reach AVV), ignore it.
Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 827f2fe71e6222882930db7e89460087cb3bce5b)
Shengjiu Wang [Tue, 27 Jan 2015 08:44:34 +0000 (16:44 +0800)]
MLK-10161-3: ARM: imx6sx: Add SPDIF_GCLK clock in clock tree
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu Wang [Tue, 27 Jan 2015 08:43:17 +0000 (16:43 +0800)]
MLK-10161-2: ARM: imx6sl: Add SPDIF_GCLK clock in clock tree
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Shengjiu Wang [Tue, 27 Jan 2015 08:24:53 +0000 (16:24 +0800)]
MLK-10161-1: ARM: imx6q: Add SPDIF_GCLK clock in clock tree
As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Li Jun [Tue, 27 Jan 2015 09:11:14 +0000 (17:11 +0800)]
MLK-10101-4 usb: add otg_fsm pointer in usb_bus
Add otg_fsm pointer in struct of usb_bus for access otg_fsm via bus.
Original way was to put it in usb_otg, then usb host can access otg_fsm via
hcd->usb_phy->otg->fsm, since usb_phy will not be the future direction, instead
phy is prefered, so this way may not work. It's more direct and simple to put
it in usb_bus.
Li Jun [Sun, 28 Sep 2014 05:55:01 +0000 (13:55 +0800)]
MLK-9618-1 doc: usb: chipidea: select gadget drivers for otg compliance test
This patch adds guide for selecting available gadget drivers for otg and EH
compliance tests.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 520cac9e4fe938887dd45b5b4df6c8e35e125a59)
Li Jun [Mon, 1 Sep 2014 07:44:15 +0000 (15:44 +0800)]
MLK-9617-2 usb: gadget: set bcdOTG of OTG descriptor for gadget drivers
This patch sets bcdOTG field of OTG descriptor for below 3 gadget drivers:
- ether
- mass storage
- serial
OTG and EH supplement release number in binary-coded decimal(i.e. 2.0 is 0200H).
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit a426ace68acd9b770ce3a609f92029782b8ca1d1)
Li Jun [Thu, 9 Jan 2014 02:25:55 +0000 (10:25 +0800)]
MLK-9617-1 usb: otg: update otg descriptor definition for OTG and EH 2.0
Add one field bcdOTG for OTG and EH supplement release number in OTG
descriptor according to On-The-Go and Embedded Host Supplement to the
USB Revision 2.0 Specification Revision 2.0 version 1.1a.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit 1bf5e829100a2922826818bd8cbb18ee81452cfc)
The default TPL is for USB OTG & EH compliance test, the supported
class is: mass storage, hub, and hid.
Besides, we add one match criterion that matching targeted device
through class at interface descriptor.
Tested-by: Li Jun <b47624@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com>
(cherry picked from commit 483c071d989ceb36cacf76e1e3e779c67e5b8280)
Li Jun [Mon, 22 Sep 2014 08:19:59 +0000 (16:19 +0800)]
ENGR00331016-5 usb: chipidea: otg: clear b_bus_req when vbus is off
In case of b_peripheral --> b_wait_acon --> b_idle due to vbus off
in b_wait_acon state, b_bus_req cannot be cleared in b_idle state,
which result in b device will do data pulse because b_bus_req is set.
This patch fix this issue by clear the input variable b_bus_req when
vbus is off.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit bc600546bf9193f1a39186ad4c07a5fd497c7bfd)
Since BSV irq is enabled for B-device all the time, so B_SESS_VLD timer
is not required, and also no need to check BSV status when B_ASE0_BRST
timer timeout.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
(cherry picked from commit a7d0b864b613c555add9ea864eb8c163e1d3362e)
Li Jun [Tue, 27 Jan 2015 07:01:57 +0000 (15:01 +0800)]
MLK-10101-3 usb: chipidea: otg: enable BSV irq when OTG B-device in host mode
When B-device in host mode, if Vbus is off by A-device or A-device is removed,
B-device should update charger status correctly. This patch enables BSV irq
for B-device in all states, so the charger connection and removal can be early
handled by BSV change irq.
Li Jun [Tue, 27 Jan 2015 03:30:35 +0000 (11:30 +0800)]
MLK-10101-2 usb: chipidea: otg: delay to enter low power mode for a_host
There is 2s delay for controller resume from usb wakeup case already,
in OTG fsm mode, A-dev can start a new session via sys input file(means
not via usb wakeup), in this case, A-dev still need the 2s delay for
host root hub access registers, otherwise system will hang due to access
register at low power mode.
Peter Chen [Fri, 3 Jan 2014 05:45:30 +0000 (13:45 +0800)]
ENGR00292408-2 usb: chipidea: imx: enable different wakeup setting
We have different wakeup setting for different roles:
For peripheral-only mode, we may only enable vbus wakeup.
The Micro-AB cable should not be considered as wakeup source.
For host-only mode, the ID change or vbus change should not be
considered as wakeup source.
For OTG mode, all wakeup setting should be considered as wakeup
source.
Peter Chen [Mon, 22 Sep 2014 08:45:39 +0000 (16:45 +0800)]
ENGR00324639 usb: chipidea: set ITC to 0 for device mode
ITC (Interrupt Threshold Control) is used to set the maximum rate at which
the host/device controller will issue interrupts. The default value is 8 (1ms)
for it. EHCI core will modify it to 1, but device mode keeps it as default
value.
In some use cases like this CR, it uses Android ADB to transfer data, ADB
only has one usb request for each direction, and maximum payload data is
only 4KB, so the speed is 4MB/s at most, it needs controller to trigger
interrupt as fast as possible to increase the speed. The USB performance
will be better if the interrupt can be triggered faster.
In this case, we set ITC default value as 0, which will trigger USB interrupt
immediately once the transfer has completed.
Peter Chen [Wed, 5 Nov 2014 06:58:32 +0000 (14:58 +0800)]
MLK-9785-5 usb: chipidea: usbmisc_imx: add unburst setting for imx6
With this setting and AHBBRST at SBUSCFG as "Incremental burst of
unspecified length", each unburst size can be taken as one single transfer.
It is benefit for unburst size transfer.
For imx6, below AHB burst setting are better performance:
- Incremental burst of unspecified length, see SBUSCFG, $BASE + 0x90
- Set Both RX/TX burst size as 16 DWords, see BURSTSIZE, $BASE + 0x160
The AHBBRST at SBUSCFG and RX/TX burst size at BURSTSIZE are implementation
dependent, each platform may have different values, and some values may not be
optimized.
The glue layer can override ahb burst configuration value by setting flag
CI_HDRC_OVERRIDE_AHB_BURST and ahbburst_config.
The glue layer can override RX/TX burst size by setting flag
CI_HDRC_OVERRIDE_BURST_LENGTH and burst_length.
Peter Chen [Tue, 4 Nov 2014 12:46:15 +0000 (20:46 +0800)]
MLK-9785-1 usb: host: ehci-hcd: enable park mode
Enable park mode will improve the performance a lot at USB ethernet use
case, but a little at USB mass storage use case, and it is not harm from
the tests. Below the performance comparison at imx6sl:
USB Ethernet (Mbps)
Default Enable Park
TX 192 262
RX 262 290
USB Mass Storage (MB/s)
Read 21.8 22.9
Write 19.5 22.8
Peter Chen [Thu, 30 Oct 2014 03:10:04 +0000 (11:10 +0800)]
MLK-9770-3 usb: chipidea: imx: add stream mode enable for device mode at imx6sl/imx6sx
Stream mode enable is known for better performance
(eg, rx at g_ncm: 175Mbps->250Mbps), and stream mode
enable has been passed with stress tests at device mode
for imx6sl and imx6sx, and no issue is found.
Peter Chen [Thu, 30 Oct 2014 01:15:15 +0000 (09:15 +0800)]
MLK-9770-2 usb: chipidea: define stream mode disable for both roles
The chipidea IP has different limitations for host and device mode,
see below errata, we may need to enable SDIS(Stream Disable Mode)
at host mode, but we don't want it at device mode at some situations.
TAR 9000378958
Title: Non-Double Word Aligned Buffer Address Sometimes Causes Host to Hang on OUT Retry
Impacted Configuration: Host mode, all transfer types
Description:
The host core operating in streaming mode may under run while sending the data packet of an OUT transaction. This under run can occur if there are unexpected system delays in fetching the remaining packet data from memory. The host forces a bad CRC on the packet, the device detects the error and discards the packet. The host then retries a Bulk, Interrupt, or Control transfer if an under run occurs according to the USB specification.
During simulations, it was found that the host does not issue the retry of the failed bulk OUT. It does not issue any other transactions except SOF packets that have incorrect frame numbers.
The second failure mode occurs if the under run occurs on an ISO OUT transaction and the next ISO transaction is a zero byte packet. The host does not issue any transactions (including SOFs). The device detects a Suspend condition, reverts to full speed, and waits for resume signaling.
A third failure mode occurs when the host under runs on an ISO OUT and the next ISO in the schedule is an ISO OUT with two max packets of 1024 bytes each.
The host should issue MDATA for the first OUT followed by DATA1 for the second. However, it drops the MDATA transaction, and issues the DATA1 transaction.
The system impact of this bug is the same regardless of the failure mode observed. The host core hangs, the ehci_ctrl state machine waits for the protocol engine to send the completion status for the corrupted transaction, which never occurs. No indication is sent to the host controller driver, no register bits change and no interrupts occur. Eventually the requesting application times out.
Detailed internal behavior:
The EHCI control state machine (ehci_ctrl) in the DMA block is responsible for parsing the schedules and initiating all transactions. The ehci_ctrl state machine passes the transaction details to the protocol block by writing the transaction information in to the TxFIFO. It then asserts the pe_hst_run_pkt signal to inform the host protocol state machine (pe_hst_state) that there is a packet in the TxFIFO.
A tag of 0x0 indicates a start of packet with the data providing the following information:
35:32 Tag
31:30 Reserved
29:23 Endpoint (lowest 4 bits)
22:16 Address
15:10 Reserved
9:8 Endpoint speed
7:6 Endpoint type
5:6 Data Toggle
3:0 PID
The pe_hst_state reads the packet information and constructs the packet and issues it to the PHY interface.
The ehci_ctrl state machine writes the start transaction information in to the TxFIFO as 0x03002910c for the OUT packet that had the under run error. However, it writes 0xC3002910C for the retry of the Out transaction, which is incorrect.
The pe_hst_state enters a bus timeout state after sending the bad CRC for the packet that under ran. It then purges any data that was back filled in to the TxFIFO for the packet that under ran. The pe_hst_state machine stops purging the TxFIFO when it is empty or if it reads a location that has a tag of 0x0, indicating a start of packet command.
The pe_hst_state reads 0xC3002910C and discards it as it does not decode to a start of packet command. It continues to purge the OUT data that has been pre-buffered for the OUT retry . The pe_hst_state detects the hst_packet_run signal and attempts to read the PID and address information from the TxFIFO. This location has packet data and so does not decode to a valid PID and so falls through to the PE_HST_SOF_LOAD state where the frame_num_counter is updated. The frame_num_counter is updated with the data in the TxFIFO. In this case, the data is incorrect as the ehci_ctrl state machine did not initiate the load. The hst_pe_state machine detects the SOF request signal and sends an SOF with the bad frame number. Meanwhile, the ehci_ctrl state machine waits indefinitely in the run_pkt state waiting for the completion status from pe_hst_state machine, which will never happen.
The ISO failure case is similar except that there is no retry for ISO. The ehci_ctrl state machine moves to the next transfer in the periodic schedule. If the under run occurs on the last entry of the periodic list then it moves to the Async schedule.
In the case of ISO OUT simulations, the next ISO is a zero byte OUT and again the start of packet command gets corrupted. The TxFIFO is empty when the hst_pe_state attempts to read the Address and PID information as the transaction is a zero byte packet. This results in the hst_pe_state machine staying in the GET_PID state, which means that it does not issue any transactions (including SOFs). The device detects a Suspend condition and reverts to full speed mode and waits for a Resume or Reset signal.
The EHCI specification allows a Non-DoubleWord (32 bits) offset to be used as a current offset for Buffer Pointer Page 0 of the qTD. In Non-DoubleWord aligned cases, the core reads the packet data from the AHB memory, performs the alignment operation before writing it in to the TxFIFO as a 32 bit data word. An End Of Packet tag (EOP) is written to the TxFIFO after all the packet data has been written in to the TxFIFO. The alignment function is reset to Idle by the EOP tag. The corruption of the start of packet command arises because the packet buffer for the OUT transaction that under ran is not aligned to a DoubleWord, and hence no EOP tag is written to the TxFIFO. The alignment function is still active when the start packet information is written in to the TxFIFO for the retry of the bulk packet or for the next transaction in the case of an under run on an ISO. This results in the corruption of the start tag and the transaction information.
Click for waveform showing the command 0x 0000300291 being written in to the TX FIFO for the Out that under ran.
Click for waveform showing the command 0xC3002910C written to the TxFIFO instead of 0x 0000300291
Versions affected: Versions 2.10a and previous versions
How discovered: Customer simulation
Workaround:
1- The EHCI specification allows a non-DoubleWord offset to be used as a current offset for Buffer Pointer Page 0 of the qTD. However, if a DoubleWord offset is used then this issue does not arise.
2- Use non streaming mode to eliminate under runs.
Resolution:
The fix involves changes to the traffic state machine in the vusb_hs_dma_traf block. The ehci_ctrl state machine updates the context information by encoding the transaction results on the hst_op_context_update signals at the end of a transaction. The signal hst_op_context_update is added to the traffic state machine, and the tx_fifo_under_ran_r signal is generated if the transaction results in an under run error. Click for waveform
The traffic state machine then traverses to the do_eop states if the tx_fifo_under_ran error is asserted. Thus an EOP tag is written in to the TxFIFO as shown in this waveform .
The EOP tag resets the align state machine to the Idle state ensuring that the next command written by the echi_ctrl state machine does not get corrupted.
File(s) modified:
RTL code fixed: …..
Method of reproducing: This failure cannot be reproduced in the current test bench.
Date Found: March 2010
Date Fixed: June 2010
Update information:
Added the RTL code fix
Peter Chen [Sat, 13 Sep 2014 07:10:04 +0000 (15:10 +0800)]
ENGR00325724-4 usb: chipidea: udc: disconnect host if system enters suspend
It is better we disconnect (pulldown dp) host when the system enters
suspend if the host did not suspend bus beforehand, it can avoid
unnecessary udc suspend irq during usb enters suspend. This unexpected
suspend irq occurs due to the udc still pulls up dp, but the host
suspends bus due to it finds the device has disconnected. The device
turns off high speed terminal will be considered a disconnection event
from the host.
Peter Chen [Tue, 26 Nov 2013 05:33:21 +0000 (13:33 +0800)]
ENGR00289645 usb: chipidea: udc: don't do hardware access if gadget has stopped
After _gadget_stop_activity is executed, we can consider the hardware
operation for gadget has finished, and the udc can be stopped and enter
low power mode. So, any later hardware operations (from usb_ep_ops APIs
or usb_gadget_ops APIs) should be considered invalid, any deinitializatons
has been covered at _gadget_stop_activity.
I meet this problem when I plug out usb cable from PC (using g_mass_storage),
my callstack like: vbus interrupt->.vbus_session->composite_disconnect
->pm_runtime_put_sync(&_gadget->dev), the composite_disconnect will
call fsg_disable, but fsg_disable calls usb_ep_disable using async way,
there are register accesses for usb_ep_disable. So sometimes, I get system
hang due to visit register without clock, sometimes not.
The Linux Kernel USB maintainer Alan Stern suggests this kinds of solution.
See: http://marc.info/?l=linux-usb&m=138541769810983&w=2.
Richard Zhu [Mon, 26 Jan 2015 06:35:14 +0000 (14:35 +0800)]
MLK-10146 arm: mcc: fix one compile error when DYNAMIC_DEBUG is set
When CONFIG_DYNAMIC_DEBUG is configured, there is one
compile error in mcc_linux.c file, the memcpy() is not
defined.
Fix it by including the linux/string.h header explicitly.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
Li Jun [Tue, 20 Jan 2015 08:03:38 +0000 (16:03 +0800)]
MLK-10086-3 usb: phy-nop: add the implementation of .set_suspend
Add clock enable/disable at .set_suspend if the PHY has
suspend requirement, it can be benefit of power saving for
phy and the whole system (parent clock may also be disabled).
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Li Jun [Tue, 20 Jan 2015 08:03:36 +0000 (16:03 +0800)]
MLK-10086-2 ARM: imx6: add dts entries for hsic controller
- Add usbphy_nop, hsic uses nop phy driver
- Add anatop phandle, hsic needs to access anatop register to
change osc clock for different boards
- Add phy_type, hsic needs to config PHY parameters at portsc
- For imx6q-arm2 board, hsic has pin conflict with ethernet, we create a
dedicated dts(imx6q-arm2-hsic.dts) for it with ethernet disabled, besides
please make sure keep the line of data and strobe unchanged between board
boots up and enable hsic controller.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Li Jun [Fri, 23 Jan 2015 10:35:35 +0000 (18:35 +0800)]
MLK-10132-3 usb: chipidea: udc: do not enter low power mode if vbus on
This patch is to prevent usb entering low power mode if vbus is on even gadget
driver is not binded, by holding the PM count of ci->dev.
So, there are 3 pm usage_count status:
- ci->dev: 1 ci->gadget.dev: 1
Device mode with gadget driver binded and vbus on.
- ci->dev: 1 ci->gadget.dev: 0
USB vbus on but gadget driver not binded.
- ci->dev: 0 ci->gadget.dev: 1
USB OTG FSM is in a_peripheral mode.
Above 2 device's pm usage_count hold by ci otg(ci->dev) and usb gadget
(ci->gadget.dev).
Li Jun [Mon, 24 Nov 2014 02:00:18 +0000 (10:00 +0800)]
MLK-9897-1 usb: chipidea: otg: use shared queue to handle hnp polling
This patch moves out hnp polling from usb otg work queue to shared queue, as
hnp polling call to usb_control_msg() which sends a control message and waits
for it complete or timeout, so it's not proper to handle it in usb otg work
queue which handles work with usb irq disabled.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <jun.li@freescale.com>
(cherry picked from commit a147c8808ad198a7b9694b7dd517166505b76c50)
There have one bug in .fec_enet_tx_queue() function to unmap the DMA memory:
For SG or TSO, get one buffer descriptor and then unmap the related DMA memory, and then
get the next buffer descriptor, loop to while() to check "TX_READY". If "TX_READY" bit
still __IS__ existed in the BD (The next fraglist or next TSO packet is not transmited
complitely), exit the current clean work. When the next work is triggered, it still repeat
above step with the same BD. The potential issue is that unmap the same DMA memory for
multiple times.
The patch fix the clean work for SG and TSO packet.
Reported-by: Anand Moon <moon.linux@yahoo.com> Reported-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Dong Aisheng [Thu, 22 Jan 2015 13:48:07 +0000 (21:48 +0800)]
MLK-10131 flexcan: fix wakeup unwork issue
Original code will always disable flexcan during suspend no matter whether
wakeup feature is enabled.
It's caused by merge issue when doing kernel upgrade.
"The GCC 4.8.1 compiler will not do the for-loop till scat_entries, instead,
it only run one round loop. This may be caused by that the GCC 4.8.1 thought
that the scat_list only have one item and then no need to do full iteration,
but this is simply wrong by looking at the assebly code. This will cause the sg
buffer not get set when scat_entries > 1 and thus lead to kernel panic.
Note: This issue not observed with GCC 4.7.2, only found on the GCC 4.8.1)"
Fix this by using the normal [0] style for defining unknown number of list
entries following the struct. This also fixes corruption with scat_q_depth, which
was mistankely added to the end of struct and overwritten if there were more
than item in the scat list.
Reported-by: Jason Liu <r64343@freescale.com> Tested-by: Jason Liu <r64343@freescale.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
Sandor Yu [Wed, 21 Jan 2015 05:33:01 +0000 (13:33 +0800)]
MLK-10117-3:csi: remove runtime suspend/resume function
CSI v4l2 capture driver have involved to generic pm domain,
runtime_suspend/resume function will been called when system
suspend/resume. It will cause request_bus_freq/release_bus_freq
called counter mismatch.
So move request_bus_freq/release_bus_freq function to
device open/close function.
Sandor Yu [Wed, 21 Jan 2015 05:27:24 +0000 (13:27 +0800)]
MLK-10117-2:pxp: Remove runtime suspend/resume function
pxp module have involved to generic pm domain,
runtime_suspend/resume function will called when system
suspend/resume. It will cause request_bus_freq/release_bus_freq
called counter mismatch.
So move request_bus_freq/release_bus_freq to clk_enable/disable
function.
Li Jun [Wed, 24 Dec 2014 10:23:39 +0000 (18:23 +0800)]
MLK-10051-2 usb: common: otg: set feature of b_hnp_enable after host request flag is set
The A-device is required to set this feature and suspend the bus within
THOST_REQ_SUSP when it determines that the B-device wishes to become host
(host_req_flag = TRUE). So this patch does this if host request flag is set
and a_set_b_hnp_en has not been set.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <jun.li@freescale.com>
Li Jun [Mon, 23 Jun 2014 07:50:50 +0000 (15:50 +0800)]
ENGR00319720-5 usb: chipidea: udc: add OTG status request handling
Peripheral answers OTG status selector request from host according to
host request flag of gadget, length is 1. this flag may be set by application
via sysfs.
Li Jun [Tue, 4 Nov 2014 12:12:31 +0000 (20:12 +0800)]
MLK-9794-2 usb: common: otg: clear host_request_flag when leaves peripheral
This patch clear host_request_flag when leaves peripheral state, instead of
entering host state, this can make sure this flag can be cleared after try
to do role switch, no matter the role switch succeeds or not.
Acked-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Li Jun <b47624@freescale.com>
Dong Aisheng [Fri, 14 Nov 2014 02:27:06 +0000 (10:27 +0800)]
MLK-9834 mmc: sdhci-esdhc-imx: fix SD3.0 failed to resume if M/F is enabled
Due to the power lost in suspend if Mega/Fast is enabled which is a new
feature introduced, the static settings like tuning control in probe()
function of controller will be lost which results in the later resume
failed on tuning routine for SD3.0 cards(SDR50/SDR104).
This patch moves the tunning setting from probe() function into
register setting path before the tuning is executed.
Then the tuning setting becomes dynamically and re-set again after
resume for a SD3.0 card when doing tuning.
Dong Aisheng [Wed, 6 Aug 2014 05:04:09 +0000 (13:04 +0800)]
ENGR00324668 mmc: core: add delay for SD3.0 UHS mode switch
We may meet the following errors with a SD3.0 DDR50 cards during reboot test.
mmc0: new ultra high speed DDR50 SDHC card at address aaaa
mmcblk0: mmc0:aaaa SU08G 7.40 GiB
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0xb00
mmcblk0: retrying using single block read
mmcblk0: error -84 transferring data, sector 0, nr 8, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 0
.....
Buffer I/O error on device mmcblk0, logical block 0
mmcblk0: unable to read partition table
The root cause is still unknown.
Since there's an errata of Sandisk eMMC card before that it requires delay for CMD6
for eMMC DDR mode to work stable, we also suspect the SD3.0 DDR requires similar delay.
(Still not confirmed by Sandisk)
By adding the delay, the overnight reboot test(run 2000+ times) did not
show the issue anymore. Originally it can easy show the error after about 20 times of
reboot test.
So this patch would be the temporary workaround for Sandisk SD3.0 DDR50 mode
unstable issue.
Dong Aisheng [Mon, 17 Nov 2014 08:51:10 +0000 (16:51 +0800)]
MLK-9428 dts: imx6sx: optimize can pad settings
Detailed reproduce steps:
1. boot-up to Linux command prompt.
2. send data from CAN device using "candump" command.
3. capture the TXD waveform during transmission.
4. severe overshoot/undershoot is observed (+4.4V ~ -1.2V).
HW team found that the pad setting of the CAN signal pins is not optimized.
In existing BSP, SPEED/DSE/SRE = 10/110/1 is used. They propose change it
to SPEED/DSE/SRE = 00/100/0.
Dong Aisheng [Tue, 18 Nov 2014 08:03:55 +0000 (16:03 +0800)]
MLK-9501 dts: imx6sx-sdb: optimize usdhc3 pad settings
Detailed reproduce steps:
1. boot-up to Linux command prompt .
2. Plug SD3.0 UHS-I SD Card into SD3 Connector (make sure SD Card running
at SD3.0 DDR50/1.8V).
2. write data to SD3 using "dd" command (SD3_CLK running at 1.8V/50MHz).
3. capture the SD3_CLK, SD3_DATA, SD3_CMD waveforms during data write using
FET probe (>=1GHz)
4. CLK waveforms like triangular wave are observed.
HW team found that the pad setting of the SD3_CLK, SD3_DATA, SD3_CMD signal pins are
not optimized. In existing BSP, when running at SD3.0/DDR50/1.8V, SPEED/DSE/SRE
= 01/011/1 is used. They propose change it to -
SD3_CLK: SPEED/DSE/SRE = 01/110/1.
SD3_DATA/SD3_CMD: SPEED/DSE/SRE = 01/101/1.
SDHC high speed cards also had such issue(refer to MLK-9500).
We only changed the default state (<50Mhz) pad setting, for ultra high speed
state like 100Mhz and 200Mhz, it does not have such issue since they already
set to the maximum Drive Strength value.
Dong Aisheng [Tue, 18 Nov 2014 08:32:03 +0000 (16:32 +0800)]
MLK-9871 dts: imx6sx: remove canfd related stuff
The CANFD IP will be removed in final production, so remove
the CANFD related stuff in dts tree to avoid confusion.
The patch only removed user level in dts part, the exists related
clocks and pads in source code are still there which seems not matter.
Dong Aisheng [Tue, 9 Dec 2014 08:43:37 +0000 (16:43 +0800)]
MLK-9975-2 imx6sx-ard: fix CAN unwork if power up the borad on first time
The CAN transceiver on MX6SX Sabreauto board seems in sleep mode
by default after power up the board. User has to press the wakeup
key on ARD baseboard before using the transceiver, or it may not
work properly when power up the board at the first time(warm reset
does not have such issue).
This patch wakeup the transceiver firstly if needed during intialization
by control the wakeup pin, then user do not have to press wakeup key
button to enable the transceiver.
BTW, stby gpio is also updated which is wrong before.
ENGR00333130-2 dts: imx6sx: add legacy imx6sx sdb revA support
The CAN transceiver is changed on RevB board and the default imx6sx-sdb.dts
is for support new RevB board.
This patch adds the dts for legacy RevA board support, especially for CAN
device.
This is for people who still wants to use RevA board with this code base.
The host->vmmc will be in disabled state if there's no card detected.
In that case arbitrarily disabling the host->vmmc in sdhci_remove_host()
may cause the following warning due to unblanced use count of regulator.
root@imx6qdlsolo:~# modprobe -r sdhci-esdhc-imx
mmc3: card e624 removed
------------[ cut here ]------------
WARNING: at drivers/regulator/core.c:1727 _regulator_disable+0xe4/0x14c()
unbalanced disables for VCC_SD3
Modules linked in: sdhci_esdhc_imx(-) sdhci_pltfm
CPU: 0 PID: 884 Comm: modprobe Not tainted 3.10.53-02577-gd22d937 #715
[<80013b00>] (unwind_backtrace+0x0/0xf4) from [<80011524>] (show_stack+0x10/0x14)
[<80011524>] (show_stack+0x10/0x14) from [<8002c290>] (warn_slowpath_common+0x54/0x6c)
[<8002c290>] (warn_slowpath_common+0x54/0x6c) from [<8002c2d8>] (warn_slowpath_fmt+0x30/0x40)
[<8002c2d8>] (warn_slowpath_fmt+0x30/0x40) from [<802cc054>] (_regulator_disable+0xe4/0x14c)
[<802cc054>] (_regulator_disable+0xe4/0x14c) from [<802cc0ec>] (regulator_disable+0x30/0x64)
[<802cc0ec>] (regulator_disable+0x30/0x64) from [<80468dfc>] (sdhci_remove_host+0x78/0x160)
[<80468dfc>] (sdhci_remove_host+0x78/0x160) from [<7f005934>] (sdhci_esdhc_imx_remove+0x30/0x58 [sdhci_esdhc_imx])
[<7f005934>] (sdhci_esdhc_imx_remove+0x30/0x58 [sdhci_esdhc_imx]) from [<80313038>] (platform_drv_remove+0x18/0x1c)
[<80313038>] (platform_drv_remove+0x18/0x1c) from [<803119d8>] (__device_release_driver+0x70/0xcc)
[<803119d8>] (__device_release_driver+0x70/0xcc) from [<803120cc>] (driver_detach+0xac/0xb0)
[<803120cc>] (driver_detach+0xac/0xb0) from [<803116c4>] (bus_remove_driver+0x7c/0xd0)
[<803116c4>] (bus_remove_driver+0x7c/0xd0) from [<8006fc80>] (SyS_delete_module+0x124/0x210)
[<8006fc80>] (SyS_delete_module+0x124/0x210) from [<8000e080>] (ret_fast_syscall+0x0/0x30)
---[ end trace 7bd0fb3a78254b54 ]---
root@imx6qdlsolo:~# EXT3-fs (mmcblk3p2): I/O error while writing superblock
Only disable regulators if they're on when remove host controller.
Fugang Duan [Mon, 19 Jan 2015 09:16:35 +0000 (17:16 +0800)]
MLK-10116 tty: serial: imx: fix flush buffer issue when module clock is at 4Mhz
In general, uart module clock require it is great than 80Mhz to match 5Mbps
baud rate. When test below 14Mhz module clock, software reset cause state
machines off normal. And for i.MX6SL evk board low power test, it set uart
module clock to 4Mhz, which cause console port print out messy code.
The patch just is workaround to fix console issue.
Sandor Yu [Mon, 19 Jan 2015 06:36:59 +0000 (14:36 +0800)]
MLK-10115: ov5640:define function ov5640_turn_on_AE_AG() with static
ov5640 driver will failed to build with build-in:
drivers/media/platform/mxc/subdev/built-in.o: In function
`ov5640_turn_on_AE_AG':
ov5640.c:(.text+0x3890): multiple definition of `ov5640_turn_on_AE_AG'
drivers/media/platform/mxc/capture/built-in.o:v4l2-int-device.c:(.text+0x783c):
first defined here
make[3]: *** [drivers/media/platform/built-in.o] Error 1
make[2]: *** [drivers/media/platform] Error 2
make[1]: *** [drivers/media] Error 2
make: *** [drivers] Error 2
make: *** Waiting for unfinished jobs....
It is caused by function of ov5640_turn_on_AE_AG define as global function,
change it to static function to resolv the issue.
Richard Zhu [Thu, 25 Dec 2014 06:36:44 +0000 (14:36 +0800)]
MLK-10058-4 pci: imx6: refine imx6sx pcie pm
- Regarding to the pcie design on imx6sx, some gpc
operations are mandatory pre-required when pcie phy
is powered on/off.
In order to DO NOT touch gpc module in pcie driver,
register one pcie phy regulator into gpc, encapsulate
the pcie phy power on/off pre gpc related operations into
regulator's notify and contained in gpc driver
- in order to save power consumption, disable pcie clks and phy
regulator if the pcie link is down.
- remove the PRST set/unset in suspend/resume, because that
usb hub would be reset, and the name of the dev node of the
thumb disk inserted in the port of the pcie2usb device,
would be changed randomly after suspend resume on imx6sx.
- add the extremely power save mode
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
Richard Zhu [Thu, 25 Dec 2014 06:30:38 +0000 (14:30 +0800)]
MLK-10058-3 arm: gpc: add pcie phy power gpc operations
For PCIe module on i.mx6sx, some GPC operations would
be mandatory required when PCIe PHY is powered on/off.
So we need update gpc driver for the new requirements.
We implement it by regulator notify framwork in gpc driver.
NOTE:
make sure gpc driver is ready before PCIe driver is probed.
Otherwise, cause system hang during PCIe driver probe,
because the notify NOT installed ready and the gpc will
NOT power on PCIe.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
Some gpc operations are mandatory required when
iMX6SX PCIe PHY is powered on/off.
use the notify framwork to encapsulate the
pre-operations in gpc driver
- add two pre-xxx macros into consumer.h
- kick off the pre-xxx events in enable/disalbe call back.
Signed-off-by: Richard Zhu <Richard.Zhu@freescale.com>
Xiubo Li [Fri, 29 Aug 2014 07:12:12 +0000 (15:12 +0800)]
ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'.
The 'big-endian-data' property is originally used to indicate whether the
LSB firstly or MSB firstly will be transmitted to the CODEC or received
from the CODEC, and there has nothing relation to the memory data.
Generally, if the audio data in big endian format, which will be using the
bytes reversion, Here this can only be used to bits reversion.
So using the 'lsb-first' instead of 'big-endian-data' can make the code
to be readable easier and more easy to understand what this property is
used to do.
This property used for configuring whether the LSB or the MSB is transmitted
first for the fifo data.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
(cherry picked from commit eadb0019d206591e34e864b62059b292e157d8fc)
Xiubo Li [Mon, 25 Aug 2014 03:31:02 +0000 (11:31 +0800)]
ASoC: fsl-sai: Convert to use regmap framework's endianness method.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 014fd22ef9c6a7e9536b7e16635714a1a34810a8)
Peter Chen [Tue, 30 Sep 2014 01:10:59 +0000 (09:10 +0800)]
MLK-10107-3 ARM: imx_v7_defconfig: enable more USB functions
USB Ethernet function at host mode
USB Media function(webcam) at host mode
USB Audio function at host mode
USB Serial function at host mode
USB EHSET driver at host mode (for OTG & EH Certification test)
Several USB Gadget functions:
- Configfs
- NCM
- Zero (used for test)
- Gadgetfs
- Serial
Above functions are built as module.
Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Peter Chen <peter.chen@freescale.com>
For chipidea, its resume sequence is not-EHCI compatible, see
below description for FPR at portsc. So in order to send SoF in
time for remote wakeup sequence(within 3ms), the RUN/STOP bit must
be set before the resume signal is ended, but the usb resume
code may run after resume signal is ended, so we had to set it
at suspend path.
Force Port Resume - RW. Default = 0b.
1= Resume detected/driven on port.
0=No resume (K-state) detected/driven on port.
Host mode:
Software sets this bit to one to drive resume signaling. The Controller sets this bit to '1' if
a J-to-K transition is detected while the port is in the Suspend state. When this bit
transitions to a '1' because a J-to-K transition is detected, the Port Change Detect bit in
the USBSTS register is also set to '1'. This bit will automatically change to '0' after the
resume sequence is complete. This behavior is different from EHCI where the controller
driver is required to set this bit to a '0' after the resume duration is timed in the driver.
Note that when the controller owns the port, the resume sequence follows the defined
sequence documented in the USB Specification Revision 2.0. The resume signaling
(Full-speed 'K') is driven on the port as long as this bit remains a '1'. This bit will remain
a '1' until the port has switched to idle. Writing a '0' has no affect because the port
controller will time the resume operation, clear the bit and the port control state switches
to HS or FS idle.
This field is '0' if Port Power(PP) is '0' in host mode.
This bit is not-EHCI compatible.
Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Peter Chen <peter.chen@freescale.com>
Peter Chen [Thu, 12 Dec 2013 06:33:02 +0000 (14:33 +0800)]
ENGR00291876 usb: phy-mxs: add delay before set phyctrl.clkgate
There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phypwd, otherwise, the wakeup
signal may can't wake up controller.