Because of a sanity check in virtio_dev_remove, a buggy device can crash
kernel. And in case of rproc it's userspace so it's not a good idea.
We are unloading a driver so how bad can it be?
Be less aggressive in handling this error: if it's a driver bug,
warning once should be enough.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
virtio: console: fix error handling in init() function
If register_virtio_driver() fails, virtio-ports class is not destroyed.
The patch adds error handling of register_virtio_driver().
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Acked-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Rusty Russell [Thu, 13 Sep 2012 01:03:44 +0000 (11:03 +1000)]
virtio: add help to CONFIG_VIRTIO option.
Trying to enable a virtio driver (eg CONFIG_VIRTIO_BLK) is painful
because it depends on CONFIG_VIRTIO. CONFIG_VIRTIO doesn't tell you
how to turn it on (it's selected from anything which provides a virtio
bus).
This patch at least adds some documentation, visible in menuconfig, as
a hint.
Reported-by: Kent Overstreet <koverstreet@google.com> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
We unified the Freescale pci/pcie initialization by changing the fsl_pci
to a platform driver. In previous PCI code architecture the initialization
routine is called at board_setup_arch stage. Now the initialization is done
in probe function which is architectural better. Also It's convenient for
adding PM support for PCI controller in later patch.
Now we registered pci controllers as platform devices. So we combine two
initialization code as one platform driver.
Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Roy Zang [Mon, 3 Sep 2012 09:22:10 +0000 (17:22 +0800)]
powerpc/pci: Use PCIe IP block revision register instead of compatible
Freescale PCIe IP block revision bigger than rev2.2 will also need
redefine the sequence of inbound windows. So change to use IP block
revision instead of compatible for the judgment.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
powerpc/mpc85xx: Add new ext fields to Integrated FLash Controller
Freescale's Integrated Flash controller(IFC) v1.1.0 supports 40 bit
address bus width.
In case more than 32 bit address is used, the EXT registers should be set.
Add support of ext registers.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Olivia Yin [Thu, 9 Aug 2012 07:42:36 +0000 (15:42 +0800)]
powerpc/e5500: Add Power ISA properties to comply with ePAPR 1.1
power-isa-version and power-isa-* are cpu node general properties defined
in ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of a property named power-isa-[CAT], where [CAT] is the
abbreviated category name with all uppercase letters converted to
lowercase, indicates that the category is supported by the implementation.
This patch update all the e5500 platforms.
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Olivia Yin [Thu, 9 Aug 2012 07:42:35 +0000 (15:42 +0800)]
powerpc/e500mc: Add Power ISA properties to comply with ePAPR 1.1
power-isa-version and power-isa-* are cpu node general properties defined
in ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of a property named power-isa-[CAT], where [CAT] is the
abbreviated category name with all uppercase letters converted to
lowercase, indicates that the category is supported by the implementation.
The patch update all the e500mc platforms.
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Olivia Yin [Thu, 9 Aug 2012 07:42:34 +0000 (15:42 +0800)]
powerpc/e500v2: Add Power ISA properties to comply with ePAPR 1.1
power-isa-version and power-isa-* are cpu node general properties defined
in ePAPR.
If the power-isa-version property exists, then for each category from the
Categories section of Book I of the Power ISA version indicated, the
existence of a property named power-isa-[CAT], where [CAT] is the
abbreviated category name with all uppercase letters converted to
lowercase, indicates that the category is supported by the implementation.
The patch update all e500v2 platforms.
Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Varun Sethi [Wed, 8 Aug 2012 04:06:09 +0000 (09:36 +0530)]
powerpc/mpic: FSL MPIC error interrupt support.
All SOC device error interrupts are muxed and delivered to the core
as a single MPIC error interrupt. Currently all the device drivers
requiring access to device errors have to register for the MPIC error
interrupt as a shared interrupt.
With this patch we add interrupt demuxing capability in the mpic driver,
allowing device drivers to register for their individual error interrupts.
This is achieved by handling error interrupts in a cascaded fashion.
MPIC error interrupt is handled by the "error_int_handler", which
subsequently demuxes it using the EISR and delivers it to the respective
drivers.
The error interrupt capability is dependent on the MPIC EIMR register,
which was introduced in FSL MPIC version 4.1 (P4080 rev2). So, error
interrupt demuxing capability is dependent on the MPIC version and can
be used for versions >= 4.1.
Jia Hongtao [Fri, 3 Aug 2012 10:14:10 +0000 (18:14 +0800)]
powerpc/swiotlb: Enable at early stage and disable if not necessary
Remove the dependency on PCI initialization for SWIOTLB initialization.
So that PCI can be initialized at proper time.
SWIOTLB is partly determined by PCI inbound/outbound map which is assigned
in PCI initialization. But swiotlb_init() should be done at the stage of
mem_init() which is much earlier than PCI initialization. So we reserve the
memory for SWIOTLB first and free it if not necessary.
All boards are converted to fit this change.
Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Acked-by: Tony Breeds <tony@bakeyournoodle.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
projects / karo-tx-linux.git / log