From 642bc4e7505e3c89a285fa452496356d356d9d76 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Thu, 14 Jun 2012 09:56:58 +0200 Subject: [PATCH] =?utf8?q?Combine=20consecutive=20inline=20asm=20instructi?= =?utf8?q?ons=20into=20one=20statement=20to=20prevent=20them=20from=20bein?= =?utf8?q?g=20reordered.=20The=20GCC=20manual=20states:=20|=20Similarly,?= =?utf8?q?=20you=20can't=20expect=20a=20sequence=20of=20volatile=20asm=20i?= =?utf8?q?nstructions=20|=20to=20remain=20perfectly=20consecutive.=20If=20?= =?utf8?q?you=20want=20consecutive=20output,=20use=20a=20|=20single=20asm.?= =?utf8?q?=20Also,=20GCC=20will=20perform=20some=20optimizations=20across?= =?utf8?q?=20a=20|=20volatile=20asm=20instruction;=20GCC=20does=20not=20?= =?utf8?q?=E2=80=9Cforget=20everything=E2=80=9D=20when=20it=20|=20encounte?= =?utf8?q?rs=20a=20volatile=20asm=20instruction=20the=20way=20some=20other?= =?utf8?q?=20compilers=20do.?= MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit --- arch/arm/cpu/armv7/cache_v7.c | 41 ++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 1b4e808a79..0923a6f09d 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -236,16 +236,18 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) /* Invalidate TLB */ static void v7_inval_tlb(void) { - /* Invalidate entire unified TLB */ - asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); - /* Invalidate entire data TLB */ - asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); - /* Invalidate entire instruction TLB */ - asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); - /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; - /* Full system ISB - make sure the instruction stream sees it */ - CP15ISB; + asm volatile ( + /* Invalidate entire unified TLB */ + "mcr p15, 0, %0, c8, c7, 0\n" + /* Invalidate entire data TLB */ + "mcr p15, 0, %0, c8, c6, 0\n" + /* Invalidate entire instruction TLB */ + "mcr p15, 0, %0, c8, c5, 0\n" + /* Full system DSB - make sure that the invalidation is complete */ + "mcr p15, 0, %0, c7, c10, 4\n" + /* Full system ISB - make sure the instruction stream sees it */ + "mcr p15, 0, %0, c7, c5, 4\n" + : : "r" (0)); } void invalidate_dcache_all(void) @@ -339,16 +341,15 @@ void invalidate_icache_all(void) * Invalidate all instruction caches to PoU. * Also flushes branch target cache. */ - asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); - - /* Invalidate entire branch predictor array */ - asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); - - /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; - - /* ISB - make sure the instruction stream sees it */ - CP15ISB; + asm volatile ( + "mcr p15, 0, %0, c7, c5, 0\n" + /* Invalidate entire branch predictor array */ + "mcr p15, 0, %0, c7, c5, 6\n" + /* Full system DSB - make sure that the invalidation is complete */ + "mcr p15, 0, %0, c7, c10, 4\n" + /* ISB - make sure the instruction stream sees it */ + "mcr p15, 0, %0, c7, c5, 4\n" + : : "r" (0)); } #else void invalidate_icache_all(void) -- 2.39.5