From db5fa76e6d7bb659d421e39af2b22a65a766a3a2 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Thu, 28 Aug 2014 13:38:15 +0800 Subject: [PATCH] ENGR00329096 clk: Add dcic clock define for imx6q Add dcic1 and dcic define in imx6q clock tree. Signed-off-by: Sandor Yu --- arch/arm/mach-imx/clk-imx6q.c | 2 ++ include/dt-bindings/clock/imx6qdl-clock.h | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 560592cd5019..dc953bbdb07c 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -321,6 +321,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); + clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24); + clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26); clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index a0ff66a04a2b..fc24b8c9012b 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -222,6 +222,8 @@ #define IMX6QDL_CLK_LDB_DI0_DIV_SEL 211 #define IMX6QDL_CLK_LDB_DI1_DIV_SEL 212 #define IMX6QDL_CLK_VIDEO_27M 213 -#define IMX6QDL_CLK_END 214 +#define IMX6QDL_CLK_DCIC1 214 +#define IMX6QDL_CLK_DCIC2 215 +#define IMX6QDL_CLK_END 216 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ -- 2.39.5