Documentation/devicetree/bindings/edac/apm-xgene-edac.txt

   1 * APM X-Gene SoC EDAC node
   2
   3 EDAC node is defined to describe on-chip error detection and correction.
   4 The follow error types are supported:
   5
   6   memory controller     - Memory controller
   7   PMD (L1/L2)           - Processor module unit (PMD) L1/L2 cache
   8
   9 The following section describes the EDAC DT node binding.
  10
  11 Required properties:
  12 - compatible            : Shall be "apm,xgene-edac".
  13 - regmap-csw            : Regmap of the CPU switch fabric (CSW) resource.
  14 - regmap-mcba           : Regmap of the MCB-A (memory bridge) resource.
  15 - regmap-mcbb           : Regmap of the MCB-B (memory bridge) resource.
  16 - regmap-efuse          : Regmap of the PMD efuse resource.
  17 - reg                   : First resource shall be the CPU bus (PCP) resource.
  18 - interrupts            : Interrupt-specifier for MCU, PMD, L3, or SoC error
  19                           IRQ(s).
  20
  21 Required properties for memory controller subnode:
  22 - compatible            : Shall be "apm,xgene-edac-mc".
  23 - reg                   : First resource shall be the memory controller unit
  24                           (MCU) resource.
  25 - memory-controller     : Instance number of the memory controller.
  26
  27 Required properties for PMD subnode:
  28 - compatible            : Shall be "apm,xgene-edac-pmd" or
  29                           "apm,xgene-edac-pmd-v2".
  30 - reg                   : First resource shall be the PMD resource.
  31 - pmd-controller        : Instance number of the PMD controller.
  32
  33 Example:
  34         csw: csw@7e200000 {
  35                 compatible = "apm,xgene-csw", "syscon";
  36                 reg = <0x0 0x7e200000 0x0 0x1000>;
  37         };
  38
  39         mcba: mcba@7e700000 {
  40                 compatible = "apm,xgene-mcb", "syscon";
  41                 reg = <0x0 0x7e700000 0x0 0x1000>;
  42         };
  43
  44         mcbb: mcbb@7e720000 {
  45                 compatible = "apm,xgene-mcb", "syscon";
  46                 reg = <0x0 0x7e720000 0x0 0x1000>;
  47         };
  48
  49         efuse: efuse@1054a000 {
  50                 compatible = "apm,xgene-efuse", "syscon";
  51                 reg = <0x0 0x1054a000 0x0 0x20>;
  52         };
  53
  54         edac@78800000 {
  55                 compatible = "apm,xgene-edac";
  56                 #address-cells = <2>;
  57                 #size-cells = <2>;
  58                 ranges;
  59                 regmap-csw = <&csw>;
  60                 regmap-mcba = <&mcba>;
  61                 regmap-mcbb = <&mcbb>;
  62                 regmap-efuse = <&efuse>;
  63                 reg = <0x0 0x78800000 0x0 0x100>;
  64                 interrupts = <0x0 0x20 0x4>,
  65                              <0x0 0x21 0x4>,
  66                              <0x0 0x27 0x4>;
  67
  68                 edacmc@7e800000 {
  69                         compatible = "apm,xgene-edac-mc";
  70                         reg = <0x0 0x7e800000 0x0 0x1000>;
  71                         memory-controller = <0>;
  72                 };
  73
  74                 edacpmd@7c000000 {
  75                         compatible = "apm,xgene-edac-pmd";
  76                         reg = <0x0 0x7c000000 0x0 0x200000>;
  77                         pmd-controller = <0>;
  78                 };
  79         };