1 ============================
2 LINUX KERNEL MEMORY BARRIERS
3 ============================
5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
10 (*) Abstract memory access model.
15 (*) What are memory barriers?
17 - Varieties of memory barrier.
18 - What may not be assumed about memory barriers?
19 - Data dependency barriers.
20 - Control dependencies.
21 - SMP barrier pairing.
22 - Examples of memory barrier sequences.
23 - Read memory barriers vs load speculation.
26 (*) Explicit kernel barriers.
29 - CPU memory barriers.
32 (*) Implicit kernel memory barriers.
35 - Interrupt disabling functions.
36 - Sleep and wake-up functions.
37 - Miscellaneous functions.
39 (*) Inter-CPU locking barrier effects.
41 - Locks vs memory accesses.
42 - Locks vs I/O accesses.
44 (*) Where are memory barriers needed?
46 - Interprocessor interaction.
51 (*) Kernel I/O barrier effects.
53 (*) Assumed minimum execution ordering model.
55 (*) The effects of the cpu cache.
58 - Cache coherency vs DMA.
59 - Cache coherency vs MMIO.
61 (*) The things CPUs get up to.
63 - And then there's the Alpha.
72 ============================
73 ABSTRACT MEMORY ACCESS MODEL
74 ============================
76 Consider the following abstract model of the system:
81 +-------+ : +--------+ : +-------+
84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
87 +-------+ : +--------+ : +-------+
95 +---------->| Device |<----------+
101 Each CPU executes a program that generates memory access operations. In the
102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
103 perform the memory operations in any order it likes, provided program causality
104 appears to be maintained. Similarly, the compiler may also arrange the
105 instructions it emits in any order it likes, provided it doesn't affect the
106 apparent operation of the program.
108 So in the above diagram, the effects of the memory operations performed by a
109 CPU are perceived by the rest of the system as the operations cross the
110 interface between the CPU and rest of the system (the dotted lines).
113 For example, consider the following sequence of events:
116 =============== ===============
121 The set of accesses as seen by the memory system in the middle can be arranged
122 in 24 different combinations:
124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
134 and can thus result in four different combinations of values:
142 Furthermore, the stores committed by a CPU to the memory system may not be
143 perceived by the loads made by another CPU in the same order as the stores were
147 As a further example, consider this sequence of events:
150 =============== ===============
151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
155 There is an obvious data dependency here, as the value loaded into D depends on
156 the address retrieved from P by CPU 2. At the end of the sequence, any of the
157 following results are possible:
159 (Q == &A) and (D == 1)
160 (Q == &B) and (D == 2)
161 (Q == &B) and (D == 4)
163 Note that CPU 2 will never try and load C into D because the CPU will load P
164 into Q before issuing the load of *Q.
170 Some devices present their control interfaces as collections of memory
171 locations, but the order in which the control registers are accessed is very
172 important. For instance, imagine an ethernet card with a set of internal
173 registers that are accessed through an address port register (A) and a data
174 port register (D). To read internal register 5, the following code might then
180 but this might show up as either of the following two sequences:
182 STORE *A = 5, x = LOAD *D
183 x = LOAD *D, STORE *A = 5
185 the second of which will almost certainly result in a malfunction, since it set
186 the address _after_ attempting to read the register.
192 There are some minimal guarantees that may be expected of a CPU:
194 (*) On any given CPU, dependent memory accesses will be issued in order, with
195 respect to itself. This means that for:
197 WRITE_ONCE(Q, P); smp_read_barrier_depends(); D = READ_ONCE(*Q);
199 the CPU will issue the following memory operations:
201 Q = LOAD P, D = LOAD *Q
203 and always in that order. On most systems, smp_read_barrier_depends()
204 does nothing, but it is required for DEC Alpha. The READ_ONCE()
205 and WRITE_ONCE() are required to prevent compiler mischief. Please
206 note that you should normally use something like rcu_dereference()
207 instead of open-coding smp_read_barrier_depends().
209 (*) Overlapping loads and stores within a particular CPU will appear to be
210 ordered within that CPU. This means that for:
212 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
214 the CPU will only issue the following sequence of memory operations:
216 a = LOAD *X, STORE *X = b
220 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
222 the CPU will only issue:
224 STORE *X = c, d = LOAD *X
226 (Loads and stores overlap if they are targeted at overlapping pieces of
229 And there are a number of things that _must_ or _must_not_ be assumed:
231 (*) It _must_not_ be assumed that the compiler will do what you want
232 with memory references that are not protected by READ_ONCE() and
233 WRITE_ONCE(). Without them, the compiler is within its rights to
234 do all sorts of "creative" transformations, which are covered in
235 the Compiler Barrier section.
237 (*) It _must_not_ be assumed that independent loads and stores will be issued
238 in the order given. This means that for:
240 X = *A; Y = *B; *D = Z;
242 we may get any of the following sequences:
244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
252 discarded. This means that for:
254 X = *A; Y = *(A + 4);
256 we may get any one of the following sequences:
258 X = LOAD *A; Y = LOAD *(A + 4);
259 Y = LOAD *(A + 4); X = LOAD *A;
260 {X, Y} = LOAD {*A, *(A + 4) };
264 *A = X; *(A + 4) = Y;
268 STORE *A = X; STORE *(A + 4) = Y;
269 STORE *(A + 4) = Y; STORE *A = X;
270 STORE {*A, *(A + 4) } = {X, Y};
272 And there are anti-guarantees:
274 (*) These guarantees do not apply to bitfields, because compilers often
275 generate code to modify these using non-atomic read-modify-write
276 sequences. Do not attempt to use bitfields to synchronize parallel
279 (*) Even in cases where bitfields are protected by locks, all fields
280 in a given bitfield must be protected by one lock. If two fields
281 in a given bitfield are protected by different locks, the compiler's
282 non-atomic read-modify-write sequences can cause an update to one
283 field to corrupt the value of an adjacent field.
285 (*) These guarantees apply only to properly aligned and sized scalar
286 variables. "Properly sized" currently means variables that are
287 the same size as "char", "short", "int" and "long". "Properly
288 aligned" means the natural alignment, thus no constraints for
289 "char", two-byte alignment for "short", four-byte alignment for
290 "int", and either four-byte or eight-byte alignment for "long",
291 on 32-bit and 64-bit systems, respectively. Note that these
292 guarantees were introduced into the C11 standard, so beware when
293 using older pre-C11 compilers (for example, gcc 4.6). The portion
294 of the standard containing this guarantee is Section 3.14, which
295 defines "memory location" as follows:
298 either an object of scalar type, or a maximal sequence
299 of adjacent bit-fields all having nonzero width
301 NOTE 1: Two threads of execution can update and access
302 separate memory locations without interfering with
305 NOTE 2: A bit-field and an adjacent non-bit-field member
306 are in separate memory locations. The same applies
307 to two bit-fields, if one is declared inside a nested
308 structure declaration and the other is not, or if the two
309 are separated by a zero-length bit-field declaration,
310 or if they are separated by a non-bit-field member
311 declaration. It is not safe to concurrently update two
312 bit-fields in the same structure if all members declared
313 between them are also bit-fields, no matter what the
314 sizes of those intervening bit-fields happen to be.
317 =========================
318 WHAT ARE MEMORY BARRIERS?
319 =========================
321 As can be seen above, independent memory operations are effectively performed
322 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
323 What is required is some way of intervening to instruct the compiler and the
324 CPU to restrict the order.
326 Memory barriers are such interventions. They impose a perceived partial
327 ordering over the memory operations on either side of the barrier.
329 Such enforcement is important because the CPUs and other devices in a system
330 can use a variety of tricks to improve performance, including reordering,
331 deferral and combination of memory operations; speculative loads; speculative
332 branch prediction and various types of caching. Memory barriers are used to
333 override or suppress these tricks, allowing the code to sanely control the
334 interaction of multiple CPUs and/or devices.
337 VARIETIES OF MEMORY BARRIER
338 ---------------------------
340 Memory barriers come in four basic varieties:
342 (1) Write (or store) memory barriers.
344 A write memory barrier gives a guarantee that all the STORE operations
345 specified before the barrier will appear to happen before all the STORE
346 operations specified after the barrier with respect to the other
347 components of the system.
349 A write barrier is a partial ordering on stores only; it is not required
350 to have any effect on loads.
352 A CPU can be viewed as committing a sequence of store operations to the
353 memory system as time progresses. All stores before a write barrier will
354 occur in the sequence _before_ all the stores after the write barrier.
356 [!] Note that write barriers should normally be paired with read or data
357 dependency barriers; see the "SMP barrier pairing" subsection.
360 (2) Data dependency barriers.
362 A data dependency barrier is a weaker form of read barrier. In the case
363 where two loads are performed such that the second depends on the result
364 of the first (eg: the first load retrieves the address to which the second
365 load will be directed), a data dependency barrier would be required to
366 make sure that the target of the second load is updated before the address
367 obtained by the first load is accessed.
369 A data dependency barrier is a partial ordering on interdependent loads
370 only; it is not required to have any effect on stores, independent loads
371 or overlapping loads.
373 As mentioned in (1), the other CPUs in the system can be viewed as
374 committing sequences of stores to the memory system that the CPU being
375 considered can then perceive. A data dependency barrier issued by the CPU
376 under consideration guarantees that for any load preceding it, if that
377 load touches one of a sequence of stores from another CPU, then by the
378 time the barrier completes, the effects of all the stores prior to that
379 touched by the load will be perceptible to any loads issued after the data
382 See the "Examples of memory barrier sequences" subsection for diagrams
383 showing the ordering constraints.
385 [!] Note that the first load really has to have a _data_ dependency and
386 not a control dependency. If the address for the second load is dependent
387 on the first load, but the dependency is through a conditional rather than
388 actually loading the address itself, then it's a _control_ dependency and
389 a full read barrier or better is required. See the "Control dependencies"
390 subsection for more information.
392 [!] Note that data dependency barriers should normally be paired with
393 write barriers; see the "SMP barrier pairing" subsection.
396 (3) Read (or load) memory barriers.
398 A read barrier is a data dependency barrier plus a guarantee that all the
399 LOAD operations specified before the barrier will appear to happen before
400 all the LOAD operations specified after the barrier with respect to the
401 other components of the system.
403 A read barrier is a partial ordering on loads only; it is not required to
404 have any effect on stores.
406 Read memory barriers imply data dependency barriers, and so can substitute
409 [!] Note that read barriers should normally be paired with write barriers;
410 see the "SMP barrier pairing" subsection.
413 (4) General memory barriers.
415 A general memory barrier gives a guarantee that all the LOAD and STORE
416 operations specified before the barrier will appear to happen before all
417 the LOAD and STORE operations specified after the barrier with respect to
418 the other components of the system.
420 A general memory barrier is a partial ordering over both loads and stores.
422 General memory barriers imply both read and write memory barriers, and so
423 can substitute for either.
426 And a couple of implicit varieties:
428 (5) ACQUIRE operations.
430 This acts as a one-way permeable barrier. It guarantees that all memory
431 operations after the ACQUIRE operation will appear to happen after the
432 ACQUIRE operation with respect to the other components of the system.
433 ACQUIRE operations include LOCK operations and smp_load_acquire()
436 Memory operations that occur before an ACQUIRE operation may appear to
437 happen after it completes.
439 An ACQUIRE operation should almost always be paired with a RELEASE
443 (6) RELEASE operations.
445 This also acts as a one-way permeable barrier. It guarantees that all
446 memory operations before the RELEASE operation will appear to happen
447 before the RELEASE operation with respect to the other components of the
448 system. RELEASE operations include UNLOCK operations and
449 smp_store_release() operations.
451 Memory operations that occur after a RELEASE operation may appear to
452 happen before it completes.
454 The use of ACQUIRE and RELEASE operations generally precludes the need
455 for other sorts of memory barrier (but note the exceptions mentioned in
456 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
457 pair is -not- guaranteed to act as a full memory barrier. However, after
458 an ACQUIRE on a given variable, all memory accesses preceding any prior
459 RELEASE on that same variable are guaranteed to be visible. In other
460 words, within a given variable's critical section, all accesses of all
461 previous critical sections for that variable are guaranteed to have
464 This means that ACQUIRE acts as a minimal "acquire" operation and
465 RELEASE acts as a minimal "release" operation.
468 Memory barriers are only required where there's a possibility of interaction
469 between two CPUs or between a CPU and a device. If it can be guaranteed that
470 there won't be any such interaction in any particular piece of code, then
471 memory barriers are unnecessary in that piece of code.
474 Note that these are the _minimum_ guarantees. Different architectures may give
475 more substantial guarantees, but they may _not_ be relied upon outside of arch
479 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
480 ----------------------------------------------
482 There are certain things that the Linux kernel memory barriers do not guarantee:
484 (*) There is no guarantee that any of the memory accesses specified before a
485 memory barrier will be _complete_ by the completion of a memory barrier
486 instruction; the barrier can be considered to draw a line in that CPU's
487 access queue that accesses of the appropriate type may not cross.
489 (*) There is no guarantee that issuing a memory barrier on one CPU will have
490 any direct effect on another CPU or any other hardware in the system. The
491 indirect effect will be the order in which the second CPU sees the effects
492 of the first CPU's accesses occur, but see the next point:
494 (*) There is no guarantee that a CPU will see the correct order of effects
495 from a second CPU's accesses, even _if_ the second CPU uses a memory
496 barrier, unless the first CPU _also_ uses a matching memory barrier (see
497 the subsection on "SMP Barrier Pairing").
499 (*) There is no guarantee that some intervening piece of off-the-CPU
500 hardware[*] will not reorder the memory accesses. CPU cache coherency
501 mechanisms should propagate the indirect effects of a memory barrier
502 between CPUs, but might not do so in order.
504 [*] For information on bus mastering DMA and coherency please read:
506 Documentation/PCI/pci.txt
507 Documentation/DMA-API-HOWTO.txt
508 Documentation/DMA-API.txt
511 DATA DEPENDENCY BARRIERS
512 ------------------------
514 The usage requirements of data dependency barriers are a little subtle, and
515 it's not always obvious that they're needed. To illustrate, consider the
516 following sequence of events:
519 =============== ===============
520 { A == 1, B == 2, C = 3, P == &A, Q == &C }
527 There's a clear data dependency here, and it would seem that by the end of the
528 sequence, Q must be either &A or &B, and that:
530 (Q == &A) implies (D == 1)
531 (Q == &B) implies (D == 4)
533 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
534 leading to the following situation:
536 (Q == &B) and (D == 2) ????
538 Whilst this may seem like a failure of coherency or causality maintenance, it
539 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
542 To deal with this, a data dependency barrier or better must be inserted
543 between the address load and the data load:
546 =============== ===============
547 { A == 1, B == 2, C = 3, P == &A, Q == &C }
552 <data dependency barrier>
555 This enforces the occurrence of one of the two implications, and prevents the
556 third possibility from arising.
558 [!] Note that this extremely counterintuitive situation arises most easily on
559 machines with split caches, so that, for example, one cache bank processes
560 even-numbered cache lines and the other bank processes odd-numbered cache
561 lines. The pointer P might be stored in an odd-numbered cache line, and the
562 variable B might be stored in an even-numbered cache line. Then, if the
563 even-numbered bank of the reading CPU's cache is extremely busy while the
564 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
565 but the old value of the variable B (2).
568 Another example of where data dependency barriers might be required is where a
569 number is read from memory and then used to calculate the index for an array
573 =============== ===============
574 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
579 <data dependency barrier>
583 The data dependency barrier is very important to the RCU system,
584 for example. See rcu_assign_pointer() and rcu_dereference() in
585 include/linux/rcupdate.h. This permits the current target of an RCU'd
586 pointer to be replaced with a new modified target, without the replacement
587 target appearing to be incompletely initialised.
589 See also the subsection on "Cache Coherency" for a more thorough example.
595 A load-load control dependency requires a full read memory barrier, not
596 simply a data dependency barrier to make it work correctly. Consider the
597 following bit of code:
601 <data dependency barrier> /* BUG: No data dependency!!! */
605 This will not have the desired effect because there is no actual data
606 dependency, but rather a control dependency that the CPU may short-circuit
607 by attempting to predict the outcome in advance, so that other CPUs see
608 the load from b as having happened before the load from a. In such a
609 case what's actually required is:
617 However, stores are not speculated. This means that ordering -is- provided
618 for load-store control dependencies, as in the following example:
620 q = READ_ONCE_CTRL(a);
625 Control dependencies pair normally with other types of barriers. That
626 said, please note that READ_ONCE_CTRL() is not optional! Without the
627 READ_ONCE_CTRL(), the compiler might combine the load from 'a' with
628 other loads from 'a', and the store to 'b' with other stores to 'b',
629 with possible highly counterintuitive effects on ordering.
631 Worse yet, if the compiler is able to prove (say) that the value of
632 variable 'a' is always non-zero, it would be well within its rights
633 to optimize the original example by eliminating the "if" statement
637 b = p; /* BUG: Compiler and CPU can both reorder!!! */
639 Finally, the READ_ONCE_CTRL() includes an smp_read_barrier_depends()
640 that DEC Alpha needs in order to respect control depedencies. Alternatively
641 use one of atomic{,64}_read_ctrl().
643 So don't leave out the READ_ONCE_CTRL().
645 It is tempting to try to enforce ordering on identical stores on both
646 branches of the "if" statement as follows:
648 q = READ_ONCE_CTRL(a);
659 Unfortunately, current compilers will transform this as follows at high
662 q = READ_ONCE_CTRL(a);
664 WRITE_ONCE(b, p); /* BUG: No ordering vs. load from a!!! */
666 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
669 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
673 Now there is no conditional between the load from 'a' and the store to
674 'b', which means that the CPU is within its rights to reorder them:
675 The conditional is absolutely required, and must be present in the
676 assembly code even after all compiler optimizations have been applied.
677 Therefore, if you need ordering in this example, you need explicit
678 memory barriers, for example, smp_store_release():
682 smp_store_release(&b, p);
685 smp_store_release(&b, p);
689 In contrast, without explicit memory barriers, two-legged-if control
690 ordering is guaranteed only when the stores differ, for example:
692 q = READ_ONCE_CTRL(a);
701 The initial READ_ONCE_CTRL() is still required to prevent the compiler
702 from proving the value of 'a'.
704 In addition, you need to be careful what you do with the local variable 'q',
705 otherwise the compiler might be able to guess the value and again remove
706 the needed conditional. For example:
708 q = READ_ONCE_CTRL(a);
717 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
718 equal to zero, in which case the compiler is within its rights to
719 transform the above code into the following:
721 q = READ_ONCE_CTRL(a);
725 Given this transformation, the CPU is not required to respect the ordering
726 between the load from variable 'a' and the store to variable 'b'. It is
727 tempting to add a barrier(), but this does not help. The conditional
728 is gone, and the barrier won't bring it back. Therefore, if you are
729 relying on this ordering, you should make sure that MAX is greater than
730 one, perhaps as follows:
732 q = READ_ONCE_CTRL(a);
733 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
742 Please note once again that the stores to 'b' differ. If they were
743 identical, as noted earlier, the compiler could pull this store outside
744 of the 'if' statement.
746 You must also be careful not to rely too much on boolean short-circuit
747 evaluation. Consider this example:
749 q = READ_ONCE_CTRL(a);
753 Because the first condition cannot fault and the second condition is
754 always true, the compiler can transform this example as following,
755 defeating control dependency:
757 q = READ_ONCE_CTRL(a);
760 This example underscores the need to ensure that the compiler cannot
761 out-guess your code. More generally, although READ_ONCE() does force
762 the compiler to actually emit code for a given load, it does not force
763 the compiler to use the results.
765 Finally, control dependencies do -not- provide transitivity. This is
766 demonstrated by two related examples, with the initial values of
767 x and y both being zero:
770 ======================= =======================
771 r1 = READ_ONCE_CTRL(x); r2 = READ_ONCE_CTRL(y);
772 if (r1 > 0) if (r2 > 0)
773 WRITE_ONCE(y, 1); WRITE_ONCE(x, 1);
775 assert(!(r1 == 1 && r2 == 1));
777 The above two-CPU example will never trigger the assert(). However,
778 if control dependencies guaranteed transitivity (which they do not),
779 then adding the following CPU would guarantee a related assertion:
782 =====================
785 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
787 But because control dependencies do -not- provide transitivity, the above
788 assertion can fail after the combined three-CPU example completes. If you
789 need the three-CPU example to provide ordering, you will need smp_mb()
790 between the loads and stores in the CPU 0 and CPU 1 code fragments,
791 that is, just before or just after the "if" statements. Furthermore,
792 the original two-CPU example is very fragile and should be avoided.
794 These two examples are the LB and WWC litmus tests from this paper:
795 http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
796 site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
800 (*) Control dependencies must be headed by READ_ONCE_CTRL(),
801 atomic{,64}_read_ctrl(). Or, as a much less preferable alternative,
802 interpose smp_read_barrier_depends() between a READ_ONCE() and the
803 control-dependent write.
805 (*) Control dependencies can order prior loads against later stores.
806 However, they do -not- guarantee any other sort of ordering:
807 Not prior loads against later loads, nor prior stores against
808 later anything. If you need these other forms of ordering,
809 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
810 later loads, smp_mb().
812 (*) If both legs of the "if" statement begin with identical stores
813 to the same variable, a barrier() statement is required at the
814 beginning of each leg of the "if" statement.
816 (*) Control dependencies require at least one run-time conditional
817 between the prior load and the subsequent store, and this
818 conditional must involve the prior load. If the compiler is able
819 to optimize the conditional away, it will have also optimized
820 away the ordering. Careful use of READ_ONCE_CTRL() READ_ONCE(),
821 and WRITE_ONCE() can help to preserve the needed conditional.
823 (*) Control dependencies require that the compiler avoid reordering the
824 dependency into nonexistence. Careful use of READ_ONCE_CTRL(),
825 atomic{,64}_read_ctrl() or smp_read_barrier_depends() can help to
826 preserve your control dependency. Please see the Compiler Barrier
827 section for more information.
829 (*) Control dependencies pair normally with other types of barriers.
831 (*) Control dependencies do -not- provide transitivity. If you
832 need transitivity, use smp_mb().
838 When dealing with CPU-CPU interactions, certain types of memory barrier should
839 always be paired. A lack of appropriate pairing is almost certainly an error.
841 General barriers pair with each other, though they also pair with most
842 other types of barriers, albeit without transitivity. An acquire barrier
843 pairs with a release barrier, but both may also pair with other barriers,
844 including of course general barriers. A write barrier pairs with a data
845 dependency barrier, a control dependency, an acquire barrier, a release
846 barrier, a read barrier, or a general barrier. Similarly a read barrier,
847 control dependency, or a data dependency barrier pairs with a write
848 barrier, an acquire barrier, a release barrier, or a general barrier:
851 =============== ===============
854 WRITE_ONCE(b, 2); x = READ_ONCE(b);
861 =============== ===============================
864 WRITE_ONCE(b, &a); x = READ_ONCE(b);
865 <data dependency barrier>
871 =============== ===============================
874 WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
875 <implicit control dependency>
879 assert(r1 == 0 || r2 == 0);
881 Basically, the read barrier always has to be there, even though it can be of
884 [!] Note that the stores before the write barrier would normally be expected to
885 match the loads after the read barrier or the data dependency barrier, and vice
889 =================== ===================
890 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
891 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
892 <write barrier> \ <read barrier>
893 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
894 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
897 EXAMPLES OF MEMORY BARRIER SEQUENCES
898 ------------------------------------
900 Firstly, write barriers act as partial orderings on store operations.
901 Consider the following sequence of events:
904 =======================
912 This sequence of events is committed to the memory coherence system in an order
913 that the rest of the system might perceive as the unordered set of { STORE A,
914 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
919 | |------>| C=3 | } /\
920 | | : +------+ }----- \ -----> Events perceptible to
921 | | : | A=1 | } \/ the rest of the system
923 | CPU 1 | : | B=2 | }
925 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
926 | | +------+ } requires all stores prior to the
927 | | : | E=5 | } barrier to be committed before
928 | | : +------+ } further stores may take place
933 | Sequence in which stores are committed to the
934 | memory system by CPU 1
938 Secondly, data dependency barriers act as partial orderings on data-dependent
939 loads. Consider the following sequence of events:
942 ======================= =======================
943 { B = 7; X = 9; Y = 8; C = &Y }
948 STORE D = 4 LOAD C (gets &B)
951 Without intervention, CPU 2 may perceive the events on CPU 1 in some
952 effectively random order, despite the write barrier issued by CPU 1:
955 | | +------+ +-------+ | Sequence of update
956 | |------>| B=2 |----- --->| Y->8 | | of perception on
957 | | : +------+ \ +-------+ | CPU 2
958 | CPU 1 | : | A=1 | \ --->| C->&Y | V
959 | | +------+ | +-------+
960 | | wwwwwwwwwwwwwwww | : :
962 | | : | C=&B |--- | : : +-------+
963 | | : +------+ \ | +-------+ | |
964 | |------>| D=4 | ----------->| C->&B |------>| |
965 | | +------+ | +-------+ | |
966 +-------+ : : | : : | |
970 Apparently incorrect ---> | | B->7 |------>| |
971 perception of B (!) | +-------+ | |
974 The load of X holds ---> \ | X->9 |------>| |
975 up the maintenance \ +-------+ | |
976 of coherence of B ----->| B->2 | +-------+
981 In the above example, CPU 2 perceives that B is 7, despite the load of *C
982 (which would be B) coming after the LOAD of C.
984 If, however, a data dependency barrier were to be placed between the load of C
985 and the load of *C (ie: B) on CPU 2:
988 ======================= =======================
989 { B = 7; X = 9; Y = 8; C = &Y }
994 STORE D = 4 LOAD C (gets &B)
995 <data dependency barrier>
998 then the following will occur:
1001 | | +------+ +-------+
1002 | |------>| B=2 |----- --->| Y->8 |
1003 | | : +------+ \ +-------+
1004 | CPU 1 | : | A=1 | \ --->| C->&Y |
1005 | | +------+ | +-------+
1006 | | wwwwwwwwwwwwwwww | : :
1008 | | : | C=&B |--- | : : +-------+
1009 | | : +------+ \ | +-------+ | |
1010 | |------>| D=4 | ----------->| C->&B |------>| |
1011 | | +------+ | +-------+ | |
1012 +-------+ : : | : : | |
1016 | | X->9 |------>| |
1018 Makes sure all effects ---> \ ddddddddddddddddd | |
1019 prior to the store of C \ +-------+ | |
1020 are perceptible to ----->| B->2 |------>| |
1021 subsequent loads +-------+ | |
1025 And thirdly, a read barrier acts as a partial order on loads. Consider the
1026 following sequence of events:
1029 ======================= =======================
1037 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1038 some effectively random order, despite the write barrier issued by CPU 1:
1041 | | +------+ +-------+
1042 | |------>| A=1 |------ --->| A->0 |
1043 | | +------+ \ +-------+
1044 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1045 | | +------+ | +-------+
1046 | |------>| B=2 |--- | : :
1047 | | +------+ \ | : : +-------+
1048 +-------+ : : \ | +-------+ | |
1049 ---------->| B->2 |------>| |
1050 | +-------+ | CPU 2 |
1051 | | A->0 |------>| |
1061 If, however, a read barrier were to be placed between the load of B and the
1065 ======================= =======================
1074 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1078 | | +------+ +-------+
1079 | |------>| A=1 |------ --->| A->0 |
1080 | | +------+ \ +-------+
1081 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1082 | | +------+ | +-------+
1083 | |------>| B=2 |--- | : :
1084 | | +------+ \ | : : +-------+
1085 +-------+ : : \ | +-------+ | |
1086 ---------->| B->2 |------>| |
1087 | +-------+ | CPU 2 |
1090 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1091 barrier causes all effects \ +-------+ | |
1092 prior to the storage of B ---->| A->1 |------>| |
1093 to be perceptible to CPU 2 +-------+ | |
1097 To illustrate this more completely, consider what could happen if the code
1098 contained a load of A either side of the read barrier:
1101 ======================= =======================
1107 LOAD A [first load of A]
1109 LOAD A [second load of A]
1111 Even though the two loads of A both occur after the load of B, they may both
1112 come up with different values:
1115 | | +------+ +-------+
1116 | |------>| A=1 |------ --->| A->0 |
1117 | | +------+ \ +-------+
1118 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1119 | | +------+ | +-------+
1120 | |------>| B=2 |--- | : :
1121 | | +------+ \ | : : +-------+
1122 +-------+ : : \ | +-------+ | |
1123 ---------->| B->2 |------>| |
1124 | +-------+ | CPU 2 |
1128 | | A->0 |------>| 1st |
1130 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1131 barrier causes all effects \ +-------+ | |
1132 prior to the storage of B ---->| A->1 |------>| 2nd |
1133 to be perceptible to CPU 2 +-------+ | |
1137 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1138 before the read barrier completes anyway:
1141 | | +------+ +-------+
1142 | |------>| A=1 |------ --->| A->0 |
1143 | | +------+ \ +-------+
1144 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1145 | | +------+ | +-------+
1146 | |------>| B=2 |--- | : :
1147 | | +------+ \ | : : +-------+
1148 +-------+ : : \ | +-------+ | |
1149 ---------->| B->2 |------>| |
1150 | +-------+ | CPU 2 |
1154 ---->| A->1 |------>| 1st |
1156 rrrrrrrrrrrrrrrrr | |
1158 | A->1 |------>| 2nd |
1163 The guarantee is that the second load will always come up with A == 1 if the
1164 load of B came up with B == 2. No such guarantee exists for the first load of
1165 A; that may come up with either A == 0 or A == 1.
1168 READ MEMORY BARRIERS VS LOAD SPECULATION
1169 ----------------------------------------
1171 Many CPUs speculate with loads: that is they see that they will need to load an
1172 item from memory, and they find a time where they're not using the bus for any
1173 other loads, and so do the load in advance - even though they haven't actually
1174 got to that point in the instruction execution flow yet. This permits the
1175 actual load instruction to potentially complete immediately because the CPU
1176 already has the value to hand.
1178 It may turn out that the CPU didn't actually need the value - perhaps because a
1179 branch circumvented the load - in which case it can discard the value or just
1180 cache it for later use.
1185 ======================= =======================
1187 DIVIDE } Divide instructions generally
1188 DIVIDE } take a long time to perform
1191 Which might appear as this:
1195 --->| B->2 |------>| |
1199 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1200 division speculates on the +-------+ ~ | |
1204 Once the divisions are complete --> : : ~-->| |
1205 the CPU can then perform the : : | |
1206 LOAD with immediate effect : : +-------+
1209 Placing a read barrier or a data dependency barrier just before the second
1213 ======================= =======================
1220 will force any value speculatively obtained to be reconsidered to an extent
1221 dependent on the type of barrier used. If there was no change made to the
1222 speculated memory location, then the speculated value will just be used:
1226 --->| B->2 |------>| |
1230 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1231 division speculates on the +-------+ ~ | |
1236 rrrrrrrrrrrrrrrr~ | |
1243 but if there was an update or an invalidation from another CPU pending, then
1244 the speculation will be cancelled and the value reloaded:
1248 --->| B->2 |------>| |
1252 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1253 division speculates on the +-------+ ~ | |
1258 rrrrrrrrrrrrrrrrr | |
1260 The speculation is discarded ---> --->| A->1 |------>| |
1261 and an updated value is +-------+ | |
1262 retrieved : : +-------+
1268 Transitivity is a deeply intuitive notion about ordering that is not
1269 always provided by real computer systems. The following example
1270 demonstrates transitivity (also called "cumulativity"):
1273 ======================= ======================= =======================
1275 STORE X=1 LOAD X STORE Y=1
1276 <general barrier> <general barrier>
1279 Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1280 This indicates that CPU 2's load from X in some sense follows CPU 1's
1281 store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1282 store to Y. The question is then "Can CPU 3's load from X return 0?"
1284 Because CPU 2's load from X in some sense came after CPU 1's store, it
1285 is natural to expect that CPU 3's load from X must therefore return 1.
1286 This expectation is an example of transitivity: if a load executing on
1287 CPU A follows a load from the same variable executing on CPU B, then
1288 CPU A's load must either return the same value that CPU B's load did,
1289 or must return some later value.
1291 In the Linux kernel, use of general memory barriers guarantees
1292 transitivity. Therefore, in the above example, if CPU 2's load from X
1293 returns 1 and its load from Y returns 0, then CPU 3's load from X must
1296 However, transitivity is -not- guaranteed for read or write barriers.
1297 For example, suppose that CPU 2's general barrier in the above example
1298 is changed to a read barrier as shown below:
1301 ======================= ======================= =======================
1303 STORE X=1 LOAD X STORE Y=1
1304 <read barrier> <general barrier>
1307 This substitution destroys transitivity: in this example, it is perfectly
1308 legal for CPU 2's load from X to return 1, its load from Y to return 0,
1309 and CPU 3's load from X to return 0.
1311 The key point is that although CPU 2's read barrier orders its pair
1312 of loads, it does not guarantee to order CPU 1's store. Therefore, if
1313 this example runs on a system where CPUs 1 and 2 share a store buffer
1314 or a level of cache, CPU 2 might have early access to CPU 1's writes.
1315 General barriers are therefore required to ensure that all CPUs agree
1316 on the combined order of CPU 1's and CPU 2's accesses.
1318 To reiterate, if your code requires transitivity, use general barriers
1322 ========================
1323 EXPLICIT KERNEL BARRIERS
1324 ========================
1326 The Linux kernel has a variety of different barriers that act at different
1329 (*) Compiler barrier.
1331 (*) CPU memory barriers.
1333 (*) MMIO write barrier.
1339 The Linux kernel has an explicit compiler barrier function that prevents the
1340 compiler from moving the memory accesses either side of it to the other side:
1344 This is a general barrier -- there are no read-read or write-write
1345 variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1346 thought of as weak forms of barrier() that affect only the specific
1347 accesses flagged by the READ_ONCE() or WRITE_ONCE().
1349 The barrier() function has the following effects:
1351 (*) Prevents the compiler from reordering accesses following the
1352 barrier() to precede any accesses preceding the barrier().
1353 One example use for this property is to ease communication between
1354 interrupt-handler code and the code that was interrupted.
1356 (*) Within a loop, forces the compiler to load the variables used
1357 in that loop's conditional on each pass through that loop.
1359 The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1360 optimizations that, while perfectly safe in single-threaded code, can
1361 be fatal in concurrent code. Here are some examples of these sorts
1364 (*) The compiler is within its rights to reorder loads and stores
1365 to the same variable, and in some cases, the CPU is within its
1366 rights to reorder loads to the same variable. This means that
1372 Might result in an older value of x stored in a[1] than in a[0].
1373 Prevent both the compiler and the CPU from doing this as follows:
1375 a[0] = READ_ONCE(x);
1376 a[1] = READ_ONCE(x);
1378 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1379 accesses from multiple CPUs to a single variable.
1381 (*) The compiler is within its rights to merge successive loads from
1382 the same variable. Such merging can cause the compiler to "optimize"
1386 do_something_with(tmp);
1388 into the following code, which, although in some sense legitimate
1389 for single-threaded code, is almost certainly not what the developer
1394 do_something_with(tmp);
1396 Use READ_ONCE() to prevent the compiler from doing this to you:
1398 while (tmp = READ_ONCE(a))
1399 do_something_with(tmp);
1401 (*) The compiler is within its rights to reload a variable, for example,
1402 in cases where high register pressure prevents the compiler from
1403 keeping all data of interest in registers. The compiler might
1404 therefore optimize the variable 'tmp' out of our previous example:
1407 do_something_with(tmp);
1409 This could result in the following code, which is perfectly safe in
1410 single-threaded code, but can be fatal in concurrent code:
1413 do_something_with(a);
1415 For example, the optimized version of this code could result in
1416 passing a zero to do_something_with() in the case where the variable
1417 a was modified by some other CPU between the "while" statement and
1418 the call to do_something_with().
1420 Again, use READ_ONCE() to prevent the compiler from doing this:
1422 while (tmp = READ_ONCE(a))
1423 do_something_with(tmp);
1425 Note that if the compiler runs short of registers, it might save
1426 tmp onto the stack. The overhead of this saving and later restoring
1427 is why compilers reload variables. Doing so is perfectly safe for
1428 single-threaded code, so you need to tell the compiler about cases
1429 where it is not safe.
1431 (*) The compiler is within its rights to omit a load entirely if it knows
1432 what the value will be. For example, if the compiler can prove that
1433 the value of variable 'a' is always zero, it can optimize this code:
1436 do_something_with(tmp);
1442 This transformation is a win for single-threaded code because it
1443 gets rid of a load and a branch. The problem is that the compiler
1444 will carry out its proof assuming that the current CPU is the only
1445 one updating variable 'a'. If variable 'a' is shared, then the
1446 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1447 compiler that it doesn't know as much as it thinks it does:
1449 while (tmp = READ_ONCE(a))
1450 do_something_with(tmp);
1452 But please note that the compiler is also closely watching what you
1453 do with the value after the READ_ONCE(). For example, suppose you
1454 do the following and MAX is a preprocessor macro with the value 1:
1456 while ((tmp = READ_ONCE(a)) % MAX)
1457 do_something_with(tmp);
1459 Then the compiler knows that the result of the "%" operator applied
1460 to MAX will always be zero, again allowing the compiler to optimize
1461 the code into near-nonexistence. (It will still load from the
1464 (*) Similarly, the compiler is within its rights to omit a store entirely
1465 if it knows that the variable already has the value being stored.
1466 Again, the compiler assumes that the current CPU is the only one
1467 storing into the variable, which can cause the compiler to do the
1468 wrong thing for shared variables. For example, suppose you have
1472 /* Code that does not store to variable a. */
1475 The compiler sees that the value of variable 'a' is already zero, so
1476 it might well omit the second store. This would come as a fatal
1477 surprise if some other CPU might have stored to variable 'a' in the
1480 Use WRITE_ONCE() to prevent the compiler from making this sort of
1484 /* Code that does not store to variable a. */
1487 (*) The compiler is within its rights to reorder memory accesses unless
1488 you tell it not to. For example, consider the following interaction
1489 between process-level code and an interrupt handler:
1491 void process_level(void)
1493 msg = get_message();
1497 void interrupt_handler(void)
1500 process_message(msg);
1503 There is nothing to prevent the compiler from transforming
1504 process_level() to the following, in fact, this might well be a
1505 win for single-threaded code:
1507 void process_level(void)
1510 msg = get_message();
1513 If the interrupt occurs between these two statement, then
1514 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
1515 to prevent this as follows:
1517 void process_level(void)
1519 WRITE_ONCE(msg, get_message());
1520 WRITE_ONCE(flag, true);
1523 void interrupt_handler(void)
1525 if (READ_ONCE(flag))
1526 process_message(READ_ONCE(msg));
1529 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1530 interrupt_handler() are needed if this interrupt handler can itself
1531 be interrupted by something that also accesses 'flag' and 'msg',
1532 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1533 and WRITE_ONCE() are not needed in interrupt_handler() other than
1534 for documentation purposes. (Note also that nested interrupts
1535 do not typically occur in modern Linux kernels, in fact, if an
1536 interrupt handler returns with interrupts enabled, you will get a
1539 You should assume that the compiler can move READ_ONCE() and
1540 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1541 barrier(), or similar primitives.
1543 This effect could also be achieved using barrier(), but READ_ONCE()
1544 and WRITE_ONCE() are more selective: With READ_ONCE() and
1545 WRITE_ONCE(), the compiler need only forget the contents of the
1546 indicated memory locations, while with barrier() the compiler must
1547 discard the value of all memory locations that it has currented
1548 cached in any machine registers. Of course, the compiler must also
1549 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1550 though the CPU of course need not do so.
1552 (*) The compiler is within its rights to invent stores to a variable,
1553 as in the following example:
1560 The compiler might save a branch by optimizing this as follows:
1566 In single-threaded code, this is not only safe, but also saves
1567 a branch. Unfortunately, in concurrent code, this optimization
1568 could cause some other CPU to see a spurious value of 42 -- even
1569 if variable 'a' was never zero -- when loading variable 'b'.
1570 Use WRITE_ONCE() to prevent this as follows:
1577 The compiler can also invent loads. These are usually less
1578 damaging, but they can result in cache-line bouncing and thus in
1579 poor performance and scalability. Use READ_ONCE() to prevent
1582 (*) For aligned memory locations whose size allows them to be accessed
1583 with a single memory-reference instruction, prevents "load tearing"
1584 and "store tearing," in which a single large access is replaced by
1585 multiple smaller accesses. For example, given an architecture having
1586 16-bit store instructions with 7-bit immediate fields, the compiler
1587 might be tempted to use two 16-bit store-immediate instructions to
1588 implement the following 32-bit store:
1592 Please note that GCC really does use this sort of optimization,
1593 which is not surprising given that it would likely take more
1594 than two instructions to build the constant and then store it.
1595 This optimization can therefore be a win in single-threaded code.
1596 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1597 this optimization in a volatile store. In the absence of such bugs,
1598 use of WRITE_ONCE() prevents store tearing in the following example:
1600 WRITE_ONCE(p, 0x00010002);
1602 Use of packed structures can also result in load and store tearing,
1605 struct __attribute__((__packed__)) foo {
1610 struct foo foo1, foo2;
1617 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1618 volatile markings, the compiler would be well within its rights to
1619 implement these three assignment statements as a pair of 32-bit
1620 loads followed by a pair of 32-bit stores. This would result in
1621 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1622 and WRITE_ONCE() again prevent tearing in this example:
1625 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
1628 All that aside, it is never necessary to use READ_ONCE() and
1629 WRITE_ONCE() on a variable that has been marked volatile. For example,
1630 because 'jiffies' is marked volatile, it is never necessary to
1631 say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1632 WRITE_ONCE() are implemented as volatile casts, which has no effect when
1633 its argument is already marked volatile.
1635 Please note that these compiler barriers have no direct effect on the CPU,
1636 which may then reorder things however it wishes.
1642 The Linux kernel has eight basic CPU memory barriers:
1644 TYPE MANDATORY SMP CONDITIONAL
1645 =============== ======================= ===========================
1646 GENERAL mb() smp_mb()
1647 WRITE wmb() smp_wmb()
1648 READ rmb() smp_rmb()
1649 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1652 All memory barriers except the data dependency barriers imply a compiler
1653 barrier. Data dependencies do not impose any additional compiler ordering.
1655 Aside: In the case of data dependencies, the compiler would be expected
1656 to issue the loads in the correct order (eg. `a[b]` would have to load
1657 the value of b before loading a[b]), however there is no guarantee in
1658 the C specification that the compiler may not speculate the value of b
1659 (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1660 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1661 having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1662 has not yet been reached about these problems, however the READ_ONCE()
1663 macro is a good place to start looking.
1665 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1666 systems because it is assumed that a CPU will appear to be self-consistent,
1667 and will order overlapping accesses correctly with respect to itself.
1669 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1670 references to shared memory on SMP systems, though the use of locking instead
1673 Mandatory barriers should not be used to control SMP effects, since mandatory
1674 barriers unnecessarily impose overhead on UP systems. They may, however, be
1675 used to control MMIO effects on accesses through relaxed memory I/O windows.
1676 These are required even on non-SMP systems as they affect the order in which
1677 memory operations appear to a device by prohibiting both the compiler and the
1678 CPU from reordering them.
1681 There are some more advanced barrier functions:
1683 (*) smp_store_mb(var, value)
1685 This assigns the value to the variable and then inserts a full memory
1686 barrier after it, depending on the function. It isn't guaranteed to
1687 insert anything more than a compiler barrier in a UP compilation.
1690 (*) smp_mb__before_atomic();
1691 (*) smp_mb__after_atomic();
1693 These are for use with atomic (such as add, subtract, increment and
1694 decrement) functions that don't return a value, especially when used for
1695 reference counting. These functions do not imply memory barriers.
1697 These are also used for atomic bitop functions that do not return a
1698 value (such as set_bit and clear_bit).
1700 As an example, consider a piece of code that marks an object as being dead
1701 and then decrements the object's reference count:
1704 smp_mb__before_atomic();
1705 atomic_dec(&obj->ref_count);
1707 This makes sure that the death mark on the object is perceived to be set
1708 *before* the reference counter is decremented.
1710 See Documentation/atomic_ops.txt for more information. See the "Atomic
1711 operations" subsection for information on where to use these.
1714 (*) lockless_dereference();
1715 This can be thought of as a pointer-fetch wrapper around the
1716 smp_read_barrier_depends() data-dependency barrier.
1718 This is also similar to rcu_dereference(), but in cases where
1719 object lifetime is handled by some mechanism other than RCU, for
1720 example, when the objects removed only when the system goes down.
1721 In addition, lockless_dereference() is used in some data structures
1722 that can be used both with and without RCU.
1728 These are for use with consistent memory to guarantee the ordering
1729 of writes or reads of shared memory accessible to both the CPU and a
1732 For example, consider a device driver that shares memory with a device
1733 and uses a descriptor status value to indicate if the descriptor belongs
1734 to the device or the CPU, and a doorbell to notify it when new
1735 descriptors are available:
1737 if (desc->status != DEVICE_OWN) {
1738 /* do not read data until we own descriptor */
1741 /* read/modify data */
1742 read_data = desc->data;
1743 desc->data = write_data;
1745 /* flush modifications before status update */
1748 /* assign ownership */
1749 desc->status = DEVICE_OWN;
1751 /* force memory to sync before notifying device via MMIO */
1754 /* notify device of new descriptors */
1755 writel(DESC_NOTIFY, doorbell);
1758 The dma_rmb() allows us guarantee the device has released ownership
1759 before we read the data from the descriptor, and the dma_wmb() allows
1760 us to guarantee the data is written to the descriptor before the device
1761 can see it now has ownership. The wmb() is needed to guarantee that the
1762 cache coherent memory writes have completed before attempting a write to
1763 the cache incoherent MMIO region.
1765 See Documentation/DMA-API.txt for more information on consistent memory.
1770 The Linux kernel also has a special barrier for use with memory-mapped I/O
1775 This is a variation on the mandatory write barrier that causes writes to weakly
1776 ordered I/O regions to be partially ordered. Its effects may go beyond the
1777 CPU->Hardware interface and actually affect the hardware at some level.
1779 See the subsection "Locks vs I/O accesses" for more information.
1782 ===============================
1783 IMPLICIT KERNEL MEMORY BARRIERS
1784 ===============================
1786 Some of the other functions in the linux kernel imply memory barriers, amongst
1787 which are locking and scheduling functions.
1789 This specification is a _minimum_ guarantee; any particular architecture may
1790 provide more substantial guarantees, but these may not be relied upon outside
1791 of arch specific code.
1797 The Linux kernel has a number of locking constructs:
1805 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1806 for each construct. These operations all imply certain barriers:
1808 (1) ACQUIRE operation implication:
1810 Memory operations issued after the ACQUIRE will be completed after the
1811 ACQUIRE operation has completed.
1813 Memory operations issued before the ACQUIRE may be completed after
1814 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
1815 combined with a following ACQUIRE, orders prior stores against
1816 subsequent loads and stores. Note that this is weaker than smp_mb()!
1817 The smp_mb__before_spinlock() primitive is free on many architectures.
1819 (2) RELEASE operation implication:
1821 Memory operations issued before the RELEASE will be completed before the
1822 RELEASE operation has completed.
1824 Memory operations issued after the RELEASE may be completed before the
1825 RELEASE operation has completed.
1827 (3) ACQUIRE vs ACQUIRE implication:
1829 All ACQUIRE operations issued before another ACQUIRE operation will be
1830 completed before that ACQUIRE operation.
1832 (4) ACQUIRE vs RELEASE implication:
1834 All ACQUIRE operations issued before a RELEASE operation will be
1835 completed before the RELEASE operation.
1837 (5) Failed conditional ACQUIRE implication:
1839 Certain locking variants of the ACQUIRE operation may fail, either due to
1840 being unable to get the lock immediately, or due to receiving an unblocked
1841 signal whilst asleep waiting for the lock to become available. Failed
1842 locks do not imply any sort of barrier.
1844 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
1845 one-way barriers is that the effects of instructions outside of a critical
1846 section may seep into the inside of the critical section.
1848 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
1849 because it is possible for an access preceding the ACQUIRE to happen after the
1850 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
1851 the two accesses can themselves then cross:
1860 ACQUIRE M, STORE *B, STORE *A, RELEASE M
1862 When the ACQUIRE and RELEASE are a lock acquisition and release,
1863 respectively, this same reordering can occur if the lock's ACQUIRE and
1864 RELEASE are to the same lock variable, but only from the perspective of
1865 another CPU not holding that lock. In short, a ACQUIRE followed by an
1866 RELEASE may -not- be assumed to be a full memory barrier.
1868 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
1869 not imply a full memory barrier. Therefore, the CPU's execution of the
1870 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
1880 ACQUIRE N, STORE *B, STORE *A, RELEASE M
1882 It might appear that this reordering could introduce a deadlock.
1883 However, this cannot happen because if such a deadlock threatened,
1884 the RELEASE would simply complete, thereby avoiding the deadlock.
1888 One key point is that we are only talking about the CPU doing
1889 the reordering, not the compiler. If the compiler (or, for
1890 that matter, the developer) switched the operations, deadlock
1893 But suppose the CPU reordered the operations. In this case,
1894 the unlock precedes the lock in the assembly code. The CPU
1895 simply elected to try executing the later lock operation first.
1896 If there is a deadlock, this lock operation will simply spin (or
1897 try to sleep, but more on that later). The CPU will eventually
1898 execute the unlock operation (which preceded the lock operation
1899 in the assembly code), which will unravel the potential deadlock,
1900 allowing the lock operation to succeed.
1902 But what if the lock is a sleeplock? In that case, the code will
1903 try to enter the scheduler, where it will eventually encounter
1904 a memory barrier, which will force the earlier unlock operation
1905 to complete, again unraveling the deadlock. There might be
1906 a sleep-unlock race, but the locking primitive needs to resolve
1907 such races properly in any case.
1909 Locks and semaphores may not provide any guarantee of ordering on UP compiled
1910 systems, and so cannot be counted on in such a situation to actually achieve
1911 anything at all - especially with respect to I/O accesses - unless combined
1912 with interrupt disabling operations.
1914 See also the section on "Inter-CPU locking barrier effects".
1917 As an example, consider the following:
1928 The following sequence of events is acceptable:
1930 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
1932 [+] Note that {*F,*A} indicates a combined access.
1934 But none of the following are:
1936 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
1937 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
1938 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
1939 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
1943 INTERRUPT DISABLING FUNCTIONS
1944 -----------------------------
1946 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
1947 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
1948 barriers are required in such a situation, they must be provided from some
1952 SLEEP AND WAKE-UP FUNCTIONS
1953 ---------------------------
1955 Sleeping and waking on an event flagged in global data can be viewed as an
1956 interaction between two pieces of data: the task state of the task waiting for
1957 the event and the global data used to indicate the event. To make sure that
1958 these appear to happen in the right order, the primitives to begin the process
1959 of going to sleep, and the primitives to initiate a wake up imply certain
1962 Firstly, the sleeper normally follows something like this sequence of events:
1965 set_current_state(TASK_UNINTERRUPTIBLE);
1966 if (event_indicated)
1971 A general memory barrier is interpolated automatically by set_current_state()
1972 after it has altered the task state:
1975 ===============================
1976 set_current_state();
1978 STORE current->state
1980 LOAD event_indicated
1982 set_current_state() may be wrapped by:
1985 prepare_to_wait_exclusive();
1987 which therefore also imply a general memory barrier after setting the state.
1988 The whole sequence above is available in various canned forms, all of which
1989 interpolate the memory barrier in the right place:
1992 wait_event_interruptible();
1993 wait_event_interruptible_exclusive();
1994 wait_event_interruptible_timeout();
1995 wait_event_killable();
1996 wait_event_timeout();
2001 Secondly, code that performs a wake up normally follows something like this:
2003 event_indicated = 1;
2004 wake_up(&event_wait_queue);
2008 event_indicated = 1;
2009 wake_up_process(event_daemon);
2011 A write memory barrier is implied by wake_up() and co. if and only if they wake
2012 something up. The barrier occurs before the task state is cleared, and so sits
2013 between the STORE to indicate the event and the STORE to set TASK_RUNNING:
2016 =============================== ===============================
2017 set_current_state(); STORE event_indicated
2018 smp_store_mb(); wake_up();
2019 STORE current->state <write barrier>
2020 <general barrier> STORE current->state
2021 LOAD event_indicated
2023 To repeat, this write memory barrier is present if and only if something
2024 is actually awakened. To see this, consider the following sequence of
2025 events, where X and Y are both initially zero:
2028 =============================== ===============================
2029 X = 1; STORE event_indicated
2030 smp_mb(); wake_up();
2031 Y = 1; wait_event(wq, Y == 1);
2032 wake_up(); load from Y sees 1, no memory barrier
2033 load from X might see 0
2035 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2038 The available waker functions include:
2044 wake_up_interruptible();
2045 wake_up_interruptible_all();
2046 wake_up_interruptible_nr();
2047 wake_up_interruptible_poll();
2048 wake_up_interruptible_sync();
2049 wake_up_interruptible_sync_poll();
2051 wake_up_locked_poll();
2057 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
2058 order multiple stores before the wake-up with respect to loads of those stored
2059 values after the sleeper has called set_current_state(). For instance, if the
2062 set_current_state(TASK_INTERRUPTIBLE);
2063 if (event_indicated)
2065 __set_current_state(TASK_RUNNING);
2066 do_something(my_data);
2071 event_indicated = 1;
2072 wake_up(&event_wait_queue);
2074 there's no guarantee that the change to event_indicated will be perceived by
2075 the sleeper as coming after the change to my_data. In such a circumstance, the
2076 code on both sides must interpolate its own memory barriers between the
2077 separate data accesses. Thus the above sleeper ought to do:
2079 set_current_state(TASK_INTERRUPTIBLE);
2080 if (event_indicated) {
2082 do_something(my_data);
2085 and the waker should do:
2089 event_indicated = 1;
2090 wake_up(&event_wait_queue);
2093 MISCELLANEOUS FUNCTIONS
2094 -----------------------
2096 Other functions that imply barriers:
2098 (*) schedule() and similar imply full memory barriers.
2101 ===================================
2102 INTER-CPU ACQUIRING BARRIER EFFECTS
2103 ===================================
2105 On SMP systems locking primitives give a more substantial form of barrier: one
2106 that does affect memory access ordering on other CPUs, within the context of
2107 conflict on any particular lock.
2110 ACQUIRES VS MEMORY ACCESSES
2111 ---------------------------
2113 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2114 three CPUs; then should the following sequence of events occur:
2117 =============================== ===============================
2118 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2120 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2121 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
2123 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
2125 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2126 through *H occur in, other than the constraints imposed by the separate locks
2127 on the separate CPUs. It might, for example, see:
2129 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2131 But it won't see any of:
2133 *B, *C or *D preceding ACQUIRE M
2134 *A, *B or *C following RELEASE M
2135 *F, *G or *H preceding ACQUIRE Q
2136 *E, *F or *G following RELEASE Q
2140 ACQUIRES VS I/O ACCESSES
2141 ------------------------
2143 Under certain circumstances (especially involving NUMA), I/O accesses within
2144 two spinlocked sections on two different CPUs may be seen as interleaved by the
2145 PCI bridge, because the PCI bridge does not necessarily participate in the
2146 cache-coherence protocol, and is therefore incapable of issuing the required
2147 read memory barriers.
2152 =============================== ===============================
2162 may be seen by the PCI bridge as follows:
2164 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
2166 which would probably cause the hardware to malfunction.
2169 What is necessary here is to intervene with an mmiowb() before dropping the
2170 spinlock, for example:
2173 =============================== ===============================
2185 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2186 before either of the stores issued on CPU 2.
2189 Furthermore, following a store by a load from the same device obviates the need
2190 for the mmiowb(), because the load forces the store to complete before the load
2194 =============================== ===============================
2205 See Documentation/DocBook/deviceiobook.tmpl for more information.
2208 =================================
2209 WHERE ARE MEMORY BARRIERS NEEDED?
2210 =================================
2212 Under normal operation, memory operation reordering is generally not going to
2213 be a problem as a single-threaded linear piece of code will still appear to
2214 work correctly, even if it's in an SMP kernel. There are, however, four
2215 circumstances in which reordering definitely _could_ be a problem:
2217 (*) Interprocessor interaction.
2219 (*) Atomic operations.
2221 (*) Accessing devices.
2226 INTERPROCESSOR INTERACTION
2227 --------------------------
2229 When there's a system with more than one processor, more than one CPU in the
2230 system may be working on the same data set at the same time. This can cause
2231 synchronisation problems, and the usual way of dealing with them is to use
2232 locks. Locks, however, are quite expensive, and so it may be preferable to
2233 operate without the use of a lock if at all possible. In such a case
2234 operations that affect both CPUs may have to be carefully ordered to prevent
2237 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2238 queued on the semaphore, by virtue of it having a piece of its stack linked to
2239 the semaphore's list of waiting processes:
2241 struct rw_semaphore {
2244 struct list_head waiters;
2247 struct rwsem_waiter {
2248 struct list_head list;
2249 struct task_struct *task;
2252 To wake up a particular waiter, the up_read() or up_write() functions have to:
2254 (1) read the next pointer from this waiter's record to know as to where the
2255 next waiter record is;
2257 (2) read the pointer to the waiter's task structure;
2259 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2261 (4) call wake_up_process() on the task; and
2263 (5) release the reference held on the waiter's task struct.
2265 In other words, it has to perform this sequence of events:
2267 LOAD waiter->list.next;
2273 and if any of these steps occur out of order, then the whole thing may
2276 Once it has queued itself and dropped the semaphore lock, the waiter does not
2277 get the lock again; it instead just waits for its task pointer to be cleared
2278 before proceeding. Since the record is on the waiter's stack, this means that
2279 if the task pointer is cleared _before_ the next pointer in the list is read,
2280 another CPU might start processing the waiter and might clobber the waiter's
2281 stack before the up*() function has a chance to read the next pointer.
2283 Consider then what might happen to the above sequence of events:
2286 =============================== ===============================
2293 Woken up by other event
2298 foo() clobbers *waiter
2300 LOAD waiter->list.next;
2303 This could be dealt with using the semaphore lock, but then the down_xxx()
2304 function has to needlessly get the spinlock again after being woken up.
2306 The way to deal with this is to insert a general SMP memory barrier:
2308 LOAD waiter->list.next;
2315 In this case, the barrier makes a guarantee that all memory accesses before the
2316 barrier will appear to happen before all the memory accesses after the barrier
2317 with respect to the other CPUs on the system. It does _not_ guarantee that all
2318 the memory accesses before the barrier will be complete by the time the barrier
2319 instruction itself is complete.
2321 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2322 compiler barrier, thus making sure the compiler emits the instructions in the
2323 right order without actually intervening in the CPU. Since there's only one
2324 CPU, that CPU's dependency ordering logic will take care of everything else.
2330 Whilst they are technically interprocessor interaction considerations, atomic
2331 operations are noted specially as some of them imply full memory barriers and
2332 some don't, but they're very heavily relied on as a group throughout the
2335 Any atomic operation that modifies some state in memory and returns information
2336 about the state (old or new) implies an SMP-conditional general memory barrier
2337 (smp_mb()) on each side of the actual operation (with the exception of
2338 explicit lock operations, described later). These include:
2341 atomic_xchg(); atomic_long_xchg();
2342 atomic_inc_return(); atomic_long_inc_return();
2343 atomic_dec_return(); atomic_long_dec_return();
2344 atomic_add_return(); atomic_long_add_return();
2345 atomic_sub_return(); atomic_long_sub_return();
2346 atomic_inc_and_test(); atomic_long_inc_and_test();
2347 atomic_dec_and_test(); atomic_long_dec_and_test();
2348 atomic_sub_and_test(); atomic_long_sub_and_test();
2349 atomic_add_negative(); atomic_long_add_negative();
2351 test_and_clear_bit();
2352 test_and_change_bit();
2356 atomic_cmpxchg(); atomic_long_cmpxchg();
2357 atomic_add_unless(); atomic_long_add_unless();
2359 These are used for such things as implementing ACQUIRE-class and RELEASE-class
2360 operations and adjusting reference counters towards object destruction, and as
2361 such the implicit memory barrier effects are necessary.
2364 The following operations are potential problems as they do _not_ imply memory
2365 barriers, but might be used for implementing such things as RELEASE-class
2373 With these the appropriate explicit memory barrier should be used if necessary
2374 (smp_mb__before_atomic() for instance).
2377 The following also do _not_ imply memory barriers, and so may require explicit
2378 memory barriers under some circumstances (smp_mb__before_atomic() for
2386 If they're used for statistics generation, then they probably don't need memory
2387 barriers, unless there's a coupling between statistical data.
2389 If they're used for reference counting on an object to control its lifetime,
2390 they probably don't need memory barriers because either the reference count
2391 will be adjusted inside a locked section, or the caller will already hold
2392 sufficient references to make the lock, and thus a memory barrier unnecessary.
2394 If they're used for constructing a lock of some description, then they probably
2395 do need memory barriers as a lock primitive generally has to do things in a
2398 Basically, each usage case has to be carefully considered as to whether memory
2399 barriers are needed or not.
2401 The following operations are special locking primitives:
2403 test_and_set_bit_lock();
2405 __clear_bit_unlock();
2407 These implement ACQUIRE-class and RELEASE-class operations. These should be used in
2408 preference to other operations when implementing locking primitives, because
2409 their implementations can be optimised on many architectures.
2411 [!] Note that special memory barrier primitives are available for these
2412 situations because on some CPUs the atomic instructions used imply full memory
2413 barriers, and so barrier instructions are superfluous in conjunction with them,
2414 and in such cases the special barrier primitives will be no-ops.
2416 See Documentation/atomic_ops.txt for more information.
2422 Many devices can be memory mapped, and so appear to the CPU as if they're just
2423 a set of memory locations. To control such a device, the driver usually has to
2424 make the right memory accesses in exactly the right order.
2426 However, having a clever CPU or a clever compiler creates a potential problem
2427 in that the carefully sequenced accesses in the driver code won't reach the
2428 device in the requisite order if the CPU or the compiler thinks it is more
2429 efficient to reorder, combine or merge accesses - something that would cause
2430 the device to malfunction.
2432 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2433 routines - such as inb() or writel() - which know how to make such accesses
2434 appropriately sequential. Whilst this, for the most part, renders the explicit
2435 use of memory barriers unnecessary, there are a couple of situations where they
2438 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2439 so for _all_ general drivers locks should be used and mmiowb() must be
2440 issued prior to unlocking the critical section.
2442 (2) If the accessor functions are used to refer to an I/O memory window with
2443 relaxed memory access properties, then _mandatory_ memory barriers are
2444 required to enforce ordering.
2446 See Documentation/DocBook/deviceiobook.tmpl for more information.
2452 A driver may be interrupted by its own interrupt service routine, and thus the
2453 two parts of the driver may interfere with each other's attempts to control or
2456 This may be alleviated - at least in part - by disabling local interrupts (a
2457 form of locking), such that the critical operations are all contained within
2458 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2459 routine is executing, the driver's core may not run on the same CPU, and its
2460 interrupt is not permitted to happen again until the current interrupt has been
2461 handled, thus the interrupt handler does not need to lock against that.
2463 However, consider a driver that was talking to an ethernet card that sports an
2464 address register and a data register. If that driver's core talks to the card
2465 under interrupt-disablement and then the driver's interrupt handler is invoked:
2476 The store to the data register might happen after the second store to the
2477 address register if ordering rules are sufficiently relaxed:
2479 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2482 If ordering rules are relaxed, it must be assumed that accesses done inside an
2483 interrupt disabled section may leak outside of it and may interleave with
2484 accesses performed in an interrupt - and vice versa - unless implicit or
2485 explicit barriers are used.
2487 Normally this won't be a problem because the I/O accesses done inside such
2488 sections will include synchronous load operations on strictly ordered I/O
2489 registers that form implicit I/O barriers. If this isn't sufficient then an
2490 mmiowb() may need to be used explicitly.
2493 A similar situation may occur between an interrupt routine and two routines
2494 running on separate CPUs that communicate with each other. If such a case is
2495 likely, then interrupt-disabling locks should be used to guarantee ordering.
2498 ==========================
2499 KERNEL I/O BARRIER EFFECTS
2500 ==========================
2502 When accessing I/O memory, drivers should use the appropriate accessor
2507 These are intended to talk to I/O space rather than memory space, but
2508 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
2509 indeed have special I/O space access cycles and instructions, but many
2510 CPUs don't have such a concept.
2512 The PCI bus, amongst others, defines an I/O space concept which - on such
2513 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
2514 space. However, it may also be mapped as a virtual I/O space in the CPU's
2515 memory map, particularly on those CPUs that don't support alternate I/O
2518 Accesses to this space may be fully synchronous (as on i386), but
2519 intermediary bridges (such as the PCI host bridge) may not fully honour
2522 They are guaranteed to be fully ordered with respect to each other.
2524 They are not guaranteed to be fully ordered with respect to other types of
2525 memory and I/O operation.
2527 (*) readX(), writeX():
2529 Whether these are guaranteed to be fully ordered and uncombined with
2530 respect to each other on the issuing CPU depends on the characteristics
2531 defined for the memory window through which they're accessing. On later
2532 i386 architecture machines, for example, this is controlled by way of the
2535 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2536 provided they're not accessing a prefetchable device.
2538 However, intermediary hardware (such as a PCI bridge) may indulge in
2539 deferral if it so wishes; to flush a store, a load from the same location
2540 is preferred[*], but a load from the same device or from configuration
2541 space should suffice for PCI.
2543 [*] NOTE! attempting to load from the same location as was written to may
2544 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2547 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2548 force stores to be ordered.
2550 Please refer to the PCI specification for more information on interactions
2551 between PCI transactions.
2553 (*) readX_relaxed(), writeX_relaxed()
2555 These are similar to readX() and writeX(), but provide weaker memory
2556 ordering guarantees. Specifically, they do not guarantee ordering with
2557 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2558 ordering with respect to LOCK or UNLOCK operations. If the latter is
2559 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2560 the same peripheral are guaranteed to be ordered with respect to each
2563 (*) ioreadX(), iowriteX()
2565 These will perform appropriately for the type of access they're actually
2566 doing, be it inX()/outX() or readX()/writeX().
2569 ========================================
2570 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2571 ========================================
2573 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2574 maintain the appearance of program causality with respect to itself. Some CPUs
2575 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2576 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2577 of arch-specific code.
2579 This means that it must be considered that the CPU will execute its instruction
2580 stream in any order it feels like - or even in parallel - provided that if an
2581 instruction in the stream depends on an earlier instruction, then that
2582 earlier instruction must be sufficiently complete[*] before the later
2583 instruction may proceed; in other words: provided that the appearance of
2584 causality is maintained.
2586 [*] Some instructions have more than one effect - such as changing the
2587 condition codes, changing registers or changing memory - and different
2588 instructions may depend on different effects.
2590 A CPU may also discard any instruction sequence that winds up having no
2591 ultimate effect. For example, if two adjacent instructions both load an
2592 immediate value into the same register, the first may be discarded.
2595 Similarly, it has to be assumed that compiler might reorder the instruction
2596 stream in any way it sees fit, again provided the appearance of causality is
2600 ============================
2601 THE EFFECTS OF THE CPU CACHE
2602 ============================
2604 The way cached memory operations are perceived across the system is affected to
2605 a certain extent by the caches that lie between CPUs and memory, and by the
2606 memory coherence system that maintains the consistency of state in the system.
2608 As far as the way a CPU interacts with another part of the system through the
2609 caches goes, the memory system has to include the CPU's caches, and memory
2610 barriers for the most part act at the interface between the CPU and its cache
2611 (memory barriers logically act on the dotted line in the following diagram):
2613 <--- CPU ---> : <----------- Memory ----------->
2615 +--------+ +--------+ : +--------+ +-----------+
2616 | | | | : | | | | +--------+
2617 | CPU | | Memory | : | CPU | | | | |
2618 | Core |--->| Access |----->| Cache |<-->| | | |
2619 | | | Queue | : | | | |--->| Memory |
2620 | | | | : | | | | | |
2621 +--------+ +--------+ : +--------+ | | | |
2622 : | Cache | +--------+
2624 : | Mechanism | +--------+
2625 +--------+ +--------+ : +--------+ | | | |
2626 | | | | : | | | | | |
2627 | CPU | | Memory | : | CPU | | |--->| Device |
2628 | Core |--->| Access |----->| Cache |<-->| | | |
2629 | | | Queue | : | | | | | |
2630 | | | | : | | | | +--------+
2631 +--------+ +--------+ : +--------+ +-----------+
2635 Although any particular load or store may not actually appear outside of the
2636 CPU that issued it since it may have been satisfied within the CPU's own cache,
2637 it will still appear as if the full memory access had taken place as far as the
2638 other CPUs are concerned since the cache coherency mechanisms will migrate the
2639 cacheline over to the accessing CPU and propagate the effects upon conflict.
2641 The CPU core may execute instructions in any order it deems fit, provided the
2642 expected program causality appears to be maintained. Some of the instructions
2643 generate load and store operations which then go into the queue of memory
2644 accesses to be performed. The core may place these in the queue in any order
2645 it wishes, and continue execution until it is forced to wait for an instruction
2648 What memory barriers are concerned with is controlling the order in which
2649 accesses cross from the CPU side of things to the memory side of things, and
2650 the order in which the effects are perceived to happen by the other observers
2653 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2654 their own loads and stores as if they had happened in program order.
2656 [!] MMIO or other device accesses may bypass the cache system. This depends on
2657 the properties of the memory window through which devices are accessed and/or
2658 the use of any special device communication instructions the CPU may have.
2664 Life isn't quite as simple as it may appear above, however: for while the
2665 caches are expected to be coherent, there's no guarantee that that coherency
2666 will be ordered. This means that whilst changes made on one CPU will
2667 eventually become visible on all CPUs, there's no guarantee that they will
2668 become apparent in the same order on those other CPUs.
2671 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
2672 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2677 +--------+ : +--->| Cache A |<------->| |
2678 | | : | +---------+ | |
2680 | | : | +---------+ | |
2681 +--------+ : +--->| Cache B |<------->| |
2684 : +---------+ | System |
2685 +--------+ : +--->| Cache C |<------->| |
2686 | | : | +---------+ | |
2688 | | : | +---------+ | |
2689 +--------+ : +--->| Cache D |<------->| |
2694 Imagine the system has the following properties:
2696 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
2699 (*) an even-numbered cache line may be in cache B, cache D or it may still be
2702 (*) whilst the CPU core is interrogating one cache, the other cache may be
2703 making use of the bus to access the rest of the system - perhaps to
2704 displace a dirty cacheline or to do a speculative load;
2706 (*) each cache has a queue of operations that need to be applied to that cache
2707 to maintain coherency with the rest of the system;
2709 (*) the coherency queue is not flushed by normal loads to lines already
2710 present in the cache, even though the contents of the queue may
2711 potentially affect those loads.
2713 Imagine, then, that two writes are made on the first CPU, with a write barrier
2714 between them to guarantee that they will appear to reach that CPU's caches in
2715 the requisite order:
2718 =============== =============== =======================================
2719 u == 0, v == 1 and p == &u, q == &u
2721 smp_wmb(); Make sure change to v is visible before
2723 <A:modify v=2> v is now in cache A exclusively
2725 <B:modify p=&v> p is now in cache B exclusively
2727 The write memory barrier forces the other CPUs in the system to perceive that
2728 the local CPU's caches have apparently been updated in the correct order. But
2729 now imagine that the second CPU wants to read those values:
2732 =============== =============== =======================================
2737 The above pair of reads may then fail to happen in the expected order, as the
2738 cacheline holding p may get updated in one of the second CPU's caches whilst
2739 the update to the cacheline holding v is delayed in the other of the second
2740 CPU's caches by some other cache event:
2743 =============== =============== =======================================
2744 u == 0, v == 1 and p == &u, q == &u
2747 <A:modify v=2> <C:busy>
2751 <B:modify p=&v> <D:commit p=&v>
2754 <C:read *q> Reads from v before v updated in cache
2758 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
2759 no guarantee that, without intervention, the order of update will be the same
2760 as that committed on CPU 1.
2763 To intervene, we need to interpolate a data dependency barrier or a read
2764 barrier between the loads. This will force the cache to commit its coherency
2765 queue before processing any further requests:
2768 =============== =============== =======================================
2769 u == 0, v == 1 and p == &u, q == &u
2772 <A:modify v=2> <C:busy>
2776 <B:modify p=&v> <D:commit p=&v>
2778 smp_read_barrier_depends()
2782 <C:read *q> Reads from v after v updated in cache
2785 This sort of problem can be encountered on DEC Alpha processors as they have a
2786 split cache that improves performance by making better use of the data bus.
2787 Whilst most CPUs do imply a data dependency barrier on the read when a memory
2788 access depends on a read, not all do, so it may not be relied on.
2790 Other CPUs may also have split caches, but must coordinate between the various
2791 cachelets for normal memory accesses. The semantics of the Alpha removes the
2792 need for coordination in the absence of memory barriers.
2795 CACHE COHERENCY VS DMA
2796 ----------------------
2798 Not all systems maintain cache coherency with respect to devices doing DMA. In
2799 such cases, a device attempting DMA may obtain stale data from RAM because
2800 dirty cache lines may be resident in the caches of various CPUs, and may not
2801 have been written back to RAM yet. To deal with this, the appropriate part of
2802 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2803 invalidate them as well).
2805 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2806 cache lines being written back to RAM from a CPU's cache after the device has
2807 installed its own data, or cache lines present in the CPU's cache may simply
2808 obscure the fact that RAM has been updated, until at such time as the cacheline
2809 is discarded from the CPU's cache and reloaded. To deal with this, the
2810 appropriate part of the kernel must invalidate the overlapping bits of the
2813 See Documentation/cachetlb.txt for more information on cache management.
2816 CACHE COHERENCY VS MMIO
2817 -----------------------
2819 Memory mapped I/O usually takes place through memory locations that are part of
2820 a window in the CPU's memory space that has different properties assigned than
2821 the usual RAM directed window.
2823 Amongst these properties is usually the fact that such accesses bypass the
2824 caching entirely and go directly to the device buses. This means MMIO accesses
2825 may, in effect, overtake accesses to cached memory that were emitted earlier.
2826 A memory barrier isn't sufficient in such a case, but rather the cache must be
2827 flushed between the cached memory write and the MMIO access if the two are in
2831 =========================
2832 THE THINGS CPUS GET UP TO
2833 =========================
2835 A programmer might take it for granted that the CPU will perform memory
2836 operations in exactly the order specified, so that if the CPU is, for example,
2837 given the following piece of code to execute:
2845 they would then expect that the CPU will complete the memory operation for each
2846 instruction before moving on to the next one, leading to a definite sequence of
2847 operations as seen by external observers in the system:
2849 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2852 Reality is, of course, much messier. With many CPUs and compilers, the above
2853 assumption doesn't hold because:
2855 (*) loads are more likely to need to be completed immediately to permit
2856 execution progress, whereas stores can often be deferred without a
2859 (*) loads may be done speculatively, and the result discarded should it prove
2860 to have been unnecessary;
2862 (*) loads may be done speculatively, leading to the result having been fetched
2863 at the wrong time in the expected sequence of events;
2865 (*) the order of the memory accesses may be rearranged to promote better use
2866 of the CPU buses and caches;
2868 (*) loads and stores may be combined to improve performance when talking to
2869 memory or I/O hardware that can do batched accesses of adjacent locations,
2870 thus cutting down on transaction setup costs (memory and PCI devices may
2871 both be able to do this); and
2873 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2874 mechanisms may alleviate this - once the store has actually hit the cache
2875 - there's no guarantee that the coherency management will be propagated in
2876 order to other CPUs.
2878 So what another CPU, say, might actually observe from the above piece of code
2881 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2883 (Where "LOAD {*C,*D}" is a combined load)
2886 However, it is guaranteed that a CPU will be self-consistent: it will see its
2887 _own_ accesses appear to be correctly ordered, without the need for a memory
2888 barrier. For instance with the following code:
2897 and assuming no intervention by an external influence, it can be assumed that
2898 the final result will appear to be:
2900 U == the original value of *A
2905 The code above may cause the CPU to generate the full sequence of memory
2908 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2910 in that order, but, without intervention, the sequence may have almost any
2911 combination of elements combined or discarded, provided the program's view
2912 of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2913 are -not- optional in the above example, as there are architectures
2914 where a given CPU might reorder successive loads to the same location.
2915 On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
2916 necessary to prevent this, for example, on Itanium the volatile casts
2917 used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
2918 and st.rel instructions (respectively) that prevent such reordering.
2920 The compiler may also combine, discard or defer elements of the sequence before
2921 the CPU even sees them.
2932 since, without either a write barrier or an WRITE_ONCE(), it can be
2933 assumed that the effect of the storage of V to *A is lost. Similarly:
2938 may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
2944 and the LOAD operation never appear outside of the CPU.
2947 AND THEN THERE'S THE ALPHA
2948 --------------------------
2950 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2951 some versions of the Alpha CPU have a split data cache, permitting them to have
2952 two semantically-related cache lines updated at separate times. This is where
2953 the data dependency barrier really becomes necessary as this synchronises both
2954 caches with the memory coherence system, thus making it seem like pointer
2955 changes vs new data occur in the right order.
2957 The Alpha defines the Linux kernel's memory barrier model.
2959 See the subsection on "Cache Coherency" above.
2969 Memory barriers can be used to implement circular buffering without the need
2970 of a lock to serialise the producer with the consumer. See:
2972 Documentation/circular-buffers.txt
2981 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2983 Chapter 5.2: Physical Address Space Characteristics
2984 Chapter 5.4: Caches and Write Buffers
2985 Chapter 5.5: Data Sharing
2986 Chapter 5.6: Read/Write Ordering
2988 AMD64 Architecture Programmer's Manual Volume 2: System Programming
2989 Chapter 7.1: Memory-Access Ordering
2990 Chapter 7.4: Buffering and Combining Memory Writes
2992 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2993 System Programming Guide
2994 Chapter 7.1: Locked Atomic Operations
2995 Chapter 7.2: Memory Ordering
2996 Chapter 7.4: Serializing Instructions
2998 The SPARC Architecture Manual, Version 9
2999 Chapter 8: Memory Models
3000 Appendix D: Formal Specification of the Memory Models
3001 Appendix J: Programming with the Memory Models
3003 UltraSPARC Programmer Reference Manual
3004 Chapter 5: Memory Accesses and Cacheability
3005 Chapter 15: Sparc-V9 Memory Models
3007 UltraSPARC III Cu User's Manual
3008 Chapter 9: Memory Models
3010 UltraSPARC IIIi Processor User's Manual
3011 Chapter 8: Memory Models
3013 UltraSPARC Architecture 2005
3015 Appendix D: Formal Specifications of the Memory Models
3017 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3018 Chapter 8: Memory Models
3019 Appendix F: Caches and Cache Coherency
3021 Solaris Internals, Core Kernel Architecture, p63-68:
3022 Chapter 3.3: Hardware Considerations for Locks and
3025 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3026 for Kernel Programmers:
3027 Chapter 13: Other Memory Models
3029 Intel Itanium Architecture Software Developer's Manual: Volume 1:
3030 Section 2.6: Speculation
3031 Section 4.4: Memory Access
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