arch/arm/boot/dts/armada-xp-gp.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP development board
   3  * (DB-MV784MP-GP)
   4  *
   5  * Copyright (C) 2013-2014 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  *
  15  * Note: this Device Tree assumes that the bootloader has remapped the
  16  * internal registers to 0xf1000000 (instead of the default
  17  * 0xd0000000). The 0xf1000000 is the default used by the recent,
  18  * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
  19  * boards were delivered with an older version of the bootloader that
  20  * left internal registers mapped at 0xd0000000. If you are in this
  21  * situation, you should either update your bootloader (preferred
  22  * solution) or the below Device Tree should be adjusted.
  23  */
  24
  25 /dts-v1/;
  26 #include <dt-bindings/gpio/gpio.h>
  27 #include "armada-xp-mv78460.dtsi"
  28
  29 / {
  30         model = "Marvell Armada XP Development Board DB-MV784MP-GP";
  31         compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  32
  33         chosen {
  34                 bootargs = "console=ttyS0,115200 earlyprintk";
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 /*
  40                  * 8 GB of plug-in RAM modules by default.The amount
  41                  * of memory available can be changed by the
  42                  * bootloader according the size of the module
  43                  * actually plugged. However, memory between
  44                  * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
  45                  * the address range used for I/O (internal registers,
  46                  * MBus windows).
  47                  */
  48                 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
  49                       <0x00000001 0x00000000 0x00000001 0x00000000>;
  50         };
  51
  52         cpus {
  53                 pm_pic {
  54                         ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
  55                                      <&gpio0 17 GPIO_ACTIVE_LOW>,
  56                                      <&gpio0 18 GPIO_ACTIVE_LOW>;
  57                 };
  58         };
  59
  60         soc {
  61                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  62                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  63                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
  64
  65                 devbus-bootcs {
  66                         status = "okay";
  67
  68                         /* Device Bus parameters are required */
  69
  70                         /* Read parameters */
  71                         devbus,bus-width    = <16>;
  72                         devbus,turn-off-ps  = <60000>;
  73                         devbus,badr-skew-ps = <0>;
  74                         devbus,acc-first-ps = <124000>;
  75                         devbus,acc-next-ps  = <248000>;
  76                         devbus,rd-setup-ps  = <0>;
  77                         devbus,rd-hold-ps   = <0>;
  78
  79                         /* Write parameters */
  80                         devbus,sync-enable = <0>;
  81                         devbus,wr-high-ps  = <60000>;
  82                         devbus,wr-low-ps   = <60000>;
  83                         devbus,ale-wr-ps   = <60000>;
  84
  85                         /* NOR 16 MiB */
  86                         nor@0 {
  87                                 compatible = "cfi-flash";
  88                                 reg = <0 0x1000000>;
  89                                 bank-width = <2>;
  90                         };
  91                 };
  92
  93                 pcie-controller {
  94                         status = "okay";
  95
  96                         /*
  97                          * The 3 slots are physically present as
  98                          * standard PCIe slots on the board.
  99                          */
 100                         pcie@1,0 {
 101                                 /* Port 0, Lane 0 */
 102                                 status = "okay";
 103                         };
 104                         pcie@9,0 {
 105                                 /* Port 2, Lane 0 */
 106                                 status = "okay";
 107                         };
 108                         pcie@10,0 {
 109                                 /* Port 3, Lane 0 */
 110                                 status = "okay";
 111                         };
 112                 };
 113
 114                 internal-regs {
 115                         serial@12000 {
 116                                 status = "okay";
 117                         };
 118                         serial@12100 {
 119                                 status = "okay";
 120                         };
 121                         serial@12200 {
 122                                 status = "okay";
 123                         };
 124                         serial@12300 {
 125                                 status = "okay";
 126                         };
 127                         pinctrl {
 128                                 pinctrl-0 = <&pic_pins>;
 129                                 pinctrl-names = "default";
 130                                 pic_pins: pic-pins-0 {
 131                                         marvell,pins = "mpp16", "mpp17",
 132                                                        "mpp18";
 133                                         marvell,function = "gpio";
 134                                 };
 135                         };
 136                         sata@a0000 {
 137                                 nr-ports = <2>;
 138                                 status = "okay";
 139                         };
 140
 141                         mdio {
 142                                 phy0: ethernet-phy@0 {
 143                                         reg = <16>;
 144                                 };
 145
 146                                 phy1: ethernet-phy@1 {
 147                                         reg = <17>;
 148                                 };
 149
 150                                 phy2: ethernet-phy@2 {
 151                                         reg = <18>;
 152                                 };
 153
 154                                 phy3: ethernet-phy@3 {
 155                                         reg = <19>;
 156                                 };
 157                         };
 158
 159                         ethernet@70000 {
 160                                 status = "okay";
 161                                 phy = <&phy0>;
 162                                 phy-mode = "qsgmii";
 163                         };
 164                         ethernet@74000 {
 165                                 status = "okay";
 166                                 phy = <&phy1>;
 167                                 phy-mode = "qsgmii";
 168                         };
 169                         ethernet@30000 {
 170                                 status = "okay";
 171                                 phy = <&phy2>;
 172                                 phy-mode = "qsgmii";
 173                         };
 174                         ethernet@34000 {
 175                                 status = "okay";
 176                                 phy = <&phy3>;
 177                                 phy-mode = "qsgmii";
 178                         };
 179
 180                         /* Front-side USB slot */
 181                         usb@50000 {
 182                                 status = "okay";
 183                         };
 184
 185                         /* Back-side USB slot */
 186                         usb@51000 {
 187                                 status = "okay";
 188                         };
 189
 190                         spi0: spi@10600 {
 191                                 status = "okay";
 192
 193                                 spi-flash@0 {
 194                                         #address-cells = <1>;
 195                                         #size-cells = <1>;
 196                                         compatible = "n25q128a13";
 197                                         reg = <0>; /* Chip select 0 */
 198                                         spi-max-frequency = <108000000>;
 199                                 };
 200                         };
 201
 202                         nand@d0000 {
 203                                 status = "okay";
 204                                 num-cs = <1>;
 205                                 marvell,nand-keep-config;
 206                                 marvell,nand-enable-arbiter;
 207                                 nand-on-flash-bbt;
 208                         };
 209                 };
 210         };
 211 };