1 /include/ "skeleton.dtsi"
3 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
6 compatible = "marvell,dove";
7 model = "Marvell Armada 88AP510 SoC";
20 compatible = "marvell,pj4a", "marvell,sheeva-v7";
22 next-level-cache = <&l2>;
28 compatible = "marvell,tauros2-cache";
29 marvell,tauros2-cache-features = <0>;
33 compatible = "marvell,dove-mbus", "marvell,mbus", "simple-bus";
36 controller = <&mbusc>;
37 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256M MEM space */
38 pcie-io-aperture = <0xf2000000 0x00200000>; /* 2M I/O space */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x0100000 /* MBUS regs 1M */
41 MBUS_ID(0xf0, 0x02) 0 0xf1800000 0x1000000 /* AXI regs 16M */
42 MBUS_ID(0x01, 0xfd) 0 0xf8000000 0x8000000 /* BootROM 128M */
43 MBUS_ID(0x03, 0x01) 0 0xc8000000 0x0100000 /* CESA SRAM 1M */
44 MBUS_ID(0x0d, 0x00) 0 0xf0000000 0x0100000>; /* PMU SRAM 1M */
48 compatible = "simple-bus";
51 interrupt-parent = <&intc>;
53 ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
54 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
55 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
56 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
57 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
58 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
59 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
60 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
62 mbusc: mbus-ctrl@20000 {
63 compatible = "marvell,mbus-controller";
64 reg = <0x20000 0x80>, <0x800100 0x8>;
68 compatible = "marvell,orion-timer";
70 interrupt-parent = <&bridge_intc>;
71 interrupts = <1>, <2>;
72 clocks = <&core_clk 0>;
75 intc: main-interrupt-ctrl@20200 {
76 compatible = "marvell,orion-intc";
78 #interrupt-cells = <1>;
79 reg = <0x20200 0x10>, <0x20210 0x10>;
82 bridge_intc: bridge-interrupt-ctrl@20110 {
83 compatible = "marvell,orion-bridge-intc";
85 #interrupt-cells = <1>;
88 marvell,#interrupts = <5>;
91 core_clk: core-clocks@d0214 {
92 compatible = "marvell,dove-core-clock";
97 gate_clk: clock-gating-ctrl@d0038 {
98 compatible = "marvell,dove-gating-clock";
100 clocks = <&core_clk 0>;
104 thermal: thermal-diode@d001c {
105 compatible = "marvell,dove-thermal";
106 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
109 uart0: serial@12000 {
110 compatible = "ns16550a";
111 reg = <0x12000 0x100>;
114 clocks = <&core_clk 0>;
118 uart1: serial@12100 {
119 compatible = "ns16550a";
120 reg = <0x12100 0x100>;
123 clocks = <&core_clk 0>;
124 pinctrl-0 = <&pmx_uart1>;
125 pinctrl-names = "default";
129 uart2: serial@12200 {
130 compatible = "ns16550a";
131 reg = <0x12000 0x100>;
134 clocks = <&core_clk 0>;
138 uart3: serial@12300 {
139 compatible = "ns16550a";
140 reg = <0x12100 0x100>;
143 clocks = <&core_clk 0>;
147 gpio0: gpio-ctrl@d0400 {
148 compatible = "marvell,orion-gpio";
151 reg = <0xd0400 0x20>;
153 interrupt-controller;
154 #interrupt-cells = <2>;
155 interrupts = <12>, <13>, <14>, <60>;
158 gpio1: gpio-ctrl@d0420 {
159 compatible = "marvell,orion-gpio";
162 reg = <0xd0420 0x20>;
164 interrupt-controller;
165 #interrupt-cells = <2>;
169 gpio2: gpio-ctrl@e8400 {
170 compatible = "marvell,orion-gpio";
173 reg = <0xe8400 0x0c>;
177 pinctrl: pin-ctrl@d0200 {
178 compatible = "marvell,dove-pinctrl";
179 reg = <0xd0200 0x10>;
180 clocks = <&gate_clk 22>;
182 pmx_gpio_0: pmx-gpio-0 {
183 marvell,pins = "mpp0";
184 marvell,function = "gpio";
187 pmx_gpio_1: pmx-gpio-1 {
188 marvell,pins = "mpp1";
189 marvell,function = "gpio";
192 pmx_gpio_2: pmx-gpio-2 {
193 marvell,pins = "mpp2";
194 marvell,function = "gpio";
197 pmx_gpio_3: pmx-gpio-3 {
198 marvell,pins = "mpp3";
199 marvell,function = "gpio";
202 pmx_gpio_4: pmx-gpio-4 {
203 marvell,pins = "mpp4";
204 marvell,function = "gpio";
207 pmx_gpio_5: pmx-gpio-5 {
208 marvell,pins = "mpp5";
209 marvell,function = "gpio";
212 pmx_gpio_6: pmx-gpio-6 {
213 marvell,pins = "mpp6";
214 marvell,function = "gpio";
217 pmx_gpio_7: pmx-gpio-7 {
218 marvell,pins = "mpp7";
219 marvell,function = "gpio";
222 pmx_gpio_8: pmx-gpio-8 {
223 marvell,pins = "mpp8";
224 marvell,function = "gpio";
227 pmx_gpio_9: pmx-gpio-9 {
228 marvell,pins = "mpp9";
229 marvell,function = "gpio";
232 pmx_gpio_10: pmx-gpio-10 {
233 marvell,pins = "mpp10";
234 marvell,function = "gpio";
237 pmx_gpio_11: pmx-gpio-11 {
238 marvell,pins = "mpp11";
239 marvell,function = "gpio";
242 pmx_gpio_12: pmx-gpio-12 {
243 marvell,pins = "mpp12";
244 marvell,function = "gpio";
247 pmx_gpio_13: pmx-gpio-13 {
248 marvell,pins = "mpp13";
249 marvell,function = "gpio";
252 pmx_gpio_14: pmx-gpio-14 {
253 marvell,pins = "mpp14";
254 marvell,function = "gpio";
257 pmx_gpio_15: pmx-gpio-15 {
258 marvell,pins = "mpp15";
259 marvell,function = "gpio";
262 pmx_gpio_16: pmx-gpio-16 {
263 marvell,pins = "mpp16";
264 marvell,function = "gpio";
267 pmx_gpio_17: pmx-gpio-17 {
268 marvell,pins = "mpp17";
269 marvell,function = "gpio";
272 pmx_gpio_18: pmx-gpio-18 {
273 marvell,pins = "mpp18";
274 marvell,function = "gpio";
277 pmx_gpio_19: pmx-gpio-19 {
278 marvell,pins = "mpp19";
279 marvell,function = "gpio";
282 pmx_gpio_20: pmx-gpio-20 {
283 marvell,pins = "mpp20";
284 marvell,function = "gpio";
287 pmx_gpio_21: pmx-gpio-21 {
288 marvell,pins = "mpp21";
289 marvell,function = "gpio";
292 pmx_camera: pmx-camera {
293 marvell,pins = "mpp_camera";
294 marvell,function = "camera";
297 pmx_camera_gpio: pmx-camera-gpio {
298 marvell,pins = "mpp_camera";
299 marvell,function = "gpio";
302 pmx_sdio0: pmx-sdio0 {
303 marvell,pins = "mpp_sdio0";
304 marvell,function = "sdio0";
307 pmx_sdio0_gpio: pmx-sdio0-gpio {
308 marvell,pins = "mpp_sdio0";
309 marvell,function = "gpio";
312 pmx_sdio1: pmx-sdio1 {
313 marvell,pins = "mpp_sdio1";
314 marvell,function = "sdio1";
317 pmx_sdio1_gpio: pmx-sdio1-gpio {
318 marvell,pins = "mpp_sdio1";
319 marvell,function = "gpio";
322 pmx_audio1_gpio: pmx-audio1-gpio {
323 marvell,pins = "mpp_audio1";
324 marvell,function = "gpio";
328 marvell,pins = "mpp_spi0";
329 marvell,function = "spi0";
332 pmx_spi0_gpio: pmx-spi0-gpio {
333 marvell,pins = "mpp_spi0";
334 marvell,function = "gpio";
337 pmx_uart1: pmx-uart1 {
338 marvell,pins = "mpp_uart1";
339 marvell,function = "uart1";
342 pmx_uart1_gpio: pmx-uart1-gpio {
343 marvell,pins = "mpp_uart1";
344 marvell,function = "gpio";
348 marvell,pins = "mpp_nand";
349 marvell,function = "nand";
352 pmx_nand_gpo: pmx-nand-gpo {
353 marvell,pins = "mpp_nand";
354 marvell,function = "gpo";
358 spi0: spi-ctrl@10600 {
359 compatible = "marvell,orion-spi";
360 #address-cells = <1>;
364 reg = <0x10600 0x28>;
365 clocks = <&core_clk 0>;
366 pinctrl-0 = <&pmx_spi0>;
367 pinctrl-names = "default";
371 spi1: spi-ctrl@14600 {
372 compatible = "marvell,orion-spi";
373 #address-cells = <1>;
377 reg = <0x14600 0x28>;
378 clocks = <&core_clk 0>;
382 i2c0: i2c-ctrl@11000 {
383 compatible = "marvell,mv64xxx-i2c";
384 reg = <0x11000 0x20>;
385 #address-cells = <1>;
388 clock-frequency = <400000>;
390 clocks = <&core_clk 0>;
394 ehci0: usb-host@50000 {
395 compatible = "marvell,orion-ehci";
396 reg = <0x50000 0x1000>;
398 clocks = <&gate_clk 0>;
402 ehci1: usb-host@51000 {
403 compatible = "marvell,orion-ehci";
404 reg = <0x51000 0x1000>;
406 clocks = <&gate_clk 1>;
410 sdio0: sdio-host@92000 {
411 compatible = "marvell,dove-sdhci";
412 reg = <0x92000 0x100>;
413 interrupts = <35>, <37>;
414 clocks = <&gate_clk 8>;
415 pinctrl-0 = <&pmx_sdio0>;
416 pinctrl-names = "default";
420 sdio1: sdio-host@90000 {
421 compatible = "marvell,dove-sdhci";
422 reg = <0x90000 0x100>;
423 interrupts = <36>, <38>;
424 clocks = <&gate_clk 9>;
425 pinctrl-0 = <&pmx_sdio1>;
426 pinctrl-names = "default";
430 sata0: sata-host@a0000 {
431 compatible = "marvell,orion-sata";
432 reg = <0xa0000 0x2400>;
434 clocks = <&gate_clk 3>;
439 rtc: real-time-clock@d8500 {
440 compatible = "marvell,orion-rtc";
441 reg = <0xd8500 0x20>;
444 crypto: crypto-engine@30000 {
445 compatible = "marvell,orion-crypto";
446 reg = <0x30000 0x10000>,
448 reg-names = "regs", "sram";
450 clocks = <&gate_clk 15>;
454 xor0: dma-engine@60800 {
455 compatible = "marvell,orion-xor";
458 clocks = <&gate_clk 23>;
475 xor1: dma-engine@60900 {
476 compatible = "marvell,orion-xor";
479 clocks = <&gate_clk 24>;
496 mdio: mdio-bus@72004 {
497 compatible = "marvell,orion-mdio";
498 #address-cells = <1>;
500 reg = <0x72004 0x84>;
502 clocks = <&gate_clk 2>;
505 ethphy: ethernet-phy {
506 device-type = "ethernet-phy";
507 /* set phy address in board file */
511 eth: ethernet-controller@72000 {
512 compatible = "marvell,orion-eth";
513 #address-cells = <1>;
515 reg = <0x72000 0x4000>;
516 clocks = <&gate_clk 2>;
517 marvell,tx-checksum-limit = <1600>;
521 device_type = "network";
522 compatible = "marvell,orion-eth-port";
525 /* overwrite MAC address in bootloader */
526 local-mac-address = [00 00 00 00 00 00];
527 phy-handle = <ðphy>;