arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #include "skeleton.dtsi"
  14
  15 #define MAX_SOURCES 400
  16 #define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
  17
  18 / {
  19         #address-cells = <1>;
  20         #size-cells = <1>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&gic>;
  24
  25         aliases {
  26                 i2c0 = &i2c1;
  27                 i2c1 = &i2c2;
  28                 i2c2 = &i2c3;
  29                 i2c3 = &i2c4;
  30                 i2c4 = &i2c5;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 serial6 = &uart7;
  38                 serial7 = &uart8;
  39                 serial8 = &uart9;
  40                 serial9 = &uart10;
  41                 ethernet0 = &cpsw_emac0;
  42                 ethernet1 = &cpsw_emac1;
  43                 d_can0 = &dcan1;
  44                 d_can1 = &dcan2;
  45         };
  46
  47         timer {
  48                 compatible = "arm,armv7-timer";
  49                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  53         };
  54
  55         gic: interrupt-controller@48211000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 interrupt-controller;
  58                 #interrupt-cells = <3>;
  59                 arm,routable-irqs = <192>;
  60                 reg = <0x48211000 0x1000>,
  61                       <0x48212000 0x1000>,
  62                       <0x48214000 0x2000>,
  63                       <0x48216000 0x2000>;
  64                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  65         };
  66
  67         /*
  68          * The soc node represents the soc top level view. It is used for IPs
  69          * that are not memory mapped in the MPU view or for the MPU itself.
  70          */
  71         soc {
  72                 compatible = "ti,omap-infra";
  73                 mpu {
  74                         compatible = "ti,omap5-mpu";
  75                         ti,hwmods = "mpu";
  76                 };
  77         };
  78
  79         /*
  80          * XXX: Use a flat representation of the SOC interconnect.
  81          * The real OMAP interconnect network is quite complex.
  82          * Since it will not bring real advantage to represent that in DT for
  83          * the moment, just use a fake OCP bus entry to represent the whole bus
  84          * hierarchy.
  85          */
  86         ocp {
  87                 compatible = "ti,dra7-l3-noc", "simple-bus";
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90                 ranges;
  91                 ti,hwmods = "l3_main_1", "l3_main_2";
  92                 reg = <0x44000000 0x1000000>,
  93                       <0x45000000 0x1000>;
  94                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  95                              <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
  96
  97                 prm: prm@4ae06000 {
  98                         compatible = "ti,dra7-prm";
  99                         reg = <0x4ae06000 0x3000>;
 100                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 101
 102                         prm_clocks: clocks {
 103                                 #address-cells = <1>;
 104                                 #size-cells = <0>;
 105                         };
 106
 107                         prm_clockdomains: clockdomains {
 108                         };
 109                 };
 110
 111                 axi@0 {
 112                         compatible = "simple-bus";
 113                         #size-cells = <1>;
 114                         #address-cells = <1>;
 115                         ranges = <0x51000000 0x51000000 0x3000
 116                                   0x0        0x20000000 0x10000000>;
 117                         pcie@51000000 {
 118                                 compatible = "ti,dra7-pcie";
 119                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 120                                 reg-names = "rc_dbics", "ti_conf", "config";
 121                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 122                                 #address-cells = <3>;
 123                                 #size-cells = <2>;
 124                                 device_type = "pci";
 125                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 126                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 127                                 #interrupt-cells = <1>;
 128                                 num-lanes = <1>;
 129                                 ti,hwmods = "pcie1";
 130                                 phys = <&pcie1_phy>;
 131                                 phy-names = "pcie-phy0";
 132                                 interrupt-map-mask = <0 0 0 7>;
 133                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 134                                                 <0 0 0 2 &pcie1_intc 2>,
 135                                                 <0 0 0 3 &pcie1_intc 3>,
 136                                                 <0 0 0 4 &pcie1_intc 4>;
 137                                 pcie1_intc: interrupt-controller {
 138                                         interrupt-controller;
 139                                         #address-cells = <0>;
 140                                         #interrupt-cells = <1>;
 141                                 };
 142                         };
 143                 };
 144
 145                 axi@1 {
 146                         compatible = "simple-bus";
 147                         #size-cells = <1>;
 148                         #address-cells = <1>;
 149                         ranges = <0x51800000 0x51800000 0x3000
 150                                   0x0        0x30000000 0x10000000>;
 151                         status = "disabled";
 152                         pcie@51000000 {
 153                                 compatible = "ti,dra7-pcie";
 154                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 155                                 reg-names = "rc_dbics", "ti_conf", "config";
 156                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 157                                 #address-cells = <3>;
 158                                 #size-cells = <2>;
 159                                 device_type = "pci";
 160                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 161                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 162                                 #interrupt-cells = <1>;
 163                                 num-lanes = <1>;
 164                                 ti,hwmods = "pcie2";
 165                                 phys = <&pcie2_phy>;
 166                                 phy-names = "pcie-phy0";
 167                                 interrupt-map-mask = <0 0 0 7>;
 168                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 169                                                 <0 0 0 2 &pcie2_intc 2>,
 170                                                 <0 0 0 3 &pcie2_intc 3>,
 171                                                 <0 0 0 4 &pcie2_intc 4>;
 172                                 pcie2_intc: interrupt-controller {
 173                                         interrupt-controller;
 174                                         #address-cells = <0>;
 175                                         #interrupt-cells = <1>;
 176                                 };
 177                         };
 178                 };
 179
 180                 bandgap: bandgap@4a0021e0 {
 181                         reg = <0x4a0021e0 0xc
 182                                 0x4a00232c 0xc
 183                                 0x4a002380 0x2c
 184                                 0x4a0023C0 0x3c
 185                                 0x4a002564 0x8
 186                                 0x4a002574 0x50>;
 187                                 compatible = "ti,dra752-bandgap";
 188                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 189                                 #thermal-sensor-cells = <1>;
 190                 };
 191
 192                 cm_core_aon: cm_core_aon@4a005000 {
 193                         compatible = "ti,dra7-cm-core-aon";
 194                         reg = <0x4a005000 0x2000>;
 195
 196                         cm_core_aon_clocks: clocks {
 197                                 #address-cells = <1>;
 198                                 #size-cells = <0>;
 199                         };
 200
 201                         cm_core_aon_clockdomains: clockdomains {
 202                         };
 203                 };
 204
 205                 cm_core: cm_core@4a008000 {
 206                         compatible = "ti,dra7-cm-core";
 207                         reg = <0x4a008000 0x3000>;
 208
 209                         cm_core_clocks: clocks {
 210                                 #address-cells = <1>;
 211                                 #size-cells = <0>;
 212                         };
 213
 214                         cm_core_clockdomains: clockdomains {
 215                         };
 216                 };
 217
 218                 counter32k: counter@4ae04000 {
 219                         compatible = "ti,omap-counter32k";
 220                         reg = <0x4ae04000 0x40>;
 221                         ti,hwmods = "counter_32k";
 222                 };
 223
 224                 dra7_ctrl_core: ctrl_core@4a002000 {
 225                         compatible = "syscon";
 226                         reg = <0x4a002000 0x6d0>;
 227                 };
 228
 229                 dra7_ctrl_general: tisyscon@4a002e00 {
 230                         compatible = "syscon";
 231                         reg = <0x4a002e00 0x7c>;
 232                 };
 233
 234                 pbias_regulator: pbias_regulator {
 235                         compatible = "ti,pbias-omap";
 236                         reg = <0 0x4>;
 237                         syscon = <&dra7_ctrl_general>;
 238                         pbias_mmc_reg: pbias_mmc_omap5 {
 239                                 regulator-name = "pbias_mmc_omap5";
 240                                 regulator-min-microvolt = <1800000>;
 241                                 regulator-max-microvolt = <3000000>;
 242                         };
 243                 };
 244
 245                 dra7_pmx_core: pinmux@4a003400 {
 246                         compatible = "ti,dra7-padconf", "pinctrl-single";
 247                         reg = <0x4a003400 0x0464>;
 248                         #address-cells = <1>;
 249                         #size-cells = <0>;
 250                         #interrupt-cells = <1>;
 251                         interrupt-controller;
 252                         pinctrl-single,register-width = <32>;
 253                         pinctrl-single,function-mask = <0x3fffffff>;
 254                 };
 255
 256                 sdma: dma-controller@4a056000 {
 257                         compatible = "ti,omap4430-sdma";
 258                         reg = <0x4a056000 0x1000>;
 259                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 260                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 261                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 262                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 263                         #dma-cells = <1>;
 264                         dma-channels = <32>;
 265                         dma-requests = <127>;
 266                 };
 267
 268                 gpio1: gpio@4ae10000 {
 269                         compatible = "ti,omap4-gpio";
 270                         reg = <0x4ae10000 0x200>;
 271                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 272                         ti,hwmods = "gpio1";
 273                         gpio-controller;
 274                         #gpio-cells = <2>;
 275                         interrupt-controller;
 276                         #interrupt-cells = <2>;
 277                 };
 278
 279                 gpio2: gpio@48055000 {
 280                         compatible = "ti,omap4-gpio";
 281                         reg = <0x48055000 0x200>;
 282                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 283                         ti,hwmods = "gpio2";
 284                         gpio-controller;
 285                         #gpio-cells = <2>;
 286                         interrupt-controller;
 287                         #interrupt-cells = <2>;
 288                 };
 289
 290                 gpio3: gpio@48057000 {
 291                         compatible = "ti,omap4-gpio";
 292                         reg = <0x48057000 0x200>;
 293                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 294                         ti,hwmods = "gpio3";
 295                         gpio-controller;
 296                         #gpio-cells = <2>;
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300
 301                 gpio4: gpio@48059000 {
 302                         compatible = "ti,omap4-gpio";
 303                         reg = <0x48059000 0x200>;
 304                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 305                         ti,hwmods = "gpio4";
 306                         gpio-controller;
 307                         #gpio-cells = <2>;
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                 };
 311
 312                 gpio5: gpio@4805b000 {
 313                         compatible = "ti,omap4-gpio";
 314                         reg = <0x4805b000 0x200>;
 315                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 316                         ti,hwmods = "gpio5";
 317                         gpio-controller;
 318                         #gpio-cells = <2>;
 319                         interrupt-controller;
 320                         #interrupt-cells = <2>;
 321                 };
 322
 323                 gpio6: gpio@4805d000 {
 324                         compatible = "ti,omap4-gpio";
 325                         reg = <0x4805d000 0x200>;
 326                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 327                         ti,hwmods = "gpio6";
 328                         gpio-controller;
 329                         #gpio-cells = <2>;
 330                         interrupt-controller;
 331                         #interrupt-cells = <2>;
 332                 };
 333
 334                 gpio7: gpio@48051000 {
 335                         compatible = "ti,omap4-gpio";
 336                         reg = <0x48051000 0x200>;
 337                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 338                         ti,hwmods = "gpio7";
 339                         gpio-controller;
 340                         #gpio-cells = <2>;
 341                         interrupt-controller;
 342                         #interrupt-cells = <2>;
 343                 };
 344
 345                 gpio8: gpio@48053000 {
 346                         compatible = "ti,omap4-gpio";
 347                         reg = <0x48053000 0x200>;
 348                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 349                         ti,hwmods = "gpio8";
 350                         gpio-controller;
 351                         #gpio-cells = <2>;
 352                         interrupt-controller;
 353                         #interrupt-cells = <2>;
 354                 };
 355
 356                 uart1: serial@4806a000 {
 357                         compatible = "ti,omap4-uart";
 358                         reg = <0x4806a000 0x100>;
 359                         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 360                         ti,hwmods = "uart1";
 361                         clock-frequency = <48000000>;
 362                         status = "disabled";
 363                         dmas = <&sdma 49>, <&sdma 50>;
 364                         dma-names = "tx", "rx";
 365                 };
 366
 367                 uart2: serial@4806c000 {
 368                         compatible = "ti,omap4-uart";
 369                         reg = <0x4806c000 0x100>;
 370                         interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 371                         ti,hwmods = "uart2";
 372                         clock-frequency = <48000000>;
 373                         status = "disabled";
 374                         dmas = <&sdma 51>, <&sdma 52>;
 375                         dma-names = "tx", "rx";
 376                 };
 377
 378                 uart3: serial@48020000 {
 379                         compatible = "ti,omap4-uart";
 380                         reg = <0x48020000 0x100>;
 381                         interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 382                         ti,hwmods = "uart3";
 383                         clock-frequency = <48000000>;
 384                         status = "disabled";
 385                         dmas = <&sdma 53>, <&sdma 54>;
 386                         dma-names = "tx", "rx";
 387                 };
 388
 389                 uart4: serial@4806e000 {
 390                         compatible = "ti,omap4-uart";
 391                         reg = <0x4806e000 0x100>;
 392                         interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 393                         ti,hwmods = "uart4";
 394                         clock-frequency = <48000000>;
 395                         status = "disabled";
 396                         dmas = <&sdma 55>, <&sdma 56>;
 397                         dma-names = "tx", "rx";
 398                 };
 399
 400                 uart5: serial@48066000 {
 401                         compatible = "ti,omap4-uart";
 402                         reg = <0x48066000 0x100>;
 403                         interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 404                         ti,hwmods = "uart5";
 405                         clock-frequency = <48000000>;
 406                         status = "disabled";
 407                         dmas = <&sdma 63>, <&sdma 64>;
 408                         dma-names = "tx", "rx";
 409                 };
 410
 411                 uart6: serial@48068000 {
 412                         compatible = "ti,omap4-uart";
 413                         reg = <0x48068000 0x100>;
 414                         interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 415                         ti,hwmods = "uart6";
 416                         clock-frequency = <48000000>;
 417                         status = "disabled";
 418                         dmas = <&sdma 79>, <&sdma 80>;
 419                         dma-names = "tx", "rx";
 420                 };
 421
 422                 uart7: serial@48420000 {
 423                         compatible = "ti,omap4-uart";
 424                         reg = <0x48420000 0x100>;
 425                         interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 426                         ti,hwmods = "uart7";
 427                         clock-frequency = <48000000>;
 428                         status = "disabled";
 429                 };
 430
 431                 uart8: serial@48422000 {
 432                         compatible = "ti,omap4-uart";
 433                         reg = <0x48422000 0x100>;
 434                         interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 435                         ti,hwmods = "uart8";
 436                         clock-frequency = <48000000>;
 437                         status = "disabled";
 438                 };
 439
 440                 uart9: serial@48424000 {
 441                         compatible = "ti,omap4-uart";
 442                         reg = <0x48424000 0x100>;
 443                         interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 444                         ti,hwmods = "uart9";
 445                         clock-frequency = <48000000>;
 446                         status = "disabled";
 447                 };
 448
 449                 uart10: serial@4ae2b000 {
 450                         compatible = "ti,omap4-uart";
 451                         reg = <0x4ae2b000 0x100>;
 452                         interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 453                         ti,hwmods = "uart10";
 454                         clock-frequency = <48000000>;
 455                         status = "disabled";
 456                 };
 457
 458                 mailbox1: mailbox@4a0f4000 {
 459                         compatible = "ti,omap4-mailbox";
 460                         reg = <0x4a0f4000 0x200>;
 461                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 462                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 463                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 464                         ti,hwmods = "mailbox1";
 465                         #mbox-cells = <1>;
 466                         ti,mbox-num-users = <3>;
 467                         ti,mbox-num-fifos = <8>;
 468                         status = "disabled";
 469                 };
 470
 471                 mailbox2: mailbox@4883a000 {
 472                         compatible = "ti,omap4-mailbox";
 473                         reg = <0x4883a000 0x200>;
 474                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 475                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 476                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 477                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 478                         ti,hwmods = "mailbox2";
 479                         #mbox-cells = <1>;
 480                         ti,mbox-num-users = <4>;
 481                         ti,mbox-num-fifos = <12>;
 482                         status = "disabled";
 483                 };
 484
 485                 mailbox3: mailbox@4883c000 {
 486                         compatible = "ti,omap4-mailbox";
 487                         reg = <0x4883c000 0x200>;
 488                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 489                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 490                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 491                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 492                         ti,hwmods = "mailbox3";
 493                         #mbox-cells = <1>;
 494                         ti,mbox-num-users = <4>;
 495                         ti,mbox-num-fifos = <12>;
 496                         status = "disabled";
 497                 };
 498
 499                 mailbox4: mailbox@4883e000 {
 500                         compatible = "ti,omap4-mailbox";
 501                         reg = <0x4883e000 0x200>;
 502                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 503                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 504                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 506                         ti,hwmods = "mailbox4";
 507                         #mbox-cells = <1>;
 508                         ti,mbox-num-users = <4>;
 509                         ti,mbox-num-fifos = <12>;
 510                         status = "disabled";
 511                 };
 512
 513                 mailbox5: mailbox@48840000 {
 514                         compatible = "ti,omap4-mailbox";
 515                         reg = <0x48840000 0x200>;
 516                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 517                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 518                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 519                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 520                         ti,hwmods = "mailbox5";
 521                         #mbox-cells = <1>;
 522                         ti,mbox-num-users = <4>;
 523                         ti,mbox-num-fifos = <12>;
 524                         status = "disabled";
 525                 };
 526
 527                 mailbox6: mailbox@48842000 {
 528                         compatible = "ti,omap4-mailbox";
 529                         reg = <0x48842000 0x200>;
 530                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 531                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 532                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 533                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 534                         ti,hwmods = "mailbox6";
 535                         #mbox-cells = <1>;
 536                         ti,mbox-num-users = <4>;
 537                         ti,mbox-num-fifos = <12>;
 538                         status = "disabled";
 539                 };
 540
 541                 mailbox7: mailbox@48844000 {
 542                         compatible = "ti,omap4-mailbox";
 543                         reg = <0x48844000 0x200>;
 544                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 545                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 546                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 547                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 548                         ti,hwmods = "mailbox7";
 549                         #mbox-cells = <1>;
 550                         ti,mbox-num-users = <4>;
 551                         ti,mbox-num-fifos = <12>;
 552                         status = "disabled";
 553                 };
 554
 555                 mailbox8: mailbox@48846000 {
 556                         compatible = "ti,omap4-mailbox";
 557                         reg = <0x48846000 0x200>;
 558                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 559                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 560                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 561                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 562                         ti,hwmods = "mailbox8";
 563                         #mbox-cells = <1>;
 564                         ti,mbox-num-users = <4>;
 565                         ti,mbox-num-fifos = <12>;
 566                         status = "disabled";
 567                 };
 568
 569                 mailbox9: mailbox@4885e000 {
 570                         compatible = "ti,omap4-mailbox";
 571                         reg = <0x4885e000 0x200>;
 572                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 574                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 575                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 576                         ti,hwmods = "mailbox9";
 577                         #mbox-cells = <1>;
 578                         ti,mbox-num-users = <4>;
 579                         ti,mbox-num-fifos = <12>;
 580                         status = "disabled";
 581                 };
 582
 583                 mailbox10: mailbox@48860000 {
 584                         compatible = "ti,omap4-mailbox";
 585                         reg = <0x48860000 0x200>;
 586                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 590                         ti,hwmods = "mailbox10";
 591                         #mbox-cells = <1>;
 592                         ti,mbox-num-users = <4>;
 593                         ti,mbox-num-fifos = <12>;
 594                         status = "disabled";
 595                 };
 596
 597                 mailbox11: mailbox@48862000 {
 598                         compatible = "ti,omap4-mailbox";
 599                         reg = <0x48862000 0x200>;
 600                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 601                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 602                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 604                         ti,hwmods = "mailbox11";
 605                         #mbox-cells = <1>;
 606                         ti,mbox-num-users = <4>;
 607                         ti,mbox-num-fifos = <12>;
 608                         status = "disabled";
 609                 };
 610
 611                 mailbox12: mailbox@48864000 {
 612                         compatible = "ti,omap4-mailbox";
 613                         reg = <0x48864000 0x200>;
 614                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 615                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 618                         ti,hwmods = "mailbox12";
 619                         #mbox-cells = <1>;
 620                         ti,mbox-num-users = <4>;
 621                         ti,mbox-num-fifos = <12>;
 622                         status = "disabled";
 623                 };
 624
 625                 mailbox13: mailbox@48802000 {
 626                         compatible = "ti,omap4-mailbox";
 627                         reg = <0x48802000 0x200>;
 628                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 632                         ti,hwmods = "mailbox13";
 633                         #mbox-cells = <1>;
 634                         ti,mbox-num-users = <4>;
 635                         ti,mbox-num-fifos = <12>;
 636                         status = "disabled";
 637                 };
 638
 639                 timer1: timer@4ae18000 {
 640                         compatible = "ti,omap5430-timer";
 641                         reg = <0x4ae18000 0x80>;
 642                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 643                         ti,hwmods = "timer1";
 644                         ti,timer-alwon;
 645                 };
 646
 647                 timer2: timer@48032000 {
 648                         compatible = "ti,omap5430-timer";
 649                         reg = <0x48032000 0x80>;
 650                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 651                         ti,hwmods = "timer2";
 652                 };
 653
 654                 timer3: timer@48034000 {
 655                         compatible = "ti,omap5430-timer";
 656                         reg = <0x48034000 0x80>;
 657                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "timer3";
 659                 };
 660
 661                 timer4: timer@48036000 {
 662                         compatible = "ti,omap5430-timer";
 663                         reg = <0x48036000 0x80>;
 664                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 665                         ti,hwmods = "timer4";
 666                 };
 667
 668                 timer5: timer@48820000 {
 669                         compatible = "ti,omap5430-timer";
 670                         reg = <0x48820000 0x80>;
 671                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 672                         ti,hwmods = "timer5";
 673                         ti,timer-dsp;
 674                 };
 675
 676                 timer6: timer@48822000 {
 677                         compatible = "ti,omap5430-timer";
 678                         reg = <0x48822000 0x80>;
 679                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 680                         ti,hwmods = "timer6";
 681                         ti,timer-dsp;
 682                         ti,timer-pwm;
 683                 };
 684
 685                 timer7: timer@48824000 {
 686                         compatible = "ti,omap5430-timer";
 687                         reg = <0x48824000 0x80>;
 688                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 689                         ti,hwmods = "timer7";
 690                         ti,timer-dsp;
 691                 };
 692
 693                 timer8: timer@48826000 {
 694                         compatible = "ti,omap5430-timer";
 695                         reg = <0x48826000 0x80>;
 696                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 697                         ti,hwmods = "timer8";
 698                         ti,timer-dsp;
 699                         ti,timer-pwm;
 700                 };
 701
 702                 timer9: timer@4803e000 {
 703                         compatible = "ti,omap5430-timer";
 704                         reg = <0x4803e000 0x80>;
 705                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 706                         ti,hwmods = "timer9";
 707                 };
 708
 709                 timer10: timer@48086000 {
 710                         compatible = "ti,omap5430-timer";
 711                         reg = <0x48086000 0x80>;
 712                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 713                         ti,hwmods = "timer10";
 714                 };
 715
 716                 timer11: timer@48088000 {
 717                         compatible = "ti,omap5430-timer";
 718                         reg = <0x48088000 0x80>;
 719                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 720                         ti,hwmods = "timer11";
 721                         ti,timer-pwm;
 722                 };
 723
 724                 timer13: timer@48828000 {
 725                         compatible = "ti,omap5430-timer";
 726                         reg = <0x48828000 0x80>;
 727                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 728                         ti,hwmods = "timer13";
 729                         status = "disabled";
 730                 };
 731
 732                 timer14: timer@4882a000 {
 733                         compatible = "ti,omap5430-timer";
 734                         reg = <0x4882a000 0x80>;
 735                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 736                         ti,hwmods = "timer14";
 737                         status = "disabled";
 738                 };
 739
 740                 timer15: timer@4882c000 {
 741                         compatible = "ti,omap5430-timer";
 742                         reg = <0x4882c000 0x80>;
 743                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 744                         ti,hwmods = "timer15";
 745                         status = "disabled";
 746                 };
 747
 748                 timer16: timer@4882e000 {
 749                         compatible = "ti,omap5430-timer";
 750                         reg = <0x4882e000 0x80>;
 751                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 752                         ti,hwmods = "timer16";
 753                         status = "disabled";
 754                 };
 755
 756                 wdt2: wdt@4ae14000 {
 757                         compatible = "ti,omap3-wdt";
 758                         reg = <0x4ae14000 0x80>;
 759                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 760                         ti,hwmods = "wd_timer2";
 761                 };
 762
 763                 hwspinlock: spinlock@4a0f6000 {
 764                         compatible = "ti,omap4-hwspinlock";
 765                         reg = <0x4a0f6000 0x1000>;
 766                         ti,hwmods = "spinlock";
 767                         #hwlock-cells = <1>;
 768                 };
 769
 770                 dmm@4e000000 {
 771                         compatible = "ti,omap5-dmm";
 772                         reg = <0x4e000000 0x800>;
 773                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 774                         ti,hwmods = "dmm";
 775                 };
 776
 777                 i2c1: i2c@48070000 {
 778                         compatible = "ti,omap4-i2c";
 779                         reg = <0x48070000 0x100>;
 780                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 781                         #address-cells = <1>;
 782                         #size-cells = <0>;
 783                         ti,hwmods = "i2c1";
 784                         status = "disabled";
 785                 };
 786
 787                 i2c2: i2c@48072000 {
 788                         compatible = "ti,omap4-i2c";
 789                         reg = <0x48072000 0x100>;
 790                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 791                         #address-cells = <1>;
 792                         #size-cells = <0>;
 793                         ti,hwmods = "i2c2";
 794                         status = "disabled";
 795                 };
 796
 797                 i2c3: i2c@48060000 {
 798                         compatible = "ti,omap4-i2c";
 799                         reg = <0x48060000 0x100>;
 800                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 801                         #address-cells = <1>;
 802                         #size-cells = <0>;
 803                         ti,hwmods = "i2c3";
 804                         status = "disabled";
 805                 };
 806
 807                 i2c4: i2c@4807a000 {
 808                         compatible = "ti,omap4-i2c";
 809                         reg = <0x4807a000 0x100>;
 810                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 811                         #address-cells = <1>;
 812                         #size-cells = <0>;
 813                         ti,hwmods = "i2c4";
 814                         status = "disabled";
 815                 };
 816
 817                 i2c5: i2c@4807c000 {
 818                         compatible = "ti,omap4-i2c";
 819                         reg = <0x4807c000 0x100>;
 820                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 821                         #address-cells = <1>;
 822                         #size-cells = <0>;
 823                         ti,hwmods = "i2c5";
 824                         status = "disabled";
 825                 };
 826
 827                 mmc1: mmc@4809c000 {
 828                         compatible = "ti,omap4-hsmmc";
 829                         reg = <0x4809c000 0x400>;
 830                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 831                         ti,hwmods = "mmc1";
 832                         ti,dual-volt;
 833                         ti,needs-special-reset;
 834                         dmas = <&sdma 61>, <&sdma 62>;
 835                         dma-names = "tx", "rx";
 836                         status = "disabled";
 837                         pbias-supply = <&pbias_mmc_reg>;
 838                 };
 839
 840                 mmc2: mmc@480b4000 {
 841                         compatible = "ti,omap4-hsmmc";
 842                         reg = <0x480b4000 0x400>;
 843                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 844                         ti,hwmods = "mmc2";
 845                         ti,needs-special-reset;
 846                         dmas = <&sdma 47>, <&sdma 48>;
 847                         dma-names = "tx", "rx";
 848                         status = "disabled";
 849                 };
 850
 851                 mmc3: mmc@480ad000 {
 852                         compatible = "ti,omap4-hsmmc";
 853                         reg = <0x480ad000 0x400>;
 854                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 855                         ti,hwmods = "mmc3";
 856                         ti,needs-special-reset;
 857                         dmas = <&sdma 77>, <&sdma 78>;
 858                         dma-names = "tx", "rx";
 859                         status = "disabled";
 860                 };
 861
 862                 mmc4: mmc@480d1000 {
 863                         compatible = "ti,omap4-hsmmc";
 864                         reg = <0x480d1000 0x400>;
 865                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 866                         ti,hwmods = "mmc4";
 867                         ti,needs-special-reset;
 868                         dmas = <&sdma 57>, <&sdma 58>;
 869                         dma-names = "tx", "rx";
 870                         status = "disabled";
 871                 };
 872
 873                 abb_mpu: regulator-abb-mpu {
 874                         compatible = "ti,abb-v3";
 875                         regulator-name = "abb_mpu";
 876                         #address-cells = <0>;
 877                         #size-cells = <0>;
 878                         clocks = <&sys_clkin1>;
 879                         ti,settling-time = <50>;
 880                         ti,clock-cycles = <16>;
 881
 882                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 883                               <0x4ae06014 0x4>, <0x4a003b20 0x8>,
 884                               <0x4ae0c158 0x4>;
 885                         reg-names = "setup-address", "control-address",
 886                                     "int-address", "efuse-address",
 887                                     "ldo-address";
 888                         ti,tranxdone-status-mask = <0x80>;
 889                         /* LDOVBBMPU_FBB_MUX_CTRL */
 890                         ti,ldovbb-override-mask = <0x400>;
 891                         /* LDOVBBMPU_FBB_VSET_OUT */
 892                         ti,ldovbb-vset-mask = <0x1F>;
 893
 894                         /*
 895                          * NOTE: only FBB mode used but actual vset will
 896                          * determine final biasing
 897                          */
 898                         ti,abb_info = <
 899                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 900                         1060000         0       0x0     0 0x02000000 0x01F00000
 901                         1160000         0       0x4     0 0x02000000 0x01F00000
 902                         1210000         0       0x8     0 0x02000000 0x01F00000
 903                         >;
 904                 };
 905
 906                 abb_ivahd: regulator-abb-ivahd {
 907                         compatible = "ti,abb-v3";
 908                         regulator-name = "abb_ivahd";
 909                         #address-cells = <0>;
 910                         #size-cells = <0>;
 911                         clocks = <&sys_clkin1>;
 912                         ti,settling-time = <50>;
 913                         ti,clock-cycles = <16>;
 914
 915                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 916                               <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
 917                               <0x4a002470 0x4>;
 918                         reg-names = "setup-address", "control-address",
 919                                     "int-address", "efuse-address",
 920                                     "ldo-address";
 921                         ti,tranxdone-status-mask = <0x40000000>;
 922                         /* LDOVBBIVA_FBB_MUX_CTRL */
 923                         ti,ldovbb-override-mask = <0x400>;
 924                         /* LDOVBBIVA_FBB_VSET_OUT */
 925                         ti,ldovbb-vset-mask = <0x1F>;
 926
 927                         /*
 928                          * NOTE: only FBB mode used but actual vset will
 929                          * determine final biasing
 930                          */
 931                         ti,abb_info = <
 932                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 933                         1055000         0       0x0     0 0x02000000 0x01F00000
 934                         1150000         0       0x4     0 0x02000000 0x01F00000
 935                         1250000         0       0x8     0 0x02000000 0x01F00000
 936                         >;
 937                 };
 938
 939                 abb_dspeve: regulator-abb-dspeve {
 940                         compatible = "ti,abb-v3";
 941                         regulator-name = "abb_dspeve";
 942                         #address-cells = <0>;
 943                         #size-cells = <0>;
 944                         clocks = <&sys_clkin1>;
 945                         ti,settling-time = <50>;
 946                         ti,clock-cycles = <16>;
 947
 948                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 949                               <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
 950                               <0x4a00246c 0x4>;
 951                         reg-names = "setup-address", "control-address",
 952                                     "int-address", "efuse-address",
 953                                     "ldo-address";
 954                         ti,tranxdone-status-mask = <0x20000000>;
 955                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 956                         ti,ldovbb-override-mask = <0x400>;
 957                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 958                         ti,ldovbb-vset-mask = <0x1F>;
 959
 960                         /*
 961                          * NOTE: only FBB mode used but actual vset will
 962                          * determine final biasing
 963                          */
 964                         ti,abb_info = <
 965                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 966                         1055000         0       0x0     0 0x02000000 0x01F00000
 967                         1150000         0       0x4     0 0x02000000 0x01F00000
 968                         1250000         0       0x8     0 0x02000000 0x01F00000
 969                         >;
 970                 };
 971
 972                 abb_gpu: regulator-abb-gpu {
 973                         compatible = "ti,abb-v3";
 974                         regulator-name = "abb_gpu";
 975                         #address-cells = <0>;
 976                         #size-cells = <0>;
 977                         clocks = <&sys_clkin1>;
 978                         ti,settling-time = <50>;
 979                         ti,clock-cycles = <16>;
 980
 981                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 982                               <0x4ae06010 0x4>, <0x4a003b08 0x8>,
 983                               <0x4ae0c154 0x4>;
 984                         reg-names = "setup-address", "control-address",
 985                                     "int-address", "efuse-address",
 986                                     "ldo-address";
 987                         ti,tranxdone-status-mask = <0x10000000>;
 988                         /* LDOVBBGPU_FBB_MUX_CTRL */
 989                         ti,ldovbb-override-mask = <0x400>;
 990                         /* LDOVBBGPU_FBB_VSET_OUT */
 991                         ti,ldovbb-vset-mask = <0x1F>;
 992
 993                         /*
 994                          * NOTE: only FBB mode used but actual vset will
 995                          * determine final biasing
 996                          */
 997                         ti,abb_info = <
 998                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 999                         1090000         0       0x0     0 0x02000000 0x01F00000
1000                         1210000         0       0x4     0 0x02000000 0x01F00000
1001                         1280000         0       0x8     0 0x02000000 0x01F00000
1002                         >;
1003                 };
1004
1005                 mcspi1: spi@48098000 {
1006                         compatible = "ti,omap4-mcspi";
1007                         reg = <0x48098000 0x200>;
1008                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1009                         #address-cells = <1>;
1010                         #size-cells = <0>;
1011                         ti,hwmods = "mcspi1";
1012                         ti,spi-num-cs = <4>;
1013                         dmas = <&sdma 35>,
1014                                <&sdma 36>,
1015                                <&sdma 37>,
1016                                <&sdma 38>,
1017                                <&sdma 39>,
1018                                <&sdma 40>,
1019                                <&sdma 41>,
1020                                <&sdma 42>;
1021                         dma-names = "tx0", "rx0", "tx1", "rx1",
1022                                     "tx2", "rx2", "tx3", "rx3";
1023                         status = "disabled";
1024                 };
1025
1026                 mcspi2: spi@4809a000 {
1027                         compatible = "ti,omap4-mcspi";
1028                         reg = <0x4809a000 0x200>;
1029                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1030                         #address-cells = <1>;
1031                         #size-cells = <0>;
1032                         ti,hwmods = "mcspi2";
1033                         ti,spi-num-cs = <2>;
1034                         dmas = <&sdma 43>,
1035                                <&sdma 44>,
1036                                <&sdma 45>,
1037                                <&sdma 46>;
1038                         dma-names = "tx0", "rx0", "tx1", "rx1";
1039                         status = "disabled";
1040                 };
1041
1042                 mcspi3: spi@480b8000 {
1043                         compatible = "ti,omap4-mcspi";
1044                         reg = <0x480b8000 0x200>;
1045                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1046                         #address-cells = <1>;
1047                         #size-cells = <0>;
1048                         ti,hwmods = "mcspi3";
1049                         ti,spi-num-cs = <2>;
1050                         dmas = <&sdma 15>, <&sdma 16>;
1051                         dma-names = "tx0", "rx0";
1052                         status = "disabled";
1053                 };
1054
1055                 mcspi4: spi@480ba000 {
1056                         compatible = "ti,omap4-mcspi";
1057                         reg = <0x480ba000 0x200>;
1058                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1059                         #address-cells = <1>;
1060                         #size-cells = <0>;
1061                         ti,hwmods = "mcspi4";
1062                         ti,spi-num-cs = <1>;
1063                         dmas = <&sdma 70>, <&sdma 71>;
1064                         dma-names = "tx0", "rx0";
1065                         status = "disabled";
1066                 };
1067
1068                 qspi: qspi@4b300000 {
1069                         compatible = "ti,dra7xxx-qspi";
1070                         reg = <0x4b300000 0x100>;
1071                         reg-names = "qspi_base";
1072                         #address-cells = <1>;
1073                         #size-cells = <0>;
1074                         ti,hwmods = "qspi";
1075                         clocks = <&qspi_gfclk_div>;
1076                         clock-names = "fck";
1077                         num-cs = <4>;
1078                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1079                         status = "disabled";
1080                 };
1081
1082                 omap_control_sata: control-phy@4a002374 {
1083                         compatible = "ti,control-phy-pipe3";
1084                         reg = <0x4a002374 0x4>;
1085                         reg-names = "power";
1086                         clocks = <&sys_clkin1>;
1087                         clock-names = "sysclk";
1088                 };
1089
1090                 /* OCP2SCP3 */
1091                 ocp2scp@4a090000 {
1092                         compatible = "ti,omap-ocp2scp";
1093                         #address-cells = <1>;
1094                         #size-cells = <1>;
1095                         ranges;
1096                         reg = <0x4a090000 0x20>;
1097                         ti,hwmods = "ocp2scp3";
1098                         sata_phy: phy@4A096000 {
1099                                 compatible = "ti,phy-pipe3-sata";
1100                                 reg = <0x4A096000 0x80>, /* phy_rx */
1101                                       <0x4A096400 0x64>, /* phy_tx */
1102                                       <0x4A096800 0x40>; /* pll_ctrl */
1103                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1104                                 ctrl-module = <&omap_control_sata>;
1105                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1106                                 clock-names = "sysclk", "refclk";
1107                                 #phy-cells = <0>;
1108                         };
1109
1110                         pcie1_phy: pciephy@4a094000 {
1111                                 compatible = "ti,phy-pipe3-pcie";
1112                                 reg = <0x4a094000 0x80>, /* phy_rx */
1113                                       <0x4a094400 0x64>; /* phy_tx */
1114                                 reg-names = "phy_rx", "phy_tx";
1115                                 ctrl-module = <&omap_control_pcie1phy>;
1116                                 clocks = <&dpll_pcie_ref_ck>,
1117                                          <&dpll_pcie_ref_m2ldo_ck>,
1118                                          <&optfclk_pciephy1_32khz>,
1119                                          <&optfclk_pciephy1_clk>,
1120                                          <&optfclk_pciephy1_div_clk>,
1121                                          <&optfclk_pciephy_div>;
1122                                 clock-names = "dpll_ref", "dpll_ref_m2",
1123                                               "wkupclk", "refclk",
1124                                               "div-clk", "phy-div";
1125                                 #phy-cells = <0>;
1126                         };
1127
1128                         pcie2_phy: pciephy@4a095000 {
1129                                 compatible = "ti,phy-pipe3-pcie";
1130                                 reg = <0x4a095000 0x80>, /* phy_rx */
1131                                       <0x4a095400 0x64>; /* phy_tx */
1132                                 reg-names = "phy_rx", "phy_tx";
1133                                 ctrl-module = <&omap_control_pcie2phy>;
1134                                 clocks = <&dpll_pcie_ref_ck>,
1135                                          <&dpll_pcie_ref_m2ldo_ck>,
1136                                          <&optfclk_pciephy2_32khz>,
1137                                          <&optfclk_pciephy2_clk>,
1138                                          <&optfclk_pciephy2_div_clk>,
1139                                          <&optfclk_pciephy_div>;
1140                                 clock-names = "dpll_ref", "dpll_ref_m2",
1141                                               "wkupclk", "refclk",
1142                                               "div-clk", "phy-div";
1143                                 #phy-cells = <0>;
1144                                 status = "disabled";
1145                         };
1146                 };
1147
1148                 sata: sata@4a141100 {
1149                         compatible = "snps,dwc-ahci";
1150                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1151                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1152                         phys = <&sata_phy>;
1153                         phy-names = "sata-phy";
1154                         clocks = <&sata_ref_clk>;
1155                         ti,hwmods = "sata";
1156                 };
1157
1158                 omap_control_pcie1phy: control-phy@0x4a003c40 {
1159                         compatible = "ti,control-phy-pcie";
1160                         reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1161                         reg-names = "power", "control_sma", "pcie_pcs";
1162                         clocks = <&sys_clkin1>;
1163                         clock-names = "sysclk";
1164                 };
1165
1166                 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1167                         compatible = "ti,control-phy-pcie";
1168                         reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1169                         reg-names = "power", "control_sma", "pcie_pcs";
1170                         clocks = <&sys_clkin1>;
1171                         clock-names = "sysclk";
1172                         status = "disabled";
1173                 };
1174
1175                 rtc@48838000 {
1176                         compatible = "ti,am3352-rtc";
1177                         reg = <0x48838000 0x100>;
1178                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1179                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1180                         ti,hwmods = "rtcss";
1181                         clocks = <&sys_32k_ck>;
1182                 };
1183
1184                 omap_control_usb2phy1: control-phy@4a002300 {
1185                         compatible = "ti,control-phy-usb2";
1186                         reg = <0x4a002300 0x4>;
1187                         reg-names = "power";
1188                 };
1189
1190                 omap_control_usb3phy1: control-phy@4a002370 {
1191                         compatible = "ti,control-phy-pipe3";
1192                         reg = <0x4a002370 0x4>;
1193                         reg-names = "power";
1194                 };
1195
1196                 omap_control_usb2phy2: control-phy@0x4a002e74 {
1197                         compatible = "ti,control-phy-usb2-dra7";
1198                         reg = <0x4a002e74 0x4>;
1199                         reg-names = "power";
1200                 };
1201
1202                 /* OCP2SCP1 */
1203                 ocp2scp@4a080000 {
1204                         compatible = "ti,omap-ocp2scp";
1205                         #address-cells = <1>;
1206                         #size-cells = <1>;
1207                         ranges;
1208                         reg = <0x4a080000 0x20>;
1209                         ti,hwmods = "ocp2scp1";
1210
1211                         usb2_phy1: phy@4a084000 {
1212                                 compatible = "ti,omap-usb2";
1213                                 reg = <0x4a084000 0x400>;
1214                                 ctrl-module = <&omap_control_usb2phy1>;
1215                                 clocks = <&usb_phy1_always_on_clk32k>,
1216                                          <&usb_otg_ss1_refclk960m>;
1217                                 clock-names =   "wkupclk",
1218                                                 "refclk";
1219                                 #phy-cells = <0>;
1220                         };
1221
1222                         usb2_phy2: phy@4a085000 {
1223                                 compatible = "ti,omap-usb2";
1224                                 reg = <0x4a085000 0x400>;
1225                                 ctrl-module = <&omap_control_usb2phy2>;
1226                                 clocks = <&usb_phy2_always_on_clk32k>,
1227                                          <&usb_otg_ss2_refclk960m>;
1228                                 clock-names =   "wkupclk",
1229                                                 "refclk";
1230                                 #phy-cells = <0>;
1231                         };
1232
1233                         usb3_phy1: phy@4a084400 {
1234                                 compatible = "ti,omap-usb3";
1235                                 reg = <0x4a084400 0x80>,
1236                                       <0x4a084800 0x64>,
1237                                       <0x4a084c00 0x40>;
1238                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1239                                 ctrl-module = <&omap_control_usb3phy1>;
1240                                 clocks = <&usb_phy3_always_on_clk32k>,
1241                                          <&sys_clkin1>,
1242                                          <&usb_otg_ss1_refclk960m>;
1243                                 clock-names =   "wkupclk",
1244                                                 "sysclk",
1245                                                 "refclk";
1246                                 #phy-cells = <0>;
1247                         };
1248                 };
1249
1250                 omap_dwc3_1: omap_dwc3_1@48880000 {
1251                         compatible = "ti,dwc3";
1252                         ti,hwmods = "usb_otg_ss1";
1253                         reg = <0x48880000 0x10000>;
1254                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1255                         #address-cells = <1>;
1256                         #size-cells = <1>;
1257                         utmi-mode = <2>;
1258                         ranges;
1259                         usb1: usb@48890000 {
1260                                 compatible = "snps,dwc3";
1261                                 reg = <0x48890000 0x17000>;
1262                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1263                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1264                                 phy-names = "usb2-phy", "usb3-phy";
1265                                 tx-fifo-resize;
1266                                 maximum-speed = "super-speed";
1267                                 dr_mode = "otg";
1268                                 snps,dis_u3_susphy_quirk;
1269                                 snps,dis_u2_susphy_quirk;
1270                         };
1271                 };
1272
1273                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1274                         compatible = "ti,dwc3";
1275                         ti,hwmods = "usb_otg_ss2";
1276                         reg = <0x488c0000 0x10000>;
1277                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1278                         #address-cells = <1>;
1279                         #size-cells = <1>;
1280                         utmi-mode = <2>;
1281                         ranges;
1282                         usb2: usb@488d0000 {
1283                                 compatible = "snps,dwc3";
1284                                 reg = <0x488d0000 0x17000>;
1285                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1286                                 phys = <&usb2_phy2>;
1287                                 phy-names = "usb2-phy";
1288                                 tx-fifo-resize;
1289                                 maximum-speed = "high-speed";
1290                                 dr_mode = "otg";
1291                                 snps,dis_u3_susphy_quirk;
1292                                 snps,dis_u2_susphy_quirk;
1293                         };
1294                 };
1295
1296                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1297                 omap_dwc3_3: omap_dwc3_3@48900000 {
1298                         compatible = "ti,dwc3";
1299                         ti,hwmods = "usb_otg_ss3";
1300                         reg = <0x48900000 0x10000>;
1301                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1302                         #address-cells = <1>;
1303                         #size-cells = <1>;
1304                         utmi-mode = <2>;
1305                         ranges;
1306                         status = "disabled";
1307                         usb3: usb@48910000 {
1308                                 compatible = "snps,dwc3";
1309                                 reg = <0x48910000 0x17000>;
1310                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1311                                 tx-fifo-resize;
1312                                 maximum-speed = "high-speed";
1313                                 dr_mode = "otg";
1314                                 snps,dis_u3_susphy_quirk;
1315                                 snps,dis_u2_susphy_quirk;
1316                         };
1317                 };
1318
1319                 elm: elm@48078000 {
1320                         compatible = "ti,am3352-elm";
1321                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1322                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1323                         ti,hwmods = "elm";
1324                         status = "disabled";
1325                 };
1326
1327                 gpmc: gpmc@50000000 {
1328                         compatible = "ti,am3352-gpmc";
1329                         ti,hwmods = "gpmc";
1330                         reg = <0x50000000 0x37c>;      /* device IO registers */
1331                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1332                         gpmc,num-cs = <8>;
1333                         gpmc,num-waitpins = <2>;
1334                         #address-cells = <2>;
1335                         #size-cells = <1>;
1336                         status = "disabled";
1337                 };
1338
1339                 atl: atl@4843c000 {
1340                         compatible = "ti,dra7-atl";
1341                         reg = <0x4843c000 0x3ff>;
1342                         ti,hwmods = "atl";
1343                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1344                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1345                         clocks = <&atl_gfclk_mux>;
1346                         clock-names = "fck";
1347                         status = "disabled";
1348                 };
1349
1350                 crossbar_mpu: crossbar@4a020000 {
1351                         compatible = "ti,irq-crossbar";
1352                         reg = <0x4a002a48 0x130>;
1353                         ti,max-irqs = <160>;
1354                         ti,max-crossbar-sources = <MAX_SOURCES>;
1355                         ti,reg-size = <2>;
1356                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1357                         ti,irqs-skip = <10 133 139 140>;
1358                         ti,irqs-safe-map = <0>;
1359                 };
1360
1361                 mac: ethernet@4a100000 {
1362                         compatible = "ti,cpsw";
1363                         ti,hwmods = "gmac";
1364                         clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>;
1365                         clock-names = "fck", "cpts";
1366                         cpdma_channels = <8>;
1367                         ale_entries = <1024>;
1368                         bd_ram_size = <0x2000>;
1369                         no_bd_ram = <0>;
1370                         rx_descs = <64>;
1371                         mac_control = <0x20>;
1372                         slaves = <2>;
1373                         active_slave = <0>;
1374                         cpts_clock_mult = <0x80000000>;
1375                         cpts_clock_shift = <29>;
1376                         reg = <0x48484000 0x1000
1377                                0x48485200 0x2E00>;
1378                         #address-cells = <1>;
1379                         #size-cells = <1>;
1380                         /*
1381                          * rx_thresh_pend
1382                          * rx_pend
1383                          * tx_pend
1384                          * misc_pend
1385                          */
1386                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1387                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1388                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1389                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1390                         ranges;
1391                         status = "disabled";
1392
1393                         davinci_mdio: mdio@48485000 {
1394                                 compatible = "ti,davinci_mdio";
1395                                 #address-cells = <1>;
1396                                 #size-cells = <0>;
1397                                 ti,hwmods = "davinci_mdio";
1398                                 bus_freq = <1000000>;
1399                                 reg = <0x48485000 0x100>;
1400                         };
1401
1402                         cpsw_emac0: slave@48480200 {
1403                                 /* Filled in by U-Boot */
1404                                 mac-address = [ 00 00 00 00 00 00 ];
1405                         };
1406
1407                         cpsw_emac1: slave@48480300 {
1408                                 /* Filled in by U-Boot */
1409                                 mac-address = [ 00 00 00 00 00 00 ];
1410                         };
1411
1412                         phy_sel: cpsw-phy-sel@4a002554 {
1413                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1414                                 reg= <0x4a002554 0x4>;
1415                                 reg-names = "gmii-sel";
1416                         };
1417                 };
1418
1419                 dcan1: can@481cc000 {
1420                         compatible = "ti,dra7-d_can";
1421                         ti,hwmods = "dcan1";
1422                         reg = <0x4ae3c000 0x2000>;
1423                         syscon-raminit = <&dra7_ctrl_core 0x558 0>;
1424                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1425                         clocks = <&dcan1_sys_clk_mux>;
1426                         status = "disabled";
1427                 };
1428
1429                 dcan2: can@481d0000 {
1430                         compatible = "ti,dra7-d_can";
1431                         ti,hwmods = "dcan2";
1432                         reg = <0x48480000 0x2000>;
1433                         syscon-raminit = <&dra7_ctrl_core 0x558 1>;
1434                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1435                         clocks = <&sys_clkin1>;
1436                         status = "disabled";
1437                 };
1438         };
1439
1440         thermal_zones: thermal-zones {
1441                 #include "omap4-cpu-thermal.dtsi"
1442                 #include "omap5-gpu-thermal.dtsi"
1443                 #include "omap5-core-thermal.dtsi"
1444         };
1445
1446 };
1447
1448 &cpu_thermal {
1449         polling-delay = <500>; /* milliseconds */
1450 };
1451
1452 /include/ "dra7xx-clocks.dtsi"