arch/arm/boot/dts/imx51.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         aliases {
  17                 serial0 = &uart1;
  18                 serial1 = &uart2;
  19                 serial2 = &uart3;
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24         };
  25
  26         tzic: tz-interrupt-controller@e0000000 {
  27                 compatible = "fsl,imx51-tzic", "fsl,tzic";
  28                 interrupt-controller;
  29                 #interrupt-cells = <1>;
  30                 reg = <0xe0000000 0x4000>;
  31         };
  32
  33         clocks {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 ckil {
  38                         compatible = "fsl,imx-ckil", "fixed-clock";
  39                         clock-frequency = <32768>;
  40                 };
  41
  42                 ckih1 {
  43                         compatible = "fsl,imx-ckih1", "fixed-clock";
  44                         clock-frequency = <22579200>;
  45                 };
  46
  47                 ckih2 {
  48                         compatible = "fsl,imx-ckih2", "fixed-clock";
  49                         clock-frequency = <0>;
  50                 };
  51
  52                 osc {
  53                         compatible = "fsl,imx-osc", "fixed-clock";
  54                         clock-frequency = <24000000>;
  55                 };
  56         };
  57
  58         soc {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 compatible = "simple-bus";
  62                 interrupt-parent = <&tzic>;
  63                 ranges;
  64
  65                 aips@70000000 { /* AIPS1 */
  66                         compatible = "fsl,aips-bus", "simple-bus";
  67                         #address-cells = <1>;
  68                         #size-cells = <1>;
  69                         reg = <0x70000000 0x10000000>;
  70                         ranges;
  71
  72                         spba@70000000 {
  73                                 compatible = "fsl,spba-bus", "simple-bus";
  74                                 #address-cells = <1>;
  75                                 #size-cells = <1>;
  76                                 reg = <0x70000000 0x40000>;
  77                                 ranges;
  78
  79                                 esdhc1: esdhc@70004000 {
  80                                         compatible = "fsl,imx51-esdhc";
  81                                         reg = <0x70004000 0x4000>;
  82                                         interrupts = <1>;
  83                                         status = "disabled";
  84                                 };
  85
  86                                 esdhc2: esdhc@70008000 {
  87                                         compatible = "fsl,imx51-esdhc";
  88                                         reg = <0x70008000 0x4000>;
  89                                         interrupts = <2>;
  90                                         bus-width = <4>;
  91                                         status = "disabled";
  92                                 };
  93
  94                                 uart3: serial@7000c000 {
  95                                         compatible = "fsl,imx51-uart", "fsl,imx21-uart";
  96                                         reg = <0x7000c000 0x4000>;
  97                                         interrupts = <33>;
  98                                         status = "disabled";
  99                                 };
 100
 101                                 ecspi1: ecspi@70010000 {
 102                                         #address-cells = <1>;
 103                                         #size-cells = <0>;
 104                                         compatible = "fsl,imx51-ecspi";
 105                                         reg = <0x70010000 0x4000>;
 106                                         interrupts = <36>;
 107                                         status = "disabled";
 108                                 };
 109
 110                                 ssi2: ssi@70014000 {
 111                                         compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 112                                         reg = <0x70014000 0x4000>;
 113                                         interrupts = <30>;
 114                                         fsl,fifo-depth = <15>;
 115                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 116                                         status = "disabled";
 117                                 };
 118
 119                                 esdhc3: esdhc@70020000 {
 120                                         compatible = "fsl,imx51-esdhc";
 121                                         reg = <0x70020000 0x4000>;
 122                                         interrupts = <3>;
 123                                         bus-width = <4>;
 124                                         status = "disabled";
 125                                 };
 126
 127                                 esdhc4: esdhc@70024000 {
 128                                         compatible = "fsl,imx51-esdhc";
 129                                         reg = <0x70024000 0x4000>;
 130                                         interrupts = <4>;
 131                                         bus-width = <4>;
 132                                         status = "disabled";
 133                                 };
 134                         };
 135
 136                         usbotg: usb@73f80000 {
 137                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 138                                 reg = <0x73f80000 0x0200>;
 139                                 interrupts = <18>;
 140                                 status = "disabled";
 141                         };
 142
 143                         usbh1: usb@73f80200 {
 144                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 145                                 reg = <0x73f80200 0x0200>;
 146                                 interrupts = <14>;
 147                                 status = "disabled";
 148                         };
 149
 150                         usbh2: usb@73f80400 {
 151                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 152                                 reg = <0x73f80400 0x0200>;
 153                                 interrupts = <16>;
 154                                 status = "disabled";
 155                         };
 156
 157                         usbh3: usb@73f80600 {
 158                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
 159                                 reg = <0x73f80600 0x0200>;
 160                                 interrupts = <17>;
 161                                 status = "disabled";
 162                         };
 163
 164                         gpio1: gpio@73f84000 {
 165                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 166                                 reg = <0x73f84000 0x4000>;
 167                                 interrupts = <50 51>;
 168                                 gpio-controller;
 169                                 #gpio-cells = <2>;
 170                                 interrupt-controller;
 171                                 #interrupt-cells = <2>;
 172                         };
 173
 174                         gpio2: gpio@73f88000 {
 175                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 176                                 reg = <0x73f88000 0x4000>;
 177                                 interrupts = <52 53>;
 178                                 gpio-controller;
 179                                 #gpio-cells = <2>;
 180                                 interrupt-controller;
 181                                 #interrupt-cells = <2>;
 182                         };
 183
 184                         gpio3: gpio@73f8c000 {
 185                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 186                                 reg = <0x73f8c000 0x4000>;
 187                                 interrupts = <54 55>;
 188                                 gpio-controller;
 189                                 #gpio-cells = <2>;
 190                                 interrupt-controller;
 191                                 #interrupt-cells = <2>;
 192                         };
 193
 194                         gpio4: gpio@73f90000 {
 195                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
 196                                 reg = <0x73f90000 0x4000>;
 197                                 interrupts = <56 57>;
 198                                 gpio-controller;
 199                                 #gpio-cells = <2>;
 200                                 interrupt-controller;
 201                                 #interrupt-cells = <2>;
 202                         };
 203
 204                         wdog1: wdog@73f98000 {
 205                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 206                                 reg = <0x73f98000 0x4000>;
 207                                 interrupts = <58>;
 208                         };
 209
 210                         wdog2: wdog@73f9c000 {
 211                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
 212                                 reg = <0x73f9c000 0x4000>;
 213                                 interrupts = <59>;
 214                                 status = "disabled";
 215                         };
 216
 217                         iomuxc: iomuxc@73fa8000 {
 218                                 compatible = "fsl,imx51-iomuxc";
 219                                 reg = <0x73fa8000 0x4000>;
 220
 221                                 audmux {
 222                                         pinctrl_audmux_1: audmuxgrp-1 {
 223                                                 fsl,pins = <
 224                                                         384 0x80000000  /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
 225                                                         386 0x80000000  /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
 226                                                         389 0x80000000  /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
 227                                                         391 0x80000000  /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
 228                                                 >;
 229                                         };
 230                                 };
 231
 232                                 fec {
 233                                         pinctrl_fec_1: fecgrp-1 {
 234                                                 fsl,pins = <
 235                                                         128 0x80000000  /* MX51_PAD_EIM_EB2__FEC_MDIO */
 236                                                         134 0x80000000  /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
 237                                                         146 0x80000000  /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
 238                                                         152 0x80000000  /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
 239                                                         158 0x80000000  /* MX51_PAD_EIM_CS4__FEC_RX_ER */
 240                                                         165 0x80000000  /* MX51_PAD_EIM_CS5__FEC_CRS */
 241                                                         206 0x80000000  /* MX51_PAD_NANDF_RB2__FEC_COL */
 242                                                         213 0x80000000  /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
 243                                                         293 0x80000000  /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
 244                                                         298 0x80000000  /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
 245                                                         225 0x80000000  /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
 246                                                         231 0x80000000  /* MX51_PAD_NANDF_CS3__FEC_MDC */
 247                                                         237 0x80000000  /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
 248                                                         243 0x80000000  /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
 249                                                         250 0x80000000  /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
 250                                                         255 0x80000000  /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
 251                                                         260 0x80000000  /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
 252                                                 >;
 253                                         };
 254                                 };
 255
 256                                 ecspi1 {
 257                                         pinctrl_ecspi1_1: ecspi1grp-1 {
 258                                                 fsl,pins = <
 259                                                         398 0x185       /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
 260                                                         394 0x185       /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
 261                                                         409 0x185       /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
 262                                                 >;
 263                                         };
 264                                 };
 265
 266                                 esdhc1 {
 267                                         pinctrl_esdhc1_1: esdhc1grp-1 {
 268                                                 fsl,pins = <
 269                                                         666 0x400020d5  /* MX51_PAD_SD1_CMD__SD1_CMD */
 270                                                         669 0x20d5      /* MX51_PAD_SD1_CLK__SD1_CLK */
 271                                                         672 0x20d5      /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
 272                                                         678 0x20d5      /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
 273                                                         684 0x20d5      /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
 274                                                         691 0x20d5      /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
 275                                                 >;
 276                                         };
 277                                 };
 278
 279                                 esdhc2 {
 280                                         pinctrl_esdhc2_1: esdhc2grp-1 {
 281                                                 fsl,pins = <
 282                                                         704 0x400020d5  /* MX51_PAD_SD2_CMD__SD2_CMD */
 283                                                         707 0x20d5      /* MX51_PAD_SD2_CLK__SD2_CLK */
 284                                                         710 0x20d5      /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
 285                                                         712 0x20d5      /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
 286                                                         715 0x20d5      /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
 287                                                         719 0x20d5      /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
 288                                                 >;
 289                                         };
 290                                 };
 291
 292                                 i2c2 {
 293                                         pinctrl_i2c2_1: i2c2grp-1 {
 294                                                 fsl,pins = <
 295                                                         449 0x400001ed  /* MX51_PAD_KEY_COL4__I2C2_SCL */
 296                                                         454 0x400001ed  /* MX51_PAD_KEY_COL5__I2C2_SDA */
 297                                                 >;
 298                                         };
 299                                 };
 300
 301                                 uart1 {
 302                                         pinctrl_uart1_1: uart1grp-1 {
 303                                                 fsl,pins = <
 304                                                         413 0x1c5       /* MX51_PAD_UART1_RXD__UART1_RXD */
 305                                                         416 0x1c5       /* MX51_PAD_UART1_TXD__UART1_TXD */
 306                                                         418 0x1c5       /* MX51_PAD_UART1_RTS__UART1_RTS */
 307                                                         420 0x1c5       /* MX51_PAD_UART1_CTS__UART1_CTS */
 308                                                 >;
 309                                         };
 310                                 };
 311
 312                                 uart2 {
 313                                         pinctrl_uart2_1: uart2grp-1 {
 314                                                 fsl,pins = <
 315                                                         423 0x1c5       /* MX51_PAD_UART2_RXD__UART2_RXD */
 316                                                         426 0x1c5       /* MX51_PAD_UART2_TXD__UART2_TXD */
 317                                                 >;
 318                                         };
 319                                 };
 320
 321                                 uart3 {
 322                                         pinctrl_uart3_1: uart3grp-1 {
 323                                                 fsl,pins = <
 324                                                         54 0x1c5        /* MX51_PAD_EIM_D25__UART3_RXD */
 325                                                         59 0x1c5        /* MX51_PAD_EIM_D26__UART3_TXD */
 326                                                         65 0x1c5        /* MX51_PAD_EIM_D27__UART3_RTS */
 327                                                         49 0x1c5        /* MX51_PAD_EIM_D24__UART3_CTS */
 328                                                 >;
 329                                         };
 330                                 };
 331                         };
 332
 333                         uart1: serial@73fbc000 {
 334                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 335                                 reg = <0x73fbc000 0x4000>;
 336                                 interrupts = <31>;
 337                                 status = "disabled";
 338                         };
 339
 340                         uart2: serial@73fc0000 {
 341                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 342                                 reg = <0x73fc0000 0x4000>;
 343                                 interrupts = <32>;
 344                                 status = "disabled";
 345                         };
 346                 };
 347
 348                 aips@80000000 { /* AIPS2 */
 349                         compatible = "fsl,aips-bus", "simple-bus";
 350                         #address-cells = <1>;
 351                         #size-cells = <1>;
 352                         reg = <0x80000000 0x10000000>;
 353                         ranges;
 354
 355                         ecspi2: ecspi@83fac000 {
 356                                 #address-cells = <1>;
 357                                 #size-cells = <0>;
 358                                 compatible = "fsl,imx51-ecspi";
 359                                 reg = <0x83fac000 0x4000>;
 360                                 interrupts = <37>;
 361                                 status = "disabled";
 362                         };
 363
 364                         sdma: sdma@83fb0000 {
 365                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
 366                                 reg = <0x83fb0000 0x4000>;
 367                                 interrupts = <6>;
 368                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
 369                         };
 370
 371                         cspi: cspi@83fc0000 {
 372                                 #address-cells = <1>;
 373                                 #size-cells = <0>;
 374                                 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
 375                                 reg = <0x83fc0000 0x4000>;
 376                                 interrupts = <38>;
 377                                 status = "disabled";
 378                         };
 379
 380                         i2c2: i2c@83fc4000 {
 381                                 #address-cells = <1>;
 382                                 #size-cells = <0>;
 383                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 384                                 reg = <0x83fc4000 0x4000>;
 385                                 interrupts = <63>;
 386                                 status = "disabled";
 387                         };
 388
 389                         i2c1: i2c@83fc8000 {
 390                                 #address-cells = <1>;
 391                                 #size-cells = <0>;
 392                                 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
 393                                 reg = <0x83fc8000 0x4000>;
 394                                 interrupts = <62>;
 395                                 status = "disabled";
 396                         };
 397
 398                         ssi1: ssi@83fcc000 {
 399                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 400                                 reg = <0x83fcc000 0x4000>;
 401                                 interrupts = <29>;
 402                                 fsl,fifo-depth = <15>;
 403                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 404                                 status = "disabled";
 405                         };
 406
 407                         audmux: audmux@83fd0000 {
 408                                 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
 409                                 reg = <0x83fd0000 0x4000>;
 410                                 status = "disabled";
 411                         };
 412
 413                         nfc: nand@83fdb000 {
 414                                 compatible = "fsl,imx51-nand";
 415                                 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
 416                                 interrupts = <8>;
 417                                 status = "disabled";
 418                         };
 419
 420                         ssi3: ssi@83fe8000 {
 421                                 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
 422                                 reg = <0x83fe8000 0x4000>;
 423                                 interrupts = <96>;
 424                                 fsl,fifo-depth = <15>;
 425                                 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
 426                                 status = "disabled";
 427                         };
 428
 429                         fec: ethernet@83fec000 {
 430                                 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
 431                                 reg = <0x83fec000 0x4000>;
 432                                 interrupts = <87>;
 433                                 status = "disabled";
 434                         };
 435                 };
 436         };
 437 };