arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 mshc0 = &emmc;
  63                 mshc1 = &sdmmc;
  64                 mshc2 = &sdio0;
  65                 mshc3 = &sdio1;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         arm-pmu {
  77                 compatible = "arm,cortex-a12-pmu";
  78                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  83         };
  84
  85         cpus {
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88                 enable-method = "rockchip,rk3066-smp";
  89                 rockchip,pmu = <&pmu>;
  90
  91                 cpu0: cpu@500 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x500>;
  95                         resets = <&cru SRST_CORE0>;
  96                         operating-points = <
  97                                 /* KHz    uV */
  98                                 1608000 1350000
  99                                 1512000 1300000
 100                                 1416000 1200000
 101                                 1200000 1100000
 102                                 1008000 1050000
 103                                  816000 1000000
 104                                  696000  950000
 105                                  600000  900000
 106                                  408000  900000
 107                                  312000  900000
 108                                  216000  900000
 109                                  126000  900000
 110                         >;
 111                         #cooling-cells = <2>; /* min followed by max */
 112                         clock-latency = <40000>;
 113                         clocks = <&cru ARMCLK>;
 114                 };
 115                 cpu1: cpu@501 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a12";
 118                         reg = <0x501>;
 119                         resets = <&cru SRST_CORE1>;
 120                 };
 121                 cpu2: cpu@502 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x502>;
 125                         resets = <&cru SRST_CORE2>;
 126                 };
 127                 cpu3: cpu@503 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a12";
 130                         reg = <0x503>;
 131                         resets = <&cru SRST_CORE3>;
 132                 };
 133         };
 134
 135         amba {
 136                 compatible = "arm,amba-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140
 141                 dmac_peri: dma-controller@ff250000 {
 142                         compatible = "arm,pl330", "arm,primecell";
 143                         reg = <0xff250000 0x4000>;
 144                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 146                         #dma-cells = <1>;
 147                         clocks = <&cru ACLK_DMAC2>;
 148                         clock-names = "apb_pclk";
 149                 };
 150
 151                 dmac_bus_ns: dma-controller@ff600000 {
 152                         compatible = "arm,pl330", "arm,primecell";
 153                         reg = <0xff600000 0x4000>;
 154                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 155                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 156                         #dma-cells = <1>;
 157                         clocks = <&cru ACLK_DMAC1>;
 158                         clock-names = "apb_pclk";
 159                         status = "disabled";
 160                 };
 161
 162                 dmac_bus_s: dma-controller@ffb20000 {
 163                         compatible = "arm,pl330", "arm,primecell";
 164                         reg = <0xffb20000 0x4000>;
 165                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 166                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 167                         #dma-cells = <1>;
 168                         clocks = <&cru ACLK_DMAC1>;
 169                         clock-names = "apb_pclk";
 170                 };
 171         };
 172
 173         reserved-memory {
 174                 #address-cells = <1>;
 175                 #size-cells = <1>;
 176                 ranges;
 177
 178                 /*
 179                  * The rk3288 cannot use the memory area above 0xfe000000
 180                  * for dma operations for some reason. While there is
 181                  * probably a better solution available somewhere, we
 182                  * haven't found it yet and while devices with 2GB of ram
 183                  * are not affected, this issue prevents 4GB from booting.
 184                  * So to make these devices at least bootable, block
 185                  * this area for the time being until the real solution
 186                  * is found.
 187                  */
 188                 dma-unusable@fe000000 {
 189                         reg = <0xfe000000 0x1000000>;
 190                 };
 191         };
 192
 193         xin24m: oscillator {
 194                 compatible = "fixed-clock";
 195                 clock-frequency = <24000000>;
 196                 clock-output-names = "xin24m";
 197                 #clock-cells = <0>;
 198         };
 199
 200         timer {
 201                 compatible = "arm,armv7-timer";
 202                 arm,cpu-registers-not-fw-configured;
 203                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 204                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 205                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 206                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 207                 clock-frequency = <24000000>;
 208         };
 209
 210         timer: timer@ff810000 {
 211                 compatible = "rockchip,rk3288-timer";
 212                 reg = <0xff810000 0x20>;
 213                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 215                 clock-names = "timer", "pclk";
 216         };
 217
 218         display-subsystem {
 219                 compatible = "rockchip,display-subsystem";
 220                 ports = <&vopl_out>, <&vopb_out>;
 221         };
 222
 223         sdmmc: dwmmc@ff0c0000 {
 224                 compatible = "rockchip,rk3288-dw-mshc";
 225                 clock-freq-min-max = <400000 150000000>;
 226                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 227                 clock-names = "biu", "ciu";
 228                 fifo-depth = <0x100>;
 229                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 230                 reg = <0xff0c0000 0x4000>;
 231                 status = "disabled";
 232         };
 233
 234         sdio0: dwmmc@ff0d0000 {
 235                 compatible = "rockchip,rk3288-dw-mshc";
 236                 clock-freq-min-max = <400000 150000000>;
 237                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
 238                 clock-names = "biu", "ciu";
 239                 fifo-depth = <0x100>;
 240                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 241                 reg = <0xff0d0000 0x4000>;
 242                 status = "disabled";
 243         };
 244
 245         sdio1: dwmmc@ff0e0000 {
 246                 compatible = "rockchip,rk3288-dw-mshc";
 247                 clock-freq-min-max = <400000 150000000>;
 248                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
 249                 clock-names = "biu", "ciu";
 250                 fifo-depth = <0x100>;
 251                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 252                 reg = <0xff0e0000 0x4000>;
 253                 status = "disabled";
 254         };
 255
 256         emmc: dwmmc@ff0f0000 {
 257                 compatible = "rockchip,rk3288-dw-mshc";
 258                 clock-freq-min-max = <400000 150000000>;
 259                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 260                 clock-names = "biu", "ciu";
 261                 fifo-depth = <0x100>;
 262                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 263                 reg = <0xff0f0000 0x4000>;
 264                 status = "disabled";
 265         };
 266
 267         saradc: saradc@ff100000 {
 268                 compatible = "rockchip,saradc";
 269                 reg = <0xff100000 0x100>;
 270                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 271                 #io-channel-cells = <1>;
 272                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 273                 clock-names = "saradc", "apb_pclk";
 274                 status = "disabled";
 275         };
 276
 277         spi0: spi@ff110000 {
 278                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 279                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 280                 clock-names = "spiclk", "apb_pclk";
 281                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 282                 dma-names = "tx", "rx";
 283                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 284                 pinctrl-names = "default";
 285                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 286                 reg = <0xff110000 0x1000>;
 287                 #address-cells = <1>;
 288                 #size-cells = <0>;
 289                 status = "disabled";
 290         };
 291
 292         spi1: spi@ff120000 {
 293                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 294                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 295                 clock-names = "spiclk", "apb_pclk";
 296                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 297                 dma-names = "tx", "rx";
 298                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 301                 reg = <0xff120000 0x1000>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304                 status = "disabled";
 305         };
 306
 307         spi2: spi@ff130000 {
 308                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 309                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 310                 clock-names = "spiclk", "apb_pclk";
 311                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 312                 dma-names = "tx", "rx";
 313                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 314                 pinctrl-names = "default";
 315                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 316                 reg = <0xff130000 0x1000>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 status = "disabled";
 320         };
 321
 322         i2c1: i2c@ff140000 {
 323                 compatible = "rockchip,rk3288-i2c";
 324                 reg = <0xff140000 0x1000>;
 325                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328                 clock-names = "i2c";
 329                 clocks = <&cru PCLK_I2C1>;
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&i2c1_xfer>;
 332                 status = "disabled";
 333         };
 334
 335         i2c3: i2c@ff150000 {
 336                 compatible = "rockchip,rk3288-i2c";
 337                 reg = <0xff150000 0x1000>;
 338                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 339                 #address-cells = <1>;
 340                 #size-cells = <0>;
 341                 clock-names = "i2c";
 342                 clocks = <&cru PCLK_I2C3>;
 343                 pinctrl-names = "default";
 344                 pinctrl-0 = <&i2c3_xfer>;
 345                 status = "disabled";
 346         };
 347
 348         i2c4: i2c@ff160000 {
 349                 compatible = "rockchip,rk3288-i2c";
 350                 reg = <0xff160000 0x1000>;
 351                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 clock-names = "i2c";
 355                 clocks = <&cru PCLK_I2C4>;
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&i2c4_xfer>;
 358                 status = "disabled";
 359         };
 360
 361         i2c5: i2c@ff170000 {
 362                 compatible = "rockchip,rk3288-i2c";
 363                 reg = <0xff170000 0x1000>;
 364                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367                 clock-names = "i2c";
 368                 clocks = <&cru PCLK_I2C5>;
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&i2c5_xfer>;
 371                 status = "disabled";
 372         };
 373
 374         uart0: serial@ff180000 {
 375                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 376                 reg = <0xff180000 0x100>;
 377                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 378                 reg-shift = <2>;
 379                 reg-io-width = <4>;
 380                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 381                 clock-names = "baudclk", "apb_pclk";
 382                 pinctrl-names = "default";
 383                 pinctrl-0 = <&uart0_xfer>;
 384                 status = "disabled";
 385         };
 386
 387         uart1: serial@ff190000 {
 388                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 389                 reg = <0xff190000 0x100>;
 390                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 391                 reg-shift = <2>;
 392                 reg-io-width = <4>;
 393                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 394                 clock-names = "baudclk", "apb_pclk";
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&uart1_xfer>;
 397                 status = "disabled";
 398         };
 399
 400         uart2: serial@ff690000 {
 401                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 402                 reg = <0xff690000 0x100>;
 403                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 404                 reg-shift = <2>;
 405                 reg-io-width = <4>;
 406                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 407                 clock-names = "baudclk", "apb_pclk";
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&uart2_xfer>;
 410                 status = "disabled";
 411         };
 412
 413         uart3: serial@ff1b0000 {
 414                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 415                 reg = <0xff1b0000 0x100>;
 416                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 417                 reg-shift = <2>;
 418                 reg-io-width = <4>;
 419                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 420                 clock-names = "baudclk", "apb_pclk";
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&uart3_xfer>;
 423                 status = "disabled";
 424         };
 425
 426         uart4: serial@ff1c0000 {
 427                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 428                 reg = <0xff1c0000 0x100>;
 429                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 430                 reg-shift = <2>;
 431                 reg-io-width = <4>;
 432                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 433                 clock-names = "baudclk", "apb_pclk";
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&uart4_xfer>;
 436                 status = "disabled";
 437         };
 438
 439         thermal-zones {
 440                 #include "rk3288-thermal.dtsi"
 441         };
 442
 443         tsadc: tsadc@ff280000 {
 444                 compatible = "rockchip,rk3288-tsadc";
 445                 reg = <0xff280000 0x100>;
 446                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 447                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 448                 clock-names = "tsadc", "apb_pclk";
 449                 resets = <&cru SRST_TSADC>;
 450                 reset-names = "tsadc-apb";
 451                 pinctrl-names = "default";
 452                 pinctrl-0 = <&otp_out>;
 453                 #thermal-sensor-cells = <1>;
 454                 rockchip,hw-tshut-temp = <95000>;
 455                 status = "disabled";
 456         };
 457
 458         gmac: ethernet@ff290000 {
 459                 compatible = "rockchip,rk3288-gmac";
 460                 reg = <0xff290000 0x10000>;
 461                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 462                 interrupt-names = "macirq";
 463                 rockchip,grf = <&grf>;
 464                 clocks = <&cru SCLK_MAC>,
 465                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 466                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 467                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 468                 clock-names = "stmmaceth",
 469                         "mac_clk_rx", "mac_clk_tx",
 470                         "clk_mac_ref", "clk_mac_refout",
 471                         "aclk_mac", "pclk_mac";
 472                 resets = <&cru SRST_MAC>;
 473                 reset-names = "stmmaceth";
 474                 status = "disabled";
 475         };
 476
 477         usb_host0_ehci: usb@ff500000 {
 478                 compatible = "generic-ehci";
 479                 reg = <0xff500000 0x100>;
 480                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 481                 clocks = <&cru HCLK_USBHOST0>;
 482                 clock-names = "usbhost";
 483                 phys = <&usbphy1>;
 484                 phy-names = "usb";
 485                 status = "disabled";
 486         };
 487
 488         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 489
 490         usb_host1: usb@ff540000 {
 491                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 492                                 "snps,dwc2";
 493                 reg = <0xff540000 0x40000>;
 494                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 495                 clocks = <&cru HCLK_USBHOST1>;
 496                 clock-names = "otg";
 497                 dr_mode = "host";
 498                 phys = <&usbphy2>;
 499                 phy-names = "usb2-phy";
 500                 status = "disabled";
 501         };
 502
 503         usb_otg: usb@ff580000 {
 504                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 505                                 "snps,dwc2";
 506                 reg = <0xff580000 0x40000>;
 507                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&cru HCLK_OTG0>;
 509                 clock-names = "otg";
 510                 dr_mode = "otg";
 511                 g-np-tx-fifo-size = <16>;
 512                 g-rx-fifo-size = <275>;
 513                 g-tx-fifo-size = <256 128 128 64 64 32>;
 514                 g-use-dma;
 515                 phys = <&usbphy0>;
 516                 phy-names = "usb2-phy";
 517                 status = "disabled";
 518         };
 519
 520         usb_hsic: usb@ff5c0000 {
 521                 compatible = "generic-ehci";
 522                 reg = <0xff5c0000 0x100>;
 523                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks = <&cru HCLK_HSIC>;
 525                 clock-names = "usbhost";
 526                 status = "disabled";
 527         };
 528
 529         i2c0: i2c@ff650000 {
 530                 compatible = "rockchip,rk3288-i2c";
 531                 reg = <0xff650000 0x1000>;
 532                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 clock-names = "i2c";
 536                 clocks = <&cru PCLK_I2C0>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c0_xfer>;
 539                 status = "disabled";
 540         };
 541
 542         i2c2: i2c@ff660000 {
 543                 compatible = "rockchip,rk3288-i2c";
 544                 reg = <0xff660000 0x1000>;
 545                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 546                 #address-cells = <1>;
 547                 #size-cells = <0>;
 548                 clock-names = "i2c";
 549                 clocks = <&cru PCLK_I2C2>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&i2c2_xfer>;
 552                 status = "disabled";
 553         };
 554
 555         pwm0: pwm@ff680000 {
 556                 compatible = "rockchip,rk3288-pwm";
 557                 reg = <0xff680000 0x10>;
 558                 #pwm-cells = <3>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&pwm0_pin>;
 561                 clocks = <&cru PCLK_PWM>;
 562                 clock-names = "pwm";
 563                 status = "disabled";
 564         };
 565
 566         pwm1: pwm@ff680010 {
 567                 compatible = "rockchip,rk3288-pwm";
 568                 reg = <0xff680010 0x10>;
 569                 #pwm-cells = <3>;
 570                 pinctrl-names = "default";
 571                 pinctrl-0 = <&pwm1_pin>;
 572                 clocks = <&cru PCLK_PWM>;
 573                 clock-names = "pwm";
 574                 status = "disabled";
 575         };
 576
 577         pwm2: pwm@ff680020 {
 578                 compatible = "rockchip,rk3288-pwm";
 579                 reg = <0xff680020 0x10>;
 580                 #pwm-cells = <3>;
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&pwm2_pin>;
 583                 clocks = <&cru PCLK_PWM>;
 584                 clock-names = "pwm";
 585                 status = "disabled";
 586         };
 587
 588         pwm3: pwm@ff680030 {
 589                 compatible = "rockchip,rk3288-pwm";
 590                 reg = <0xff680030 0x10>;
 591                 #pwm-cells = <2>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&pwm3_pin>;
 594                 clocks = <&cru PCLK_PWM>;
 595                 clock-names = "pwm";
 596                 status = "disabled";
 597         };
 598
 599         bus_intmem@ff700000 {
 600                 compatible = "mmio-sram";
 601                 reg = <0xff700000 0x18000>;
 602                 #address-cells = <1>;
 603                 #size-cells = <1>;
 604                 ranges = <0 0xff700000 0x18000>;
 605                 smp-sram@0 {
 606                         compatible = "rockchip,rk3066-smp-sram";
 607                         reg = <0x00 0x10>;
 608                 };
 609         };
 610
 611         sram@ff720000 {
 612                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 613                 reg = <0xff720000 0x1000>;
 614         };
 615
 616         pmu: power-management@ff730000 {
 617                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 618                 reg = <0xff730000 0x100>;
 619
 620                 power: power-controller {
 621                         compatible = "rockchip,rk3288-power-controller";
 622                         #power-domain-cells = <1>;
 623                         #address-cells = <1>;
 624                         #size-cells = <0>;
 625
 626                         /*
 627                          * Note: Although SCLK_* are the working clocks
 628                          * of device without including on the NOC, needed for
 629                          * synchronous reset.
 630                          *
 631                          * The clocks on the which NOC:
 632                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 633                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 634                          * ACLK_RGA is on ACLK_RGA_NIU.
 635                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 636                          *
 637                          * Which clock are device clocks:
 638                          *      clocks          devices
 639                          *      *_IEP           IEP:Image Enhancement Processor
 640                          *      *_ISP           ISP:Image Signal Processing
 641                          *      *_VIP           VIP:Video Input Processor
 642                          *      *_VOP*          VOP:Visual Output Processor
 643                          *      *_RGA           RGA
 644                          *      *_EDP*          EDP
 645                          *      *_LVDS_*        LVDS
 646                          *      *_HDMI          HDMI
 647                          *      *_MIPI_*        MIPI
 648                          */
 649                         pd_vio {
 650                                 reg = <RK3288_PD_VIO>;
 651                                 clocks = <&cru ACLK_IEP>,
 652                                          <&cru ACLK_ISP>,
 653                                          <&cru ACLK_RGA>,
 654                                          <&cru ACLK_VIP>,
 655                                          <&cru ACLK_VOP0>,
 656                                          <&cru ACLK_VOP1>,
 657                                          <&cru DCLK_VOP0>,
 658                                          <&cru DCLK_VOP1>,
 659                                          <&cru HCLK_IEP>,
 660                                          <&cru HCLK_ISP>,
 661                                          <&cru HCLK_RGA>,
 662                                          <&cru HCLK_VIP>,
 663                                          <&cru HCLK_VOP0>,
 664                                          <&cru HCLK_VOP1>,
 665                                          <&cru PCLK_EDP_CTRL>,
 666                                          <&cru PCLK_HDMI_CTRL>,
 667                                          <&cru PCLK_LVDS_PHY>,
 668                                          <&cru PCLK_MIPI_CSI>,
 669                                          <&cru PCLK_MIPI_DSI0>,
 670                                          <&cru PCLK_MIPI_DSI1>,
 671                                          <&cru SCLK_EDP_24M>,
 672                                          <&cru SCLK_EDP>,
 673                                          <&cru SCLK_ISP_JPE>,
 674                                          <&cru SCLK_ISP>,
 675                                          <&cru SCLK_RGA>;
 676                         };
 677
 678                         /*
 679                          * Note: The following 3 are HEVC(H.265) clocks,
 680                          * and on the ACLK_HEVC_NIU (NOC).
 681                          */
 682                         pd_hevc {
 683                                 reg = <RK3288_PD_HEVC>;
 684                                 clocks = <&cru ACLK_HEVC>,
 685                                          <&cru SCLK_HEVC_CABAC>,
 686                                          <&cru SCLK_HEVC_CORE>;
 687                         };
 688
 689                         /*
 690                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 691                          * (video endecoder & decoder) clocks that on the
 692                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 693                          */
 694                         pd_video {
 695                                 reg = <RK3288_PD_VIDEO>;
 696                                 clocks = <&cru ACLK_VCODEC>,
 697                                          <&cru HCLK_VCODEC>;
 698                         };
 699
 700                         /*
 701                          * Note: ACLK_GPU is the GPU clock,
 702                          * and on the ACLK_GPU_NIU (NOC).
 703                          */
 704                         pd_gpu {
 705                                 reg = <RK3288_PD_GPU>;
 706                                 clocks = <&cru ACLK_GPU>;
 707                         };
 708                 };
 709         };
 710
 711         sgrf: syscon@ff740000 {
 712                 compatible = "rockchip,rk3288-sgrf", "syscon";
 713                 reg = <0xff740000 0x1000>;
 714         };
 715
 716         cru: clock-controller@ff760000 {
 717                 compatible = "rockchip,rk3288-cru";
 718                 reg = <0xff760000 0x1000>;
 719                 rockchip,grf = <&grf>;
 720                 #clock-cells = <1>;
 721                 #reset-cells = <1>;
 722                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 723                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 724                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 725                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 726                                   <&cru PCLK_PERI>;
 727                 assigned-clock-rates = <594000000>, <400000000>,
 728                                        <500000000>, <300000000>,
 729                                        <150000000>, <75000000>,
 730                                        <300000000>, <150000000>,
 731                                        <75000000>;
 732         };
 733
 734         grf: syscon@ff770000 {
 735                 compatible = "rockchip,rk3288-grf", "syscon";
 736                 reg = <0xff770000 0x1000>;
 737         };
 738
 739         wdt: watchdog@ff800000 {
 740                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 741                 reg = <0xff800000 0x100>;
 742                 clocks = <&cru PCLK_WDT>;
 743                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 744                 status = "disabled";
 745         };
 746
 747         i2s: i2s@ff890000 {
 748                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 749                 reg = <0xff890000 0x10000>;
 750                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 751                 #address-cells = <1>;
 752                 #size-cells = <0>;
 753                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 754                 dma-names = "tx", "rx";
 755                 clock-names = "i2s_hclk", "i2s_clk";
 756                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 757                 pinctrl-names = "default";
 758                 pinctrl-0 = <&i2s0_bus>;
 759                 status = "disabled";
 760         };
 761
 762         vopb: vop@ff930000 {
 763                 compatible = "rockchip,rk3288-vop";
 764                 reg = <0xff930000 0x19c>;
 765                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 766                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 767                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 768                 power-domains = <&power RK3288_PD_VIO>;
 769                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 770                 reset-names = "axi", "ahb", "dclk";
 771                 iommus = <&vopb_mmu>;
 772                 status = "disabled";
 773
 774                 vopb_out: port {
 775                         #address-cells = <1>;
 776                         #size-cells = <0>;
 777
 778                         vopb_out_hdmi: endpoint@0 {
 779                                 reg = <0>;
 780                                 remote-endpoint = <&hdmi_in_vopb>;
 781                         };
 782                 };
 783         };
 784
 785         vopb_mmu: iommu@ff930300 {
 786                 compatible = "rockchip,iommu";
 787                 reg = <0xff930300 0x100>;
 788                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 789                 interrupt-names = "vopb_mmu";
 790                 power-domains = <&power RK3288_PD_VIO>;
 791                 #iommu-cells = <0>;
 792                 status = "disabled";
 793         };
 794
 795         vopl: vop@ff940000 {
 796                 compatible = "rockchip,rk3288-vop";
 797                 reg = <0xff940000 0x19c>;
 798                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 799                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 800                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 801                 power-domains = <&power RK3288_PD_VIO>;
 802                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 803                 reset-names = "axi", "ahb", "dclk";
 804                 iommus = <&vopl_mmu>;
 805                 status = "disabled";
 806
 807                 vopl_out: port {
 808                         #address-cells = <1>;
 809                         #size-cells = <0>;
 810
 811                         vopl_out_hdmi: endpoint@0 {
 812                                 reg = <0>;
 813                                 remote-endpoint = <&hdmi_in_vopl>;
 814                         };
 815                 };
 816         };
 817
 818         vopl_mmu: iommu@ff940300 {
 819                 compatible = "rockchip,iommu";
 820                 reg = <0xff940300 0x100>;
 821                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 822                 interrupt-names = "vopl_mmu";
 823                 power-domains = <&power RK3288_PD_VIO>;
 824                 #iommu-cells = <0>;
 825                 status = "disabled";
 826         };
 827
 828         hdmi: hdmi@ff980000 {
 829                 compatible = "rockchip,rk3288-dw-hdmi";
 830                 reg = <0xff980000 0x20000>;
 831                 reg-io-width = <4>;
 832                 rockchip,grf = <&grf>;
 833                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 834                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 835                 clock-names = "iahb", "isfr";
 836                 power-domains = <&power RK3288_PD_VIO>;
 837                 status = "disabled";
 838
 839                 ports {
 840                         hdmi_in: port {
 841                                 #address-cells = <1>;
 842                                 #size-cells = <0>;
 843                                 hdmi_in_vopb: endpoint@0 {
 844                                         reg = <0>;
 845                                         remote-endpoint = <&vopb_out_hdmi>;
 846                                 };
 847                                 hdmi_in_vopl: endpoint@1 {
 848                                         reg = <1>;
 849                                         remote-endpoint = <&vopl_out_hdmi>;
 850                                 };
 851                         };
 852                 };
 853         };
 854
 855         gic: interrupt-controller@ffc01000 {
 856                 compatible = "arm,gic-400";
 857                 interrupt-controller;
 858                 #interrupt-cells = <3>;
 859                 #address-cells = <0>;
 860
 861                 reg = <0xffc01000 0x1000>,
 862                       <0xffc02000 0x1000>,
 863                       <0xffc04000 0x2000>,
 864                       <0xffc06000 0x2000>;
 865                 interrupts = <GIC_PPI 9 0xf04>;
 866         };
 867
 868         usbphy: phy {
 869                 compatible = "rockchip,rk3288-usb-phy";
 870                 rockchip,grf = <&grf>;
 871                 #address-cells = <1>;
 872                 #size-cells = <0>;
 873                 status = "disabled";
 874
 875                 usbphy0: usb-phy0 {
 876                         #phy-cells = <0>;
 877                         reg = <0x320>;
 878                         clocks = <&cru SCLK_OTGPHY0>;
 879                         clock-names = "phyclk";
 880                 };
 881
 882                 usbphy1: usb-phy1 {
 883                         #phy-cells = <0>;
 884                         reg = <0x334>;
 885                         clocks = <&cru SCLK_OTGPHY1>;
 886                         clock-names = "phyclk";
 887                 };
 888
 889                 usbphy2: usb-phy2 {
 890                         #phy-cells = <0>;
 891                         reg = <0x348>;
 892                         clocks = <&cru SCLK_OTGPHY2>;
 893                         clock-names = "phyclk";
 894                 };
 895         };
 896
 897         pinctrl: pinctrl {
 898                 compatible = "rockchip,rk3288-pinctrl";
 899                 rockchip,grf = <&grf>;
 900                 rockchip,pmu = <&pmu>;
 901                 #address-cells = <1>;
 902                 #size-cells = <1>;
 903                 ranges;
 904
 905                 gpio0: gpio0@ff750000 {
 906                         compatible = "rockchip,gpio-bank";
 907                         reg =   <0xff750000 0x100>;
 908                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 909                         clocks = <&cru PCLK_GPIO0>;
 910
 911                         gpio-controller;
 912                         #gpio-cells = <2>;
 913
 914                         interrupt-controller;
 915                         #interrupt-cells = <2>;
 916                 };
 917
 918                 gpio1: gpio1@ff780000 {
 919                         compatible = "rockchip,gpio-bank";
 920                         reg = <0xff780000 0x100>;
 921                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 922                         clocks = <&cru PCLK_GPIO1>;
 923
 924                         gpio-controller;
 925                         #gpio-cells = <2>;
 926
 927                         interrupt-controller;
 928                         #interrupt-cells = <2>;
 929                 };
 930
 931                 gpio2: gpio2@ff790000 {
 932                         compatible = "rockchip,gpio-bank";
 933                         reg = <0xff790000 0x100>;
 934                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 935                         clocks = <&cru PCLK_GPIO2>;
 936
 937                         gpio-controller;
 938                         #gpio-cells = <2>;
 939
 940                         interrupt-controller;
 941                         #interrupt-cells = <2>;
 942                 };
 943
 944                 gpio3: gpio3@ff7a0000 {
 945                         compatible = "rockchip,gpio-bank";
 946                         reg = <0xff7a0000 0x100>;
 947                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 948                         clocks = <&cru PCLK_GPIO3>;
 949
 950                         gpio-controller;
 951                         #gpio-cells = <2>;
 952
 953                         interrupt-controller;
 954                         #interrupt-cells = <2>;
 955                 };
 956
 957                 gpio4: gpio4@ff7b0000 {
 958                         compatible = "rockchip,gpio-bank";
 959                         reg = <0xff7b0000 0x100>;
 960                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 961                         clocks = <&cru PCLK_GPIO4>;
 962
 963                         gpio-controller;
 964                         #gpio-cells = <2>;
 965
 966                         interrupt-controller;
 967                         #interrupt-cells = <2>;
 968                 };
 969
 970                 gpio5: gpio5@ff7c0000 {
 971                         compatible = "rockchip,gpio-bank";
 972                         reg = <0xff7c0000 0x100>;
 973                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 974                         clocks = <&cru PCLK_GPIO5>;
 975
 976                         gpio-controller;
 977                         #gpio-cells = <2>;
 978
 979                         interrupt-controller;
 980                         #interrupt-cells = <2>;
 981                 };
 982
 983                 gpio6: gpio6@ff7d0000 {
 984                         compatible = "rockchip,gpio-bank";
 985                         reg = <0xff7d0000 0x100>;
 986                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 987                         clocks = <&cru PCLK_GPIO6>;
 988
 989                         gpio-controller;
 990                         #gpio-cells = <2>;
 991
 992                         interrupt-controller;
 993                         #interrupt-cells = <2>;
 994                 };
 995
 996                 gpio7: gpio7@ff7e0000 {
 997                         compatible = "rockchip,gpio-bank";
 998                         reg = <0xff7e0000 0x100>;
 999                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1000                         clocks = <&cru PCLK_GPIO7>;
1001
1002                         gpio-controller;
1003                         #gpio-cells = <2>;
1004
1005                         interrupt-controller;
1006                         #interrupt-cells = <2>;
1007                 };
1008
1009                 gpio8: gpio8@ff7f0000 {
1010                         compatible = "rockchip,gpio-bank";
1011                         reg = <0xff7f0000 0x100>;
1012                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1013                         clocks = <&cru PCLK_GPIO8>;
1014
1015                         gpio-controller;
1016                         #gpio-cells = <2>;
1017
1018                         interrupt-controller;
1019                         #interrupt-cells = <2>;
1020                 };
1021
1022                 hdmi {
1023                         hdmi_ddc: hdmi-ddc {
1024                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1025                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1026                         };
1027                 };
1028
1029                 pcfg_pull_up: pcfg-pull-up {
1030                         bias-pull-up;
1031                 };
1032
1033                 pcfg_pull_down: pcfg-pull-down {
1034                         bias-pull-down;
1035                 };
1036
1037                 pcfg_pull_none: pcfg-pull-none {
1038                         bias-disable;
1039                 };
1040
1041                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1042                         bias-disable;
1043                         drive-strength = <12>;
1044                 };
1045
1046                 sleep {
1047                         global_pwroff: global-pwroff {
1048                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1049                         };
1050
1051                         ddrio_pwroff: ddrio-pwroff {
1052                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1053                         };
1054
1055                         ddr0_retention: ddr0-retention {
1056                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1057                         };
1058
1059                         ddr1_retention: ddr1-retention {
1060                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1061                         };
1062                 };
1063
1064                 i2c0 {
1065                         i2c0_xfer: i2c0-xfer {
1066                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1067                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1068                         };
1069                 };
1070
1071                 i2c1 {
1072                         i2c1_xfer: i2c1-xfer {
1073                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1074                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1075                         };
1076                 };
1077
1078                 i2c2 {
1079                         i2c2_xfer: i2c2-xfer {
1080                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1081                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1082                         };
1083                 };
1084
1085                 i2c3 {
1086                         i2c3_xfer: i2c3-xfer {
1087                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1088                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1089                         };
1090                 };
1091
1092                 i2c4 {
1093                         i2c4_xfer: i2c4-xfer {
1094                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1095                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1096                         };
1097                 };
1098
1099                 i2c5 {
1100                         i2c5_xfer: i2c5-xfer {
1101                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1102                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1103                         };
1104                 };
1105
1106                 i2s0 {
1107                         i2s0_bus: i2s0-bus {
1108                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1109                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1110                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1111                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1112                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1113                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1114                         };
1115                 };
1116
1117                 sdmmc {
1118                         sdmmc_clk: sdmmc-clk {
1119                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1120                         };
1121
1122                         sdmmc_cmd: sdmmc-cmd {
1123                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1124                         };
1125
1126                         sdmmc_cd: sdmcc-cd {
1127                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1128                         };
1129
1130                         sdmmc_bus1: sdmmc-bus1 {
1131                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1132                         };
1133
1134                         sdmmc_bus4: sdmmc-bus4 {
1135                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1136                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1137                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1138                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1139                         };
1140                 };
1141
1142                 sdio0 {
1143                         sdio0_bus1: sdio0-bus1 {
1144                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1145                         };
1146
1147                         sdio0_bus4: sdio0-bus4 {
1148                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1149                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1150                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1151                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1152                         };
1153
1154                         sdio0_cmd: sdio0-cmd {
1155                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1156                         };
1157
1158                         sdio0_clk: sdio0-clk {
1159                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1160                         };
1161
1162                         sdio0_cd: sdio0-cd {
1163                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1164                         };
1165
1166                         sdio0_wp: sdio0-wp {
1167                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1168                         };
1169
1170                         sdio0_pwr: sdio0-pwr {
1171                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1172                         };
1173
1174                         sdio0_bkpwr: sdio0-bkpwr {
1175                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1176                         };
1177
1178                         sdio0_int: sdio0-int {
1179                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1180                         };
1181                 };
1182
1183                 sdio1 {
1184                         sdio1_bus1: sdio1-bus1 {
1185                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1186                         };
1187
1188                         sdio1_bus4: sdio1-bus4 {
1189                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1190                                                 <3 25 4 &pcfg_pull_up>,
1191                                                 <3 26 4 &pcfg_pull_up>,
1192                                                 <3 27 4 &pcfg_pull_up>;
1193                         };
1194
1195                         sdio1_cd: sdio1-cd {
1196                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1197                         };
1198
1199                         sdio1_wp: sdio1-wp {
1200                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1201                         };
1202
1203                         sdio1_bkpwr: sdio1-bkpwr {
1204                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1205                         };
1206
1207                         sdio1_int: sdio1-int {
1208                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1209                         };
1210
1211                         sdio1_cmd: sdio1-cmd {
1212                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1213                         };
1214
1215                         sdio1_clk: sdio1-clk {
1216                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1217                         };
1218
1219                         sdio1_pwr: sdio1-pwr {
1220                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1221                         };
1222                 };
1223
1224                 emmc {
1225                         emmc_clk: emmc-clk {
1226                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1227                         };
1228
1229                         emmc_cmd: emmc-cmd {
1230                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1231                         };
1232
1233                         emmc_pwr: emmc-pwr {
1234                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1235                         };
1236
1237                         emmc_bus1: emmc-bus1 {
1238                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1239                         };
1240
1241                         emmc_bus4: emmc-bus4 {
1242                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1243                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1244                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1245                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1246                         };
1247
1248                         emmc_bus8: emmc-bus8 {
1249                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1250                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1251                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1252                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1253                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1254                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1255                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1256                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1257                         };
1258                 };
1259
1260                 spi0 {
1261                         spi0_clk: spi0-clk {
1262                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1263                         };
1264                         spi0_cs0: spi0-cs0 {
1265                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1266                         };
1267                         spi0_tx: spi0-tx {
1268                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1269                         };
1270                         spi0_rx: spi0-rx {
1271                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1272                         };
1273                         spi0_cs1: spi0-cs1 {
1274                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1275                         };
1276                 };
1277                 spi1 {
1278                         spi1_clk: spi1-clk {
1279                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1280                         };
1281                         spi1_cs0: spi1-cs0 {
1282                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1283                         };
1284                         spi1_rx: spi1-rx {
1285                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1286                         };
1287                         spi1_tx: spi1-tx {
1288                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1289                         };
1290                 };
1291
1292                 spi2 {
1293                         spi2_cs1: spi2-cs1 {
1294                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1295                         };
1296                         spi2_clk: spi2-clk {
1297                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1298                         };
1299                         spi2_cs0: spi2-cs0 {
1300                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1301                         };
1302                         spi2_rx: spi2-rx {
1303                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1304                         };
1305                         spi2_tx: spi2-tx {
1306                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1307                         };
1308                 };
1309
1310                 uart0 {
1311                         uart0_xfer: uart0-xfer {
1312                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1313                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1314                         };
1315
1316                         uart0_cts: uart0-cts {
1317                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1318                         };
1319
1320                         uart0_rts: uart0-rts {
1321                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323                 };
1324
1325                 uart1 {
1326                         uart1_xfer: uart1-xfer {
1327                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1328                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1329                         };
1330
1331                         uart1_cts: uart1-cts {
1332                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1333                         };
1334
1335                         uart1_rts: uart1-rts {
1336                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1337                         };
1338                 };
1339
1340                 uart2 {
1341                         uart2_xfer: uart2-xfer {
1342                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1343                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345                         /* no rts / cts for uart2 */
1346                 };
1347
1348                 uart3 {
1349                         uart3_xfer: uart3-xfer {
1350                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1351                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1352                         };
1353
1354                         uart3_cts: uart3-cts {
1355                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1356                         };
1357
1358                         uart3_rts: uart3-rts {
1359                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1360                         };
1361                 };
1362
1363                 uart4 {
1364                         uart4_xfer: uart4-xfer {
1365                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1366                                                 <5 13 3 &pcfg_pull_none>;
1367                         };
1368
1369                         uart4_cts: uart4-cts {
1370                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1371                         };
1372
1373                         uart4_rts: uart4-rts {
1374                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1375                         };
1376                 };
1377
1378                 tsadc {
1379                         otp_out: otp-out {
1380                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1381                         };
1382                 };
1383
1384                 pwm0 {
1385                         pwm0_pin: pwm0-pin {
1386                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1387                         };
1388                 };
1389
1390                 pwm1 {
1391                         pwm1_pin: pwm1-pin {
1392                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1393                         };
1394                 };
1395
1396                 pwm2 {
1397                         pwm2_pin: pwm2-pin {
1398                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1399                         };
1400                 };
1401
1402                 pwm3 {
1403                         pwm3_pin: pwm3-pin {
1404                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1405                         };
1406                 };
1407
1408                 gmac {
1409                         rgmii_pins: rgmii-pins {
1410                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1411                                                 <3 31 3 &pcfg_pull_none>,
1412                                                 <3 26 3 &pcfg_pull_none>,
1413                                                 <3 27 3 &pcfg_pull_none>,
1414                                                 <3 28 3 &pcfg_pull_none_12ma>,
1415                                                 <3 29 3 &pcfg_pull_none_12ma>,
1416                                                 <3 24 3 &pcfg_pull_none_12ma>,
1417                                                 <3 25 3 &pcfg_pull_none_12ma>,
1418                                                 <4 0 3 &pcfg_pull_none>,
1419                                                 <4 5 3 &pcfg_pull_none>,
1420                                                 <4 6 3 &pcfg_pull_none>,
1421                                                 <4 9 3 &pcfg_pull_none_12ma>,
1422                                                 <4 4 3 &pcfg_pull_none_12ma>,
1423                                                 <4 1 3 &pcfg_pull_none>,
1424                                                 <4 3 3 &pcfg_pull_none>;
1425                         };
1426
1427                         rmii_pins: rmii-pins {
1428                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1429                                                 <3 31 3 &pcfg_pull_none>,
1430                                                 <3 28 3 &pcfg_pull_none>,
1431                                                 <3 29 3 &pcfg_pull_none>,
1432                                                 <4 0 3 &pcfg_pull_none>,
1433                                                 <4 5 3 &pcfg_pull_none>,
1434                                                 <4 4 3 &pcfg_pull_none>,
1435                                                 <4 1 3 &pcfg_pull_none>,
1436                                                 <4 2 3 &pcfg_pull_none>,
1437                                                 <4 3 3 &pcfg_pull_none>;
1438                         };
1439                 };
1440         };
1441 };