arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /include/ "skeleton.dtsi"
  14
  15 / {
  16         interrupt-parent = <&intc>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21                 cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a8";
  24                         reg = <0x0>;
  25                 };
  26         };
  27
  28         memory {
  29                 reg = <0x40000000 0x80000000>;
  30         };
  31
  32         clocks {
  33                 #address-cells = <1>;
  34                 #size-cells = <1>;
  35                 ranges;
  36
  37                 /*
  38                  * This is a dummy clock, to be used as placeholder on
  39                  * other mux clocks when a specific parent clock is not
  40                  * yet implemented. It should be dropped when the driver
  41                  * is complete.
  42                  */
  43                 dummy: dummy {
  44                         #clock-cells = <0>;
  45                         compatible = "fixed-clock";
  46                         clock-frequency = <0>;
  47                 };
  48
  49                 osc24M: osc24M@01c20050 {
  50                         #clock-cells = <0>;
  51                         compatible = "allwinner,sun4i-osc-clk";
  52                         reg = <0x01c20050 0x4>;
  53                         clock-frequency = <24000000>;
  54                 };
  55
  56                 osc32k: osc32k {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <32768>;
  60                 };
  61
  62                 pll1: pll1@01c20000 {
  63                         #clock-cells = <0>;
  64                         compatible = "allwinner,sun4i-pll1-clk";
  65                         reg = <0x01c20000 0x4>;
  66                         clocks = <&osc24M>;
  67                 };
  68
  69                 pll4: pll4@01c20018 {
  70                         #clock-cells = <0>;
  71                         compatible = "allwinner,sun4i-pll1-clk";
  72                         reg = <0x01c20018 0x4>;
  73                         clocks = <&osc24M>;
  74                 };
  75
  76                 /* dummy is 200M */
  77                 cpu: cpu@01c20054 {
  78                         #clock-cells = <0>;
  79                         compatible = "allwinner,sun4i-cpu-clk";
  80                         reg = <0x01c20054 0x4>;
  81                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  82                 };
  83
  84                 axi: axi@01c20054 {
  85                         #clock-cells = <0>;
  86                         compatible = "allwinner,sun4i-axi-clk";
  87                         reg = <0x01c20054 0x4>;
  88                         clocks = <&cpu>;
  89                 };
  90
  91                 axi_gates: axi_gates@01c2005c {
  92                         #clock-cells = <1>;
  93                         compatible = "allwinner,sun4i-axi-gates-clk";
  94                         reg = <0x01c2005c 0x4>;
  95                         clocks = <&axi>;
  96                         clock-output-names = "axi_dram";
  97                 };
  98
  99                 ahb: ahb@01c20054 {
 100                         #clock-cells = <0>;
 101                         compatible = "allwinner,sun4i-ahb-clk";
 102                         reg = <0x01c20054 0x4>;
 103                         clocks = <&axi>;
 104                 };
 105
 106                 ahb_gates: ahb_gates@01c20060 {
 107                         #clock-cells = <1>;
 108                         compatible = "allwinner,sun4i-ahb-gates-clk";
 109                         reg = <0x01c20060 0x8>;
 110                         clocks = <&ahb>;
 111                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 112                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 113                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 114                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 115                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 116                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 117                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 118                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 119                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 120                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 121                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 122                 };
 123
 124                 apb0: apb0@01c20054 {
 125                         #clock-cells = <0>;
 126                         compatible = "allwinner,sun4i-apb0-clk";
 127                         reg = <0x01c20054 0x4>;
 128                         clocks = <&ahb>;
 129                 };
 130
 131                 apb0_gates: apb0_gates@01c20068 {
 132                         #clock-cells = <1>;
 133                         compatible = "allwinner,sun4i-apb0-gates-clk";
 134                         reg = <0x01c20068 0x4>;
 135                         clocks = <&apb0>;
 136                         clock-output-names = "apb0_codec", "apb0_spdif",
 137                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 138                                 "apb0_ir1", "apb0_keypad";
 139                 };
 140
 141                 /* dummy is pll62 */
 142                 apb1_mux: apb1_mux@01c20058 {
 143                         #clock-cells = <0>;
 144                         compatible = "allwinner,sun4i-apb1-mux-clk";
 145                         reg = <0x01c20058 0x4>;
 146                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 147                 };
 148
 149                 apb1: apb1@01c20058 {
 150                         #clock-cells = <0>;
 151                         compatible = "allwinner,sun4i-apb1-clk";
 152                         reg = <0x01c20058 0x4>;
 153                         clocks = <&apb1_mux>;
 154                 };
 155
 156                 apb1_gates: apb1_gates@01c2006c {
 157                         #clock-cells = <1>;
 158                         compatible = "allwinner,sun4i-apb1-gates-clk";
 159                         reg = <0x01c2006c 0x4>;
 160                         clocks = <&apb1>;
 161                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 162                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 163                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 164                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 165                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 166                                 "apb1_uart7";
 167                 };
 168         };
 169
 170         soc@01c00000 {
 171                 compatible = "simple-bus";
 172                 #address-cells = <1>;
 173                 #size-cells = <1>;
 174                 ranges;
 175
 176                 emac: ethernet@01c0b000 {
 177                         compatible = "allwinner,sun4i-emac";
 178                         reg = <0x01c0b000 0x1000>;
 179                         interrupts = <55>;
 180                         clocks = <&ahb_gates 17>;
 181                         status = "disabled";
 182                 };
 183
 184                 mdio@01c0b080 {
 185                         compatible = "allwinner,sun4i-mdio";
 186                         reg = <0x01c0b080 0x14>;
 187                         status = "disabled";
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                 };
 191
 192                 intc: interrupt-controller@01c20400 {
 193                         compatible = "allwinner,sun4i-ic";
 194                         reg = <0x01c20400 0x400>;
 195                         interrupt-controller;
 196                         #interrupt-cells = <1>;
 197                 };
 198
 199                 pio: pinctrl@01c20800 {
 200                         compatible = "allwinner,sun4i-a10-pinctrl";
 201                         reg = <0x01c20800 0x400>;
 202                         interrupts = <28>;
 203                         clocks = <&apb0_gates 5>;
 204                         gpio-controller;
 205                         interrupt-controller;
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         #gpio-cells = <3>;
 209
 210                         uart0_pins_a: uart0@0 {
 211                                 allwinner,pins = "PB22", "PB23";
 212                                 allwinner,function = "uart0";
 213                                 allwinner,drive = <0>;
 214                                 allwinner,pull = <0>;
 215                         };
 216
 217                         uart0_pins_b: uart0@1 {
 218                                 allwinner,pins = "PF2", "PF4";
 219                                 allwinner,function = "uart0";
 220                                 allwinner,drive = <0>;
 221                                 allwinner,pull = <0>;
 222                         };
 223
 224                         uart1_pins_a: uart1@0 {
 225                                 allwinner,pins = "PA10", "PA11";
 226                                 allwinner,function = "uart1";
 227                                 allwinner,drive = <0>;
 228                                 allwinner,pull = <0>;
 229                         };
 230
 231                         i2c0_pins_a: i2c0@0 {
 232                                 allwinner,pins = "PB0", "PB1";
 233                                 allwinner,function = "i2c0";
 234                                 allwinner,drive = <0>;
 235                                 allwinner,pull = <0>;
 236                         };
 237
 238                         i2c1_pins_a: i2c1@0 {
 239                                 allwinner,pins = "PB18", "PB19";
 240                                 allwinner,function = "i2c1";
 241                                 allwinner,drive = <0>;
 242                                 allwinner,pull = <0>;
 243                         };
 244
 245                         i2c2_pins_a: i2c2@0 {
 246                                 allwinner,pins = "PB20", "PB21";
 247                                 allwinner,function = "i2c2";
 248                                 allwinner,drive = <0>;
 249                                 allwinner,pull = <0>;
 250                         };
 251
 252                         emac_pins_a: emac0@0 {
 253                                 allwinner,pins = "PA0", "PA1", "PA2",
 254                                                 "PA3", "PA4", "PA5", "PA6",
 255                                                 "PA7", "PA8", "PA9", "PA10",
 256                                                 "PA11", "PA12", "PA13", "PA14",
 257                                                 "PA15", "PA16";
 258                                 allwinner,function = "emac";
 259                                 allwinner,drive = <0>;
 260                                 allwinner,pull = <0>;
 261                         };
 262                 };
 263
 264                 timer@01c20c00 {
 265                         compatible = "allwinner,sun4i-timer";
 266                         reg = <0x01c20c00 0x90>;
 267                         interrupts = <22>;
 268                         clocks = <&osc24M>;
 269                 };
 270
 271                 wdt: watchdog@01c20c90 {
 272                         compatible = "allwinner,sun4i-wdt";
 273                         reg = <0x01c20c90 0x10>;
 274                 };
 275
 276                 sid: eeprom@01c23800 {
 277                         compatible = "allwinner,sun4i-sid";
 278                         reg = <0x01c23800 0x10>;
 279                 };
 280
 281                 uart0: serial@01c28000 {
 282                         compatible = "snps,dw-apb-uart";
 283                         reg = <0x01c28000 0x400>;
 284                         interrupts = <1>;
 285                         reg-shift = <2>;
 286                         reg-io-width = <4>;
 287                         clocks = <&apb1_gates 16>;
 288                         status = "disabled";
 289                 };
 290
 291                 uart1: serial@01c28400 {
 292                         compatible = "snps,dw-apb-uart";
 293                         reg = <0x01c28400 0x400>;
 294                         interrupts = <2>;
 295                         reg-shift = <2>;
 296                         reg-io-width = <4>;
 297                         clocks = <&apb1_gates 17>;
 298                         status = "disabled";
 299                 };
 300
 301                 uart2: serial@01c28800 {
 302                         compatible = "snps,dw-apb-uart";
 303                         reg = <0x01c28800 0x400>;
 304                         interrupts = <3>;
 305                         reg-shift = <2>;
 306                         reg-io-width = <4>;
 307                         clocks = <&apb1_gates 18>;
 308                         status = "disabled";
 309                 };
 310
 311                 uart3: serial@01c28c00 {
 312                         compatible = "snps,dw-apb-uart";
 313                         reg = <0x01c28c00 0x400>;
 314                         interrupts = <4>;
 315                         reg-shift = <2>;
 316                         reg-io-width = <4>;
 317                         clocks = <&apb1_gates 19>;
 318                         status = "disabled";
 319                 };
 320
 321                 uart4: serial@01c29000 {
 322                         compatible = "snps,dw-apb-uart";
 323                         reg = <0x01c29000 0x400>;
 324                         interrupts = <17>;
 325                         reg-shift = <2>;
 326                         reg-io-width = <4>;
 327                         clocks = <&apb1_gates 20>;
 328                         status = "disabled";
 329                 };
 330
 331                 uart5: serial@01c29400 {
 332                         compatible = "snps,dw-apb-uart";
 333                         reg = <0x01c29400 0x400>;
 334                         interrupts = <18>;
 335                         reg-shift = <2>;
 336                         reg-io-width = <4>;
 337                         clocks = <&apb1_gates 21>;
 338                         status = "disabled";
 339                 };
 340
 341                 uart6: serial@01c29800 {
 342                         compatible = "snps,dw-apb-uart";
 343                         reg = <0x01c29800 0x400>;
 344                         interrupts = <19>;
 345                         reg-shift = <2>;
 346                         reg-io-width = <4>;
 347                         clocks = <&apb1_gates 22>;
 348                         status = "disabled";
 349                 };
 350
 351                 uart7: serial@01c29c00 {
 352                         compatible = "snps,dw-apb-uart";
 353                         reg = <0x01c29c00 0x400>;
 354                         interrupts = <20>;
 355                         reg-shift = <2>;
 356                         reg-io-width = <4>;
 357                         clocks = <&apb1_gates 23>;
 358                         status = "disabled";
 359                 };
 360
 361                 i2c0: i2c@01c2ac00 {
 362                         compatible = "allwinner,sun4i-i2c";
 363                         reg = <0x01c2ac00 0x400>;
 364                         interrupts = <7>;
 365                         clocks = <&apb1_gates 0>;
 366                         clock-frequency = <100000>;
 367                         status = "disabled";
 368                 };
 369
 370                 i2c1: i2c@01c2b000 {
 371                         compatible = "allwinner,sun4i-i2c";
 372                         reg = <0x01c2b000 0x400>;
 373                         interrupts = <8>;
 374                         clocks = <&apb1_gates 1>;
 375                         clock-frequency = <100000>;
 376                         status = "disabled";
 377                 };
 378
 379                 i2c2: i2c@01c2b400 {
 380                         compatible = "allwinner,sun4i-i2c";
 381                         reg = <0x01c2b400 0x400>;
 382                         interrupts = <9>;
 383                         clocks = <&apb1_gates 2>;
 384                         clock-frequency = <100000>;
 385                         status = "disabled";
 386                 };
 387         };
 388 };