arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include "skeleton.dtsi"
  45
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 #include <dt-bindings/dma/sun4i-a10.h>
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50
  51 / {
  52         interrupt-parent = <&intc>;
  53
  54         aliases {
  55                 ethernet0 = &emac;
  56         };
  57
  58         chosen {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 framebuffer@0 {
  64                         compatible = "allwinner,simple-framebuffer",
  65                                      "simple-framebuffer";
  66                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  67                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  68                                  <&ahb_gates 44>;
  69                         status = "disabled";
  70                 };
  71
  72                 framebuffer@1 {
  73                         compatible = "allwinner,simple-framebuffer",
  74                                      "simple-framebuffer";
  75                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  76                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  77                                  <&ahb_gates 44>, <&ahb_gates 46>;
  78                         status = "disabled";
  79                 };
  80
  81                 framebuffer@2 {
  82                         compatible = "allwinner,simple-framebuffer",
  83                                      "simple-framebuffer";
  84                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  85                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  86                                  <&ahb_gates 46>;
  87                         status = "disabled";
  88                 };
  89
  90                 framebuffer@3 {
  91                         compatible = "allwinner,simple-framebuffer",
  92                                      "simple-framebuffer";
  93                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
  94                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  95                                  <&ahb_gates 44>, <&ahb_gates 46>;
  96                         status = "disabled";
  97                 };
  98         };
  99
 100         cpus {
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 cpu0: cpu@0 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a8";
 106                         reg = <0x0>;
 107                         clocks = <&cpu>;
 108                         clock-latency = <244144>; /* 8 32k periods */
 109                         operating-points = <
 110                                 /* kHz    uV */
 111                                 1008000 1400000
 112                                 912000  1350000
 113                                 864000  1300000
 114                                 624000  1250000
 115                                 >;
 116                         #cooling-cells = <2>;
 117                         cooling-min-level = <0>;
 118                         cooling-max-level = <3>;
 119                 };
 120         };
 121
 122         thermal-zones {
 123                 cpu_thermal {
 124                         /* milliseconds */
 125                         polling-delay-passive = <250>;
 126                         polling-delay = <1000>;
 127                         thermal-sensors = <&rtp>;
 128
 129                         cooling-maps {
 130                                 map0 {
 131                                         trip = <&cpu_alert0>;
 132                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 133                                 };
 134                         };
 135
 136                         trips {
 137                                 cpu_alert0: cpu_alert0 {
 138                                         /* milliCelsius */
 139                                         temperature = <850000>;
 140                                         hysteresis = <2000>;
 141                                         type = "passive";
 142                                 };
 143
 144                                 cpu_crit: cpu_crit {
 145                                         /* milliCelsius */
 146                                         temperature = <100000>;
 147                                         hysteresis = <2000>;
 148                                         type = "critical";
 149                                 };
 150                         };
 151                 };
 152         };
 153
 154         memory {
 155                 reg = <0x40000000 0x80000000>;
 156         };
 157
 158         clocks {
 159                 #address-cells = <1>;
 160                 #size-cells = <1>;
 161                 ranges;
 162
 163                 /*
 164                  * This is a dummy clock, to be used as placeholder on
 165                  * other mux clocks when a specific parent clock is not
 166                  * yet implemented. It should be dropped when the driver
 167                  * is complete.
 168                  */
 169                 dummy: dummy {
 170                         #clock-cells = <0>;
 171                         compatible = "fixed-clock";
 172                         clock-frequency = <0>;
 173                 };
 174
 175                 osc24M: clk@01c20050 {
 176                         #clock-cells = <0>;
 177                         compatible = "allwinner,sun4i-a10-osc-clk";
 178                         reg = <0x01c20050 0x4>;
 179                         clock-frequency = <24000000>;
 180                         clock-output-names = "osc24M";
 181                 };
 182
 183                 osc32k: clk@0 {
 184                         #clock-cells = <0>;
 185                         compatible = "fixed-clock";
 186                         clock-frequency = <32768>;
 187                         clock-output-names = "osc32k";
 188                 };
 189
 190                 pll1: clk@01c20000 {
 191                         #clock-cells = <0>;
 192                         compatible = "allwinner,sun4i-a10-pll1-clk";
 193                         reg = <0x01c20000 0x4>;
 194                         clocks = <&osc24M>;
 195                         clock-output-names = "pll1";
 196                 };
 197
 198                 pll2: clk@01c20008 {
 199                         #clock-cells = <1>;
 200                         compatible = "allwinner,sun4i-a10-pll2-clk";
 201                         reg = <0x01c20008 0x8>;
 202                         clocks = <&osc24M>;
 203                         clock-output-names = "pll2-1x", "pll2-2x",
 204                                              "pll2-4x", "pll2-8x";
 205                 };
 206
 207                 pll4: clk@01c20018 {
 208                         #clock-cells = <0>;
 209                         compatible = "allwinner,sun4i-a10-pll1-clk";
 210                         reg = <0x01c20018 0x4>;
 211                         clocks = <&osc24M>;
 212                         clock-output-names = "pll4";
 213                 };
 214
 215                 pll5: clk@01c20020 {
 216                         #clock-cells = <1>;
 217                         compatible = "allwinner,sun4i-a10-pll5-clk";
 218                         reg = <0x01c20020 0x4>;
 219                         clocks = <&osc24M>;
 220                         clock-output-names = "pll5_ddr", "pll5_other";
 221                 };
 222
 223                 pll6: clk@01c20028 {
 224                         #clock-cells = <1>;
 225                         compatible = "allwinner,sun4i-a10-pll6-clk";
 226                         reg = <0x01c20028 0x4>;
 227                         clocks = <&osc24M>;
 228                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 229                 };
 230
 231                 /* dummy is 200M */
 232                 cpu: cpu@01c20054 {
 233                         #clock-cells = <0>;
 234                         compatible = "allwinner,sun4i-a10-cpu-clk";
 235                         reg = <0x01c20054 0x4>;
 236                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 237                         clock-output-names = "cpu";
 238                 };
 239
 240                 axi: axi@01c20054 {
 241                         #clock-cells = <0>;
 242                         compatible = "allwinner,sun4i-a10-axi-clk";
 243                         reg = <0x01c20054 0x4>;
 244                         clocks = <&cpu>;
 245                         clock-output-names = "axi";
 246                 };
 247
 248                 axi_gates: clk@01c2005c {
 249                         #clock-cells = <1>;
 250                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 251                         reg = <0x01c2005c 0x4>;
 252                         clocks = <&axi>;
 253                         clock-indices = <0>;
 254                         clock-output-names = "axi_dram";
 255                 };
 256
 257                 ahb: ahb@01c20054 {
 258                         #clock-cells = <0>;
 259                         compatible = "allwinner,sun4i-a10-ahb-clk";
 260                         reg = <0x01c20054 0x4>;
 261                         clocks = <&axi>;
 262                         clock-output-names = "ahb";
 263                 };
 264
 265                 ahb_gates: clk@01c20060 {
 266                         #clock-cells = <1>;
 267                         compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 268                         reg = <0x01c20060 0x8>;
 269                         clocks = <&ahb>;
 270                         clock-indices = <0>, <1>,
 271                                         <2>, <3>,
 272                                         <4>, <5>, <6>,
 273                                         <7>, <8>, <9>,
 274                                         <10>, <11>, <12>,
 275                                         <13>, <14>, <16>,
 276                                         <17>, <18>, <20>,
 277                                         <21>, <22>, <23>,
 278                                         <24>, <25>, <26>,
 279                                         <32>, <33>, <34>,
 280                                         <35>, <36>, <37>,
 281                                         <40>, <41>, <43>,
 282                                         <44>, <45>,
 283                                         <46>, <47>,
 284                                         <50>, <52>;
 285                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 286                                              "ahb_ohci0", "ahb_ehci1",
 287                                              "ahb_ohci1", "ahb_ss", "ahb_dma",
 288                                              "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 289                                              "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 290                                              "ahb_nand", "ahb_sdram", "ahb_ace",
 291                                              "ahb_emac", "ahb_ts", "ahb_spi0",
 292                                              "ahb_spi1", "ahb_spi2", "ahb_spi3",
 293                                              "ahb_pata", "ahb_sata", "ahb_gps",
 294                                              "ahb_ve", "ahb_tvd", "ahb_tve0",
 295                                              "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
 296                                              "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 297                                              "ahb_de_be0", "ahb_de_be1",
 298                                              "ahb_de_fe0", "ahb_de_fe1",
 299                                              "ahb_mp", "ahb_mali400";
 300                 };
 301
 302                 apb0: apb0@01c20054 {
 303                         #clock-cells = <0>;
 304                         compatible = "allwinner,sun4i-a10-apb0-clk";
 305                         reg = <0x01c20054 0x4>;
 306                         clocks = <&ahb>;
 307                         clock-output-names = "apb0";
 308                 };
 309
 310                 apb0_gates: clk@01c20068 {
 311                         #clock-cells = <1>;
 312                         compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 313                         reg = <0x01c20068 0x4>;
 314                         clocks = <&apb0>;
 315                         clock-indices = <0>, <1>,
 316                                         <2>, <3>,
 317                                         <5>, <6>,
 318                                         <7>, <10>;
 319                         clock-output-names = "apb0_codec", "apb0_spdif",
 320                                              "apb0_ac97", "apb0_iis",
 321                                              "apb0_pio", "apb0_ir0",
 322                                              "apb0_ir1", "apb0_keypad";
 323                 };
 324
 325                 apb1: clk@01c20058 {
 326                         #clock-cells = <0>;
 327                         compatible = "allwinner,sun4i-a10-apb1-clk";
 328                         reg = <0x01c20058 0x4>;
 329                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 330                         clock-output-names = "apb1";
 331                 };
 332
 333                 apb1_gates: clk@01c2006c {
 334                         #clock-cells = <1>;
 335                         compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 336                         reg = <0x01c2006c 0x4>;
 337                         clocks = <&apb1>;
 338                         clock-indices = <0>, <1>,
 339                                         <2>, <4>,
 340                                         <5>, <6>,
 341                                         <7>, <16>,
 342                                         <17>, <18>,
 343                                         <19>, <20>,
 344                                         <21>, <22>,
 345                                         <23>;
 346                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 347                                              "apb1_i2c2", "apb1_can",
 348                                              "apb1_scr", "apb1_ps20",
 349                                              "apb1_ps21", "apb1_uart0",
 350                                              "apb1_uart1", "apb1_uart2",
 351                                              "apb1_uart3", "apb1_uart4",
 352                                              "apb1_uart5", "apb1_uart6",
 353                                              "apb1_uart7";
 354                 };
 355
 356                 nand_clk: clk@01c20080 {
 357                         #clock-cells = <0>;
 358                         compatible = "allwinner,sun4i-a10-mod0-clk";
 359                         reg = <0x01c20080 0x4>;
 360                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 361                         clock-output-names = "nand";
 362                 };
 363
 364                 ms_clk: clk@01c20084 {
 365                         #clock-cells = <0>;
 366                         compatible = "allwinner,sun4i-a10-mod0-clk";
 367                         reg = <0x01c20084 0x4>;
 368                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 369                         clock-output-names = "ms";
 370                 };
 371
 372                 mmc0_clk: clk@01c20088 {
 373                         #clock-cells = <1>;
 374                         compatible = "allwinner,sun4i-a10-mmc-clk";
 375                         reg = <0x01c20088 0x4>;
 376                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 377                         clock-output-names = "mmc0",
 378                                              "mmc0_output",
 379                                              "mmc0_sample";
 380                 };
 381
 382                 mmc1_clk: clk@01c2008c {
 383                         #clock-cells = <1>;
 384                         compatible = "allwinner,sun4i-a10-mmc-clk";
 385                         reg = <0x01c2008c 0x4>;
 386                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 387                         clock-output-names = "mmc1",
 388                                              "mmc1_output",
 389                                              "mmc1_sample";
 390                 };
 391
 392                 mmc2_clk: clk@01c20090 {
 393                         #clock-cells = <1>;
 394                         compatible = "allwinner,sun4i-a10-mmc-clk";
 395                         reg = <0x01c20090 0x4>;
 396                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 397                         clock-output-names = "mmc2",
 398                                              "mmc2_output",
 399                                              "mmc2_sample";
 400                 };
 401
 402                 mmc3_clk: clk@01c20094 {
 403                         #clock-cells = <1>;
 404                         compatible = "allwinner,sun4i-a10-mmc-clk";
 405                         reg = <0x01c20094 0x4>;
 406                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 407                         clock-output-names = "mmc3",
 408                                              "mmc3_output",
 409                                              "mmc3_sample";
 410                 };
 411
 412                 ts_clk: clk@01c20098 {
 413                         #clock-cells = <0>;
 414                         compatible = "allwinner,sun4i-a10-mod0-clk";
 415                         reg = <0x01c20098 0x4>;
 416                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 417                         clock-output-names = "ts";
 418                 };
 419
 420                 ss_clk: clk@01c2009c {
 421                         #clock-cells = <0>;
 422                         compatible = "allwinner,sun4i-a10-mod0-clk";
 423                         reg = <0x01c2009c 0x4>;
 424                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 425                         clock-output-names = "ss";
 426                 };
 427
 428                 spi0_clk: clk@01c200a0 {
 429                         #clock-cells = <0>;
 430                         compatible = "allwinner,sun4i-a10-mod0-clk";
 431                         reg = <0x01c200a0 0x4>;
 432                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 433                         clock-output-names = "spi0";
 434                 };
 435
 436                 spi1_clk: clk@01c200a4 {
 437                         #clock-cells = <0>;
 438                         compatible = "allwinner,sun4i-a10-mod0-clk";
 439                         reg = <0x01c200a4 0x4>;
 440                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 441                         clock-output-names = "spi1";
 442                 };
 443
 444                 spi2_clk: clk@01c200a8 {
 445                         #clock-cells = <0>;
 446                         compatible = "allwinner,sun4i-a10-mod0-clk";
 447                         reg = <0x01c200a8 0x4>;
 448                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 449                         clock-output-names = "spi2";
 450                 };
 451
 452                 pata_clk: clk@01c200ac {
 453                         #clock-cells = <0>;
 454                         compatible = "allwinner,sun4i-a10-mod0-clk";
 455                         reg = <0x01c200ac 0x4>;
 456                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 457                         clock-output-names = "pata";
 458                 };
 459
 460                 ir0_clk: clk@01c200b0 {
 461                         #clock-cells = <0>;
 462                         compatible = "allwinner,sun4i-a10-mod0-clk";
 463                         reg = <0x01c200b0 0x4>;
 464                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 465                         clock-output-names = "ir0";
 466                 };
 467
 468                 ir1_clk: clk@01c200b4 {
 469                         #clock-cells = <0>;
 470                         compatible = "allwinner,sun4i-a10-mod0-clk";
 471                         reg = <0x01c200b4 0x4>;
 472                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 473                         clock-output-names = "ir1";
 474                 };
 475
 476                 usb_clk: clk@01c200cc {
 477                         #clock-cells = <1>;
 478                         #reset-cells = <1>;
 479                         compatible = "allwinner,sun4i-a10-usb-clk";
 480                         reg = <0x01c200cc 0x4>;
 481                         clocks = <&pll6 1>;
 482                         clock-output-names = "usb_ohci0", "usb_ohci1",
 483                                              "usb_phy";
 484                 };
 485
 486                 spi3_clk: clk@01c200d4 {
 487                         #clock-cells = <0>;
 488                         compatible = "allwinner,sun4i-a10-mod0-clk";
 489                         reg = <0x01c200d4 0x4>;
 490                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 491                         clock-output-names = "spi3";
 492                 };
 493         };
 494
 495         soc@01c00000 {
 496                 compatible = "simple-bus";
 497                 #address-cells = <1>;
 498                 #size-cells = <1>;
 499                 ranges;
 500
 501                 sram-controller@01c00000 {
 502                         compatible = "allwinner,sun4i-a10-sram-controller";
 503                         reg = <0x01c00000 0x30>;
 504                         #address-cells = <1>;
 505                         #size-cells = <1>;
 506                         ranges;
 507
 508                         sram_a: sram@00000000 {
 509                                 compatible = "mmio-sram";
 510                                 reg = <0x00000000 0xc000>;
 511                                 #address-cells = <1>;
 512                                 #size-cells = <1>;
 513                                 ranges = <0 0x00000000 0xc000>;
 514
 515                                 emac_sram: sram-section@8000 {
 516                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 517                                         reg = <0x8000 0x4000>;
 518                                         status = "disabled";
 519                                 };
 520                         };
 521
 522                         sram_d: sram@00010000 {
 523                                 compatible = "mmio-sram";
 524                                 reg = <0x00010000 0x1000>;
 525                                 #address-cells = <1>;
 526                                 #size-cells = <1>;
 527                                 ranges = <0 0x00010000 0x1000>;
 528
 529                                 otg_sram: sram-section@0000 {
 530                                         compatible = "allwinner,sun4i-a10-sram-d";
 531                                         reg = <0x0000 0x1000>;
 532                                         status = "disabled";
 533                                 };
 534                         };
 535                 };
 536
 537                 dma: dma-controller@01c02000 {
 538                         compatible = "allwinner,sun4i-a10-dma";
 539                         reg = <0x01c02000 0x1000>;
 540                         interrupts = <27>;
 541                         clocks = <&ahb_gates 6>;
 542                         #dma-cells = <2>;
 543                 };
 544
 545                 spi0: spi@01c05000 {
 546                         compatible = "allwinner,sun4i-a10-spi";
 547                         reg = <0x01c05000 0x1000>;
 548                         interrupts = <10>;
 549                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 550                         clock-names = "ahb", "mod";
 551                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 552                                <&dma SUN4I_DMA_DEDICATED 26>;
 553                         dma-names = "rx", "tx";
 554                         status = "disabled";
 555                         #address-cells = <1>;
 556                         #size-cells = <0>;
 557                 };
 558
 559                 spi1: spi@01c06000 {
 560                         compatible = "allwinner,sun4i-a10-spi";
 561                         reg = <0x01c06000 0x1000>;
 562                         interrupts = <11>;
 563                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 564                         clock-names = "ahb", "mod";
 565                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 566                                <&dma SUN4I_DMA_DEDICATED 8>;
 567                         dma-names = "rx", "tx";
 568                         status = "disabled";
 569                         #address-cells = <1>;
 570                         #size-cells = <0>;
 571                 };
 572
 573                 emac: ethernet@01c0b000 {
 574                         compatible = "allwinner,sun4i-a10-emac";
 575                         reg = <0x01c0b000 0x1000>;
 576                         interrupts = <55>;
 577                         clocks = <&ahb_gates 17>;
 578                         allwinner,sram = <&emac_sram 1>;
 579                         status = "disabled";
 580                 };
 581
 582                 mdio: mdio@01c0b080 {
 583                         compatible = "allwinner,sun4i-a10-mdio";
 584                         reg = <0x01c0b080 0x14>;
 585                         status = "disabled";
 586                         #address-cells = <1>;
 587                         #size-cells = <0>;
 588                 };
 589
 590                 mmc0: mmc@01c0f000 {
 591                         compatible = "allwinner,sun4i-a10-mmc";
 592                         reg = <0x01c0f000 0x1000>;
 593                         clocks = <&ahb_gates 8>,
 594                                  <&mmc0_clk 0>,
 595                                  <&mmc0_clk 1>,
 596                                  <&mmc0_clk 2>;
 597                         clock-names = "ahb",
 598                                       "mmc",
 599                                       "output",
 600                                       "sample";
 601                         interrupts = <32>;
 602                         status = "disabled";
 603                         #address-cells = <1>;
 604                         #size-cells = <0>;
 605                 };
 606
 607                 mmc1: mmc@01c10000 {
 608                         compatible = "allwinner,sun4i-a10-mmc";
 609                         reg = <0x01c10000 0x1000>;
 610                         clocks = <&ahb_gates 9>,
 611                                  <&mmc1_clk 0>,
 612                                  <&mmc1_clk 1>,
 613                                  <&mmc1_clk 2>;
 614                         clock-names = "ahb",
 615                                       "mmc",
 616                                       "output",
 617                                       "sample";
 618                         interrupts = <33>;
 619                         status = "disabled";
 620                         #address-cells = <1>;
 621                         #size-cells = <0>;
 622                 };
 623
 624                 mmc2: mmc@01c11000 {
 625                         compatible = "allwinner,sun4i-a10-mmc";
 626                         reg = <0x01c11000 0x1000>;
 627                         clocks = <&ahb_gates 10>,
 628                                  <&mmc2_clk 0>,
 629                                  <&mmc2_clk 1>,
 630                                  <&mmc2_clk 2>;
 631                         clock-names = "ahb",
 632                                       "mmc",
 633                                       "output",
 634                                       "sample";
 635                         interrupts = <34>;
 636                         status = "disabled";
 637                         #address-cells = <1>;
 638                         #size-cells = <0>;
 639                 };
 640
 641                 mmc3: mmc@01c12000 {
 642                         compatible = "allwinner,sun4i-a10-mmc";
 643                         reg = <0x01c12000 0x1000>;
 644                         clocks = <&ahb_gates 11>,
 645                                  <&mmc3_clk 0>,
 646                                  <&mmc3_clk 1>,
 647                                  <&mmc3_clk 2>;
 648                         clock-names = "ahb",
 649                                       "mmc",
 650                                       "output",
 651                                       "sample";
 652                         interrupts = <35>;
 653                         status = "disabled";
 654                         #address-cells = <1>;
 655                         #size-cells = <0>;
 656                 };
 657
 658                 usb_otg: usb@01c13000 {
 659                         compatible = "allwinner,sun4i-a10-musb";
 660                         reg = <0x01c13000 0x0400>;
 661                         clocks = <&ahb_gates 0>;
 662                         interrupts = <38>;
 663                         interrupt-names = "mc";
 664                         phys = <&usbphy 0>;
 665                         phy-names = "usb";
 666                         extcon = <&usbphy 0>;
 667                         allwinner,sram = <&otg_sram 1>;
 668                         status = "disabled";
 669                 };
 670
 671                 usbphy: phy@01c13400 {
 672                         #phy-cells = <1>;
 673                         compatible = "allwinner,sun4i-a10-usb-phy";
 674                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 675                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 676                         clocks = <&usb_clk 8>;
 677                         clock-names = "usb_phy";
 678                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 679                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 680                         status = "disabled";
 681                 };
 682
 683                 ehci0: usb@01c14000 {
 684                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 685                         reg = <0x01c14000 0x100>;
 686                         interrupts = <39>;
 687                         clocks = <&ahb_gates 1>;
 688                         phys = <&usbphy 1>;
 689                         phy-names = "usb";
 690                         status = "disabled";
 691                 };
 692
 693                 ohci0: usb@01c14400 {
 694                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 695                         reg = <0x01c14400 0x100>;
 696                         interrupts = <64>;
 697                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 698                         phys = <&usbphy 1>;
 699                         phy-names = "usb";
 700                         status = "disabled";
 701                 };
 702
 703                 crypto: crypto-engine@01c15000 {
 704                         compatible = "allwinner,sun4i-a10-crypto";
 705                         reg = <0x01c15000 0x1000>;
 706                         interrupts = <86>;
 707                         clocks = <&ahb_gates 5>, <&ss_clk>;
 708                         clock-names = "ahb", "mod";
 709                 };
 710
 711                 spi2: spi@01c17000 {
 712                         compatible = "allwinner,sun4i-a10-spi";
 713                         reg = <0x01c17000 0x1000>;
 714                         interrupts = <12>;
 715                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 716                         clock-names = "ahb", "mod";
 717                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 718                                <&dma SUN4I_DMA_DEDICATED 28>;
 719                         dma-names = "rx", "tx";
 720                         status = "disabled";
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                 };
 724
 725                 ahci: sata@01c18000 {
 726                         compatible = "allwinner,sun4i-a10-ahci";
 727                         reg = <0x01c18000 0x1000>;
 728                         interrupts = <56>;
 729                         clocks = <&pll6 0>, <&ahb_gates 25>;
 730                         status = "disabled";
 731                 };
 732
 733                 ehci1: usb@01c1c000 {
 734                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 735                         reg = <0x01c1c000 0x100>;
 736                         interrupts = <40>;
 737                         clocks = <&ahb_gates 3>;
 738                         phys = <&usbphy 2>;
 739                         phy-names = "usb";
 740                         status = "disabled";
 741                 };
 742
 743                 ohci1: usb@01c1c400 {
 744                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 745                         reg = <0x01c1c400 0x100>;
 746                         interrupts = <65>;
 747                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 748                         phys = <&usbphy 2>;
 749                         phy-names = "usb";
 750                         status = "disabled";
 751                 };
 752
 753                 spi3: spi@01c1f000 {
 754                         compatible = "allwinner,sun4i-a10-spi";
 755                         reg = <0x01c1f000 0x1000>;
 756                         interrupts = <50>;
 757                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 758                         clock-names = "ahb", "mod";
 759                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 760                                <&dma SUN4I_DMA_DEDICATED 30>;
 761                         dma-names = "rx", "tx";
 762                         status = "disabled";
 763                         #address-cells = <1>;
 764                         #size-cells = <0>;
 765                 };
 766
 767                 intc: interrupt-controller@01c20400 {
 768                         compatible = "allwinner,sun4i-a10-ic";
 769                         reg = <0x01c20400 0x400>;
 770                         interrupt-controller;
 771                         #interrupt-cells = <1>;
 772                 };
 773
 774                 pio: pinctrl@01c20800 {
 775                         compatible = "allwinner,sun4i-a10-pinctrl";
 776                         reg = <0x01c20800 0x400>;
 777                         interrupts = <28>;
 778                         clocks = <&apb0_gates 5>;
 779                         gpio-controller;
 780                         interrupt-controller;
 781                         #interrupt-cells = <3>;
 782                         #gpio-cells = <3>;
 783
 784                         pwm0_pins_a: pwm0@0 {
 785                                 allwinner,pins = "PB2";
 786                                 allwinner,function = "pwm";
 787                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 788                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 789                         };
 790
 791                         pwm1_pins_a: pwm1@0 {
 792                                 allwinner,pins = "PI3";
 793                                 allwinner,function = "pwm";
 794                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 795                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 796                         };
 797
 798                         uart0_pins_a: uart0@0 {
 799                                 allwinner,pins = "PB22", "PB23";
 800                                 allwinner,function = "uart0";
 801                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 802                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 803                         };
 804
 805                         uart0_pins_b: uart0@1 {
 806                                 allwinner,pins = "PF2", "PF4";
 807                                 allwinner,function = "uart0";
 808                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 809                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 810                         };
 811
 812                         uart1_pins_a: uart1@0 {
 813                                 allwinner,pins = "PA10", "PA11";
 814                                 allwinner,function = "uart1";
 815                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 816                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 817                         };
 818
 819                         i2c0_pins_a: i2c0@0 {
 820                                 allwinner,pins = "PB0", "PB1";
 821                                 allwinner,function = "i2c0";
 822                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 823                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 824                         };
 825
 826                         i2c1_pins_a: i2c1@0 {
 827                                 allwinner,pins = "PB18", "PB19";
 828                                 allwinner,function = "i2c1";
 829                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 830                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 831                         };
 832
 833                         i2c2_pins_a: i2c2@0 {
 834                                 allwinner,pins = "PB20", "PB21";
 835                                 allwinner,function = "i2c2";
 836                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 837                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 838                         };
 839
 840                         emac_pins_a: emac0@0 {
 841                                 allwinner,pins = "PA0", "PA1", "PA2",
 842                                                 "PA3", "PA4", "PA5", "PA6",
 843                                                 "PA7", "PA8", "PA9", "PA10",
 844                                                 "PA11", "PA12", "PA13", "PA14",
 845                                                 "PA15", "PA16";
 846                                 allwinner,function = "emac";
 847                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 848                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 849                         };
 850
 851                         mmc0_pins_a: mmc0@0 {
 852                                 allwinner,pins = "PF0", "PF1", "PF2",
 853                                                  "PF3", "PF4", "PF5";
 854                                 allwinner,function = "mmc0";
 855                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 856                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 857                         };
 858
 859                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 860                                 allwinner,pins = "PH1";
 861                                 allwinner,function = "gpio_in";
 862                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 863                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 864                         };
 865
 866                         ir0_rx_pins_a: ir0@0 {
 867                                 allwinner,pins = "PB4";
 868                                 allwinner,function = "ir0";
 869                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 870                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 871                         };
 872
 873                         ir0_tx_pins_a: ir0@1 {
 874                                 allwinner,pins = "PB3";
 875                                 allwinner,function = "ir0";
 876                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 877                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 878                         };
 879
 880                         ir1_rx_pins_a: ir1@0 {
 881                                 allwinner,pins = "PB23";
 882                                 allwinner,function = "ir1";
 883                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 884                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 885                         };
 886
 887                         ir1_tx_pins_a: ir1@1 {
 888                                 allwinner,pins = "PB22";
 889                                 allwinner,function = "ir1";
 890                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 891                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 892                         };
 893
 894                         spi0_pins_a: spi0@0 {
 895                                 allwinner,pins = "PI11", "PI12", "PI13";
 896                                 allwinner,function = "spi0";
 897                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 898                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 899                         };
 900
 901                         spi0_cs0_pins_a: spi0_cs0@0 {
 902                                 allwinner,pins = "PI10";
 903                                 allwinner,function = "spi0";
 904                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 905                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 906                         };
 907
 908                         spi1_pins_a: spi1@0 {
 909                                 allwinner,pins = "PI17", "PI18", "PI19";
 910                                 allwinner,function = "spi1";
 911                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 912                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 913                         };
 914
 915                         spi1_cs0_pins_a: spi1_cs0@0 {
 916                                 allwinner,pins = "PI16";
 917                                 allwinner,function = "spi1";
 918                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 919                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 920                         };
 921
 922                         spi2_pins_a: spi2@0 {
 923                                 allwinner,pins = "PC20", "PC21", "PC22";
 924                                 allwinner,function = "spi2";
 925                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 926                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 927                         };
 928
 929                         spi2_pins_b: spi2@1 {
 930                                 allwinner,pins = "PB15", "PB16", "PB17";
 931                                 allwinner,function = "spi2";
 932                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 933                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 934                         };
 935
 936                         spi2_cs0_pins_a: spi2_cs0@0 {
 937                                 allwinner,pins = "PC19";
 938                                 allwinner,function = "spi2";
 939                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 940                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 941                         };
 942
 943                         spi2_cs0_pins_b: spi2_cs0@1 {
 944                                 allwinner,pins = "PB14";
 945                                 allwinner,function = "spi2";
 946                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 947                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 948                         };
 949
 950                         ps20_pins_a: ps20@0 {
 951                                 allwinner,pins = "PI20", "PI21";
 952                                 allwinner,function = "ps2";
 953                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 954                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 955                         };
 956
 957                         ps21_pins_a: ps21@0 {
 958                                 allwinner,pins = "PH12", "PH13";
 959                                 allwinner,function = "ps2";
 960                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 961                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 962                         };
 963                 };
 964
 965                 timer@01c20c00 {
 966                         compatible = "allwinner,sun4i-a10-timer";
 967                         reg = <0x01c20c00 0x90>;
 968                         interrupts = <22>;
 969                         clocks = <&osc24M>;
 970                 };
 971
 972                 wdt: watchdog@01c20c90 {
 973                         compatible = "allwinner,sun4i-a10-wdt";
 974                         reg = <0x01c20c90 0x10>;
 975                 };
 976
 977                 rtc: rtc@01c20d00 {
 978                         compatible = "allwinner,sun4i-a10-rtc";
 979                         reg = <0x01c20d00 0x20>;
 980                         interrupts = <24>;
 981                 };
 982
 983                 pwm: pwm@01c20e00 {
 984                         compatible = "allwinner,sun4i-a10-pwm";
 985                         reg = <0x01c20e00 0xc>;
 986                         clocks = <&osc24M>;
 987                         #pwm-cells = <3>;
 988                         status = "disabled";
 989                 };
 990
 991                 ir0: ir@01c21800 {
 992                         compatible = "allwinner,sun4i-a10-ir";
 993                         clocks = <&apb0_gates 6>, <&ir0_clk>;
 994                         clock-names = "apb", "ir";
 995                         interrupts = <5>;
 996                         reg = <0x01c21800 0x40>;
 997                         status = "disabled";
 998                 };
 999
1000                 ir1: ir@01c21c00 {
1001                         compatible = "allwinner,sun4i-a10-ir";
1002                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1003                         clock-names = "apb", "ir";
1004                         interrupts = <6>;
1005                         reg = <0x01c21c00 0x40>;
1006                         status = "disabled";
1007                 };
1008
1009                 lradc: lradc@01c22800 {
1010                         compatible = "allwinner,sun4i-a10-lradc-keys";
1011                         reg = <0x01c22800 0x100>;
1012                         interrupts = <31>;
1013                         status = "disabled";
1014                 };
1015
1016                 sid: eeprom@01c23800 {
1017                         compatible = "allwinner,sun4i-a10-sid";
1018                         reg = <0x01c23800 0x10>;
1019                 };
1020
1021                 rtp: rtp@01c25000 {
1022                         compatible = "allwinner,sun4i-a10-ts";
1023                         reg = <0x01c25000 0x100>;
1024                         interrupts = <29>;
1025                         #thermal-sensor-cells = <0>;
1026                 };
1027
1028                 uart0: serial@01c28000 {
1029                         compatible = "snps,dw-apb-uart";
1030                         reg = <0x01c28000 0x400>;
1031                         interrupts = <1>;
1032                         reg-shift = <2>;
1033                         reg-io-width = <4>;
1034                         clocks = <&apb1_gates 16>;
1035                         status = "disabled";
1036                 };
1037
1038                 uart1: serial@01c28400 {
1039                         compatible = "snps,dw-apb-uart";
1040                         reg = <0x01c28400 0x400>;
1041                         interrupts = <2>;
1042                         reg-shift = <2>;
1043                         reg-io-width = <4>;
1044                         clocks = <&apb1_gates 17>;
1045                         status = "disabled";
1046                 };
1047
1048                 uart2: serial@01c28800 {
1049                         compatible = "snps,dw-apb-uart";
1050                         reg = <0x01c28800 0x400>;
1051                         interrupts = <3>;
1052                         reg-shift = <2>;
1053                         reg-io-width = <4>;
1054                         clocks = <&apb1_gates 18>;
1055                         status = "disabled";
1056                 };
1057
1058                 uart3: serial@01c28c00 {
1059                         compatible = "snps,dw-apb-uart";
1060                         reg = <0x01c28c00 0x400>;
1061                         interrupts = <4>;
1062                         reg-shift = <2>;
1063                         reg-io-width = <4>;
1064                         clocks = <&apb1_gates 19>;
1065                         status = "disabled";
1066                 };
1067
1068                 uart4: serial@01c29000 {
1069                         compatible = "snps,dw-apb-uart";
1070                         reg = <0x01c29000 0x400>;
1071                         interrupts = <17>;
1072                         reg-shift = <2>;
1073                         reg-io-width = <4>;
1074                         clocks = <&apb1_gates 20>;
1075                         status = "disabled";
1076                 };
1077
1078                 uart5: serial@01c29400 {
1079                         compatible = "snps,dw-apb-uart";
1080                         reg = <0x01c29400 0x400>;
1081                         interrupts = <18>;
1082                         reg-shift = <2>;
1083                         reg-io-width = <4>;
1084                         clocks = <&apb1_gates 21>;
1085                         status = "disabled";
1086                 };
1087
1088                 uart6: serial@01c29800 {
1089                         compatible = "snps,dw-apb-uart";
1090                         reg = <0x01c29800 0x400>;
1091                         interrupts = <19>;
1092                         reg-shift = <2>;
1093                         reg-io-width = <4>;
1094                         clocks = <&apb1_gates 22>;
1095                         status = "disabled";
1096                 };
1097
1098                 uart7: serial@01c29c00 {
1099                         compatible = "snps,dw-apb-uart";
1100                         reg = <0x01c29c00 0x400>;
1101                         interrupts = <20>;
1102                         reg-shift = <2>;
1103                         reg-io-width = <4>;
1104                         clocks = <&apb1_gates 23>;
1105                         status = "disabled";
1106                 };
1107
1108                 i2c0: i2c@01c2ac00 {
1109                         compatible = "allwinner,sun4i-a10-i2c";
1110                         reg = <0x01c2ac00 0x400>;
1111                         interrupts = <7>;
1112                         clocks = <&apb1_gates 0>;
1113                         status = "disabled";
1114                         #address-cells = <1>;
1115                         #size-cells = <0>;
1116                 };
1117
1118                 i2c1: i2c@01c2b000 {
1119                         compatible = "allwinner,sun4i-a10-i2c";
1120                         reg = <0x01c2b000 0x400>;
1121                         interrupts = <8>;
1122                         clocks = <&apb1_gates 1>;
1123                         status = "disabled";
1124                         #address-cells = <1>;
1125                         #size-cells = <0>;
1126                 };
1127
1128                 i2c2: i2c@01c2b400 {
1129                         compatible = "allwinner,sun4i-a10-i2c";
1130                         reg = <0x01c2b400 0x400>;
1131                         interrupts = <9>;
1132                         clocks = <&apb1_gates 2>;
1133                         status = "disabled";
1134                         #address-cells = <1>;
1135                         #size-cells = <0>;
1136                 };
1137
1138                 ps20: ps2@01c2a000 {
1139                         compatible = "allwinner,sun4i-a10-ps2";
1140                         reg = <0x01c2a000 0x400>;
1141                         interrupts = <62>;
1142                         clocks = <&apb1_gates 6>;
1143                         status = "disabled";
1144                 };
1145
1146                 ps21: ps2@01c2a400 {
1147                         compatible = "allwinner,sun4i-a10-ps2";
1148                         reg = <0x01c2a400 0x400>;
1149                         interrupts = <63>;
1150                         clocks = <&apb1_gates 7>;
1151                         status = "disabled";
1152                 };
1153         };
1154 };