arch/arm/boot/dts/tegra30-apalis.dtsi

   1 #include "tegra30.dtsi"
   2
   3 /*
   4  * Toradex Apalis T30 Module Device Tree
   5  * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
   6  * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
   7  */
   8 / {
   9         model = "Toradex Apalis T30";
  10         compatible = "toradex,apalis_t30", "nvidia,tegra30";
  11
  12         pcie-controller@00003000 {
  13                 avdd-pexa-supply = <&vdd2_reg>;
  14                 vdd-pexa-supply = <&vdd2_reg>;
  15                 avdd-pexb-supply = <&vdd2_reg>;
  16                 vdd-pexb-supply = <&vdd2_reg>;
  17                 avdd-pex-pll-supply = <&vdd2_reg>;
  18                 avdd-plle-supply = <&ldo6_reg>;
  19                 vddio-pex-ctl-supply = <&sys_3v3_reg>;
  20                 hvdd-pex-supply = <&sys_3v3_reg>;
  21
  22                 pci@1,0 {
  23                         nvidia,num-lanes = <4>;
  24                 };
  25
  26                 pci@2,0 {
  27                         nvidia,num-lanes = <1>;
  28                 };
  29
  30                 pci@3,0 {
  31                         nvidia,num-lanes = <1>;
  32                 };
  33         };
  34
  35         host1x@50000000 {
  36                 hdmi@54280000 {
  37                         vdd-supply = <&avdd_hdmi_3v3_reg>;
  38                         pll-supply = <&avdd_hdmi_pll_1v8_reg>;
  39
  40                         nvidia,hpd-gpio =
  41                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
  42                         nvidia,ddc-i2c-bus = <&hdmiddc>;
  43                 };
  44         };
  45
  46         pinmux@70000868 {
  47                 pinctrl-names = "default";
  48                 pinctrl-0 = <&state_default>;
  49
  50                 state_default: pinmux {
  51                         /* Apalis BKL1_ON */
  52                         pv2 {
  53                                 nvidia,pins = "pv2";
  54                                 nvidia,function = "rsvd4";
  55                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  56                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  57                         };
  58
  59                         /* Apalis BKL1_PWM */
  60                         uart3_rts_n_pc0 {
  61                                 nvidia,pins = "uart3_rts_n_pc0";
  62                                 nvidia,function = "pwm0";
  63                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  64                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  65                         };
  66                         /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
  67                         uart3_cts_n_pa1 {
  68                                 nvidia,pins = "uart3_cts_n_pa1";
  69                                 nvidia,function = "rsvd2";
  70                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
  71                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  72                         };
  73
  74                         /* Apalis CAN1 on SPI6 */
  75                         spi2_cs0_n_px3 {
  76                                 nvidia,pins = "spi2_cs0_n_px3",
  77                                               "spi2_miso_px1",
  78                                               "spi2_mosi_px0",
  79                                               "spi2_sck_px2";
  80                                 nvidia,function = "spi6";
  81                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  82                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  83                         };
  84                         /* CAN_INT1 */
  85                         spi2_cs1_n_pw2 {
  86                                 nvidia,pins = "spi2_cs1_n_pw2";
  87                                 nvidia,function = "spi3";
  88                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  89                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  90                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  91                         };
  92
  93                         /* Apalis CAN2 on SPI4 */
  94                         gmi_a16_pj7 {
  95                                 nvidia,pins = "gmi_a16_pj7",
  96                                               "gmi_a17_pb0",
  97                                               "gmi_a18_pb1",
  98                                               "gmi_a19_pk7";
  99                                 nvidia,function = "spi4";
 100                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 101                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 102                         };
 103                         /* CAN_INT2 */
 104                         spi2_cs2_n_pw3 {
 105                                 nvidia,pins = "spi2_cs2_n_pw3";
 106                                 nvidia,function = "spi3";
 107                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 108                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 109                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 110                         };
 111
 112                         /* Apalis Digital Audio */
 113                         clk1_req_pee2 {
 114                                 nvidia,pins = "clk1_req_pee2";
 115                                 nvidia,function = "hda";
 116                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 117                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 118                         };
 119                         clk2_out_pw5 {
 120                                 nvidia,pins = "clk2_out_pw5";
 121                                 nvidia,function = "extperiph2";
 122                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 123                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 124                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 125                         };
 126                         dap1_fs_pn0 {
 127                                 nvidia,pins = "dap1_fs_pn0",
 128                                               "dap1_din_pn1",
 129                                               "dap1_dout_pn2",
 130                                               "dap1_sclk_pn3";
 131                                 nvidia,function = "hda";
 132                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 133                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 134                         };
 135
 136                         /* Apalis I2C3 */
 137                         cam_i2c_scl_pbb1 {
 138                                 nvidia,pins = "cam_i2c_scl_pbb1",
 139                                               "cam_i2c_sda_pbb2";
 140                                 nvidia,function = "i2c3";
 141                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 142                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 143                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 144                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 145                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 146                         };
 147
 148                         /* Apalis MMC1 */
 149                         sdmmc3_clk_pa6 {
 150                                 nvidia,pins = "sdmmc3_clk_pa6",
 151                                               "sdmmc3_cmd_pa7";
 152                                 nvidia,function = "sdmmc3";
 153                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 154                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 155                         };
 156                         sdmmc3_dat0_pb7 {
 157                                 nvidia,pins = "sdmmc3_dat0_pb7",
 158                                               "sdmmc3_dat1_pb6",
 159                                               "sdmmc3_dat2_pb5",
 160                                               "sdmmc3_dat3_pb4",
 161                                               "sdmmc3_dat4_pd1",
 162                                               "sdmmc3_dat5_pd0",
 163                                               "sdmmc3_dat6_pd3",
 164                                               "sdmmc3_dat7_pd4";
 165                                 nvidia,function = "sdmmc3";
 166                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 167                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 168                         };
 169                         /* Apalis MMC1_CD# */
 170                         pv3 {
 171                                 nvidia,pins = "pv3";
 172                                 nvidia,function = "rsvd2";
 173                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 174                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 175                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 176                         };
 177
 178                         /* Apalis PWM1 */
 179                         pu6 {
 180                                 nvidia,pins = "pu6";
 181                                 nvidia,function = "pwm3";
 182                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 183                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 184                         };
 185
 186                         /* Apalis PWM2 */
 187                         pu5 {
 188                                 nvidia,pins = "pu5";
 189                                 nvidia,function = "pwm2";
 190                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 191                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 192                         };
 193
 194                         /* Apalis PWM3 */
 195                         pu4 {
 196                                 nvidia,pins = "pu4";
 197                                 nvidia,function = "pwm1";
 198                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 199                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 200                         };
 201
 202                         /* Apalis PWM4 */
 203                         pu3 {
 204                                 nvidia,pins = "pu3";
 205                                 nvidia,function = "pwm0";
 206                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 207                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 208                         };
 209
 210                         /* Apalis RESET_MOCI# */
 211                         gmi_rst_n_pi4 {
 212                                 nvidia,pins = "gmi_rst_n_pi4";
 213                                 nvidia,function = "gmi";
 214                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 215                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 216                         };
 217
 218                         /* Apalis SD1 */
 219                         sdmmc1_clk_pz0 {
 220                                 nvidia,pins = "sdmmc1_clk_pz0";
 221                                 nvidia,function = "sdmmc1";
 222                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 223                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 224                         };
 225                         sdmmc1_cmd_pz1 {
 226                                 nvidia,pins = "sdmmc1_cmd_pz1",
 227                                               "sdmmc1_dat0_py7",
 228                                               "sdmmc1_dat1_py6",
 229                                               "sdmmc1_dat2_py5",
 230                                               "sdmmc1_dat3_py4";
 231                                 nvidia,function = "sdmmc1";
 232                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 233                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 234                         };
 235                         /* Apalis SD1_CD# */
 236                         clk2_req_pcc5 {
 237                                 nvidia,pins = "clk2_req_pcc5";
 238                                 nvidia,function = "rsvd2";
 239                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 240                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 241                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 242                         };
 243
 244                         /* Apalis SPI1 */
 245                         spi1_sck_px5 {
 246                                 nvidia,pins = "spi1_sck_px5",
 247                                               "spi1_mosi_px4",
 248                                               "spi1_miso_px7",
 249                                               "spi1_cs0_n_px6";
 250                                 nvidia,function = "spi1";
 251                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 252                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 253                         };
 254
 255                         /* Apalis SPI2 */
 256                         lcd_sck_pz4 {
 257                                 nvidia,pins = "lcd_sck_pz4",
 258                                               "lcd_sdout_pn5",
 259                                               "lcd_sdin_pz2",
 260                                               "lcd_cs0_n_pn4";
 261                                 nvidia,function = "spi5";
 262                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 263                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 264                         };
 265
 266                         /* Apalis UART1 */
 267                         ulpi_data0 {
 268                                 nvidia,pins = "ulpi_data0_po1",
 269                                               "ulpi_data1_po2",
 270                                               "ulpi_data2_po3",
 271                                               "ulpi_data3_po4",
 272                                               "ulpi_data4_po5",
 273                                               "ulpi_data5_po6",
 274                                               "ulpi_data6_po7",
 275                                               "ulpi_data7_po0";
 276                                 nvidia,function = "uarta";
 277                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 278                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 279                         };
 280
 281                         /* Apalis UART2 */
 282                         ulpi_clk_py0 {
 283                                 nvidia,pins = "ulpi_clk_py0",
 284                                               "ulpi_dir_py1",
 285                                               "ulpi_nxt_py2",
 286                                               "ulpi_stp_py3";
 287                                 nvidia,function = "uartd";
 288                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 289                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 290                         };
 291
 292                         /* Apalis UART3 */
 293                         uart2_rxd_pc3 {
 294                                 nvidia,pins = "uart2_rxd_pc3",
 295                                               "uart2_txd_pc2";
 296                                 nvidia,function = "uartb";
 297                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 298                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 299                         };
 300
 301                         /* Apalis UART4 */
 302                         uart3_rxd_pw7 {
 303                                 nvidia,pins = "uart3_rxd_pw7",
 304                                               "uart3_txd_pw6";
 305                                 nvidia,function = "uartc";
 306                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 307                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 308                         };
 309
 310                         /* Apalis USBO1_EN */
 311                         gen2_i2c_scl_pt5 {
 312                                 nvidia,pins = "gen2_i2c_scl_pt5";
 313                                 nvidia,function = "rsvd4";
 314                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 315                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 316                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 317                         };
 318
 319                         /* Apalis USBO1_OC# */
 320                         gen2_i2c_sda_pt6 {
 321                                 nvidia,pins = "gen2_i2c_sda_pt6";
 322                                 nvidia,function = "rsvd4";
 323                                 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
 324                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 325                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 326                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 327                         };
 328
 329                         /* Apalis WAKE1_MICO */
 330                         pv1 {
 331                                 nvidia,pins = "pv1";
 332                                 nvidia,function = "rsvd1";
 333                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 334                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 335                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 336                         };
 337
 338                         /* eMMC (On-module) */
 339                         sdmmc4_clk_pcc4 {
 340                                 nvidia,pins = "sdmmc4_clk_pcc4",
 341                                               "sdmmc4_rst_n_pcc3";
 342                                 nvidia,function = "sdmmc4";
 343                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 344                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 345                         };
 346                         sdmmc4_dat0_paa0 {
 347                                 nvidia,pins = "sdmmc4_dat0_paa0",
 348                                               "sdmmc4_dat1_paa1",
 349                                               "sdmmc4_dat2_paa2",
 350                                               "sdmmc4_dat3_paa3",
 351                                               "sdmmc4_dat4_paa4",
 352                                               "sdmmc4_dat5_paa5",
 353                                               "sdmmc4_dat6_paa6",
 354                                               "sdmmc4_dat7_paa7";
 355                                 nvidia,function = "sdmmc4";
 356                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 357                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 358                         };
 359
 360                         /* LVDS Transceiver Configuration */
 361                         pbb0 {
 362                                 nvidia,pins = "pbb0",
 363                                               "pbb7",
 364                                               "pcc1",
 365                                               "pcc2";
 366                                 nvidia,function = "rsvd2";
 367                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 368                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 369                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 370                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 371                         };
 372                         pbb3 {
 373                                 nvidia,pins = "pbb3",
 374                                               "pbb4",
 375                                               "pbb5",
 376                                               "pbb6";
 377                                 nvidia,function = "displayb";
 378                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 379                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 380                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 381                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 382                         };
 383
 384                         /* Power I2C (On-module) */
 385                         pwr_i2c_scl_pz6 {
 386                                 nvidia,pins = "pwr_i2c_scl_pz6",
 387                                               "pwr_i2c_sda_pz7";
 388                                 nvidia,function = "i2cpwr";
 389                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 390                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 391                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 392                                 nvidia,lock = <TEGRA_PIN_DISABLE>;
 393                                 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
 394                         };
 395
 396                         /*
 397                          * THERMD_ALERT#, unlatched I2C address pin of LM95245
 398                          * temperature sensor therefore requires disabling for
 399                          * now
 400                          */
 401                         lcd_dc1_pd2 {
 402                                 nvidia,pins = "lcd_dc1_pd2";
 403                                 nvidia,function = "rsvd3";
 404                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 405                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 406                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 407                         };
 408
 409                         /* TOUCH_PEN_INT# */
 410                         pv0 {
 411                                 nvidia,pins = "pv0";
 412                                 nvidia,function = "rsvd1";
 413                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 414                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 415                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 416                         };
 417                 };
 418         };
 419
 420         hdmiddc: i2c@7000c700 {
 421                 clock-frequency = <100000>;
 422         };
 423
 424         /*
 425          * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
 426          * touch screen controller
 427          */
 428         i2c@7000d000 {
 429                 status = "okay";
 430                 clock-frequency = <100000>;
 431
 432                 pmic: tps65911@2d {
 433                         compatible = "ti,tps65911";
 434                         reg = <0x2d>;
 435
 436                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 437                         #interrupt-cells = <2>;
 438                         interrupt-controller;
 439
 440                         ti,system-power-controller;
 441
 442                         #gpio-cells = <2>;
 443                         gpio-controller;
 444
 445                         vcc1-supply = <&sys_3v3_reg>;
 446                         vcc2-supply = <&sys_3v3_reg>;
 447                         vcc3-supply = <&vio_reg>;
 448                         vcc4-supply = <&sys_3v3_reg>;
 449                         vcc5-supply = <&sys_3v3_reg>;
 450                         vcc6-supply = <&vio_reg>;
 451                         vcc7-supply = <&charge_pump_5v0_reg>;
 452                         vccio-supply = <&sys_3v3_reg>;
 453
 454                         regulators {
 455                                 /* SW1: +V1.35_VDDIO_DDR */
 456                                 vdd1_reg: vdd1 {
 457                                         regulator-name = "vddio_ddr_1v35";
 458                                         regulator-min-microvolt = <1350000>;
 459                                         regulator-max-microvolt = <1350000>;
 460                                         regulator-always-on;
 461                                 };
 462
 463                                 /* SW2: +V1.05 */
 464                                 vdd2_reg: vdd2 {
 465                                         regulator-name =
 466                                                 "vdd_pexa,vdd_pexb,vdd_sata";
 467                                         regulator-min-microvolt = <1050000>;
 468                                         regulator-max-microvolt = <1050000>;
 469                                 };
 470
 471                                 /* SW CTRL: +V1.0_VDD_CPU */
 472                                 vddctrl_reg: vddctrl {
 473                                         regulator-name = "vdd_cpu,vdd_sys";
 474                                         regulator-min-microvolt = <1150000>;
 475                                         regulator-max-microvolt = <1150000>;
 476                                         regulator-always-on;
 477                                 };
 478
 479                                 /* SWIO: +V1.8 */
 480                                 vio_reg: vio {
 481                                         regulator-name = "vdd_1v8_gen";
 482                                         regulator-min-microvolt = <1800000>;
 483                                         regulator-max-microvolt = <1800000>;
 484                                         regulator-always-on;
 485                                 };
 486
 487                                 /* LDO1: unused */
 488
 489                                 /*
 490                                  * EN_+V3.3 switching via FET:
 491                                  * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
 492                                  * see also v3_3 fixed supply
 493                                  */
 494                                 ldo2_reg: ldo2 {
 495                                         regulator-name = "en_3v3";
 496                                         regulator-min-microvolt = <3300000>;
 497                                         regulator-max-microvolt = <3300000>;
 498                                         regulator-always-on;
 499                                 };
 500
 501                                 /* +V1.2_CSI */
 502                                 ldo3_reg: ldo3 {
 503                                         regulator-name =
 504                                                 "avdd_dsi_csi,pwrdet_mipi";
 505                                         regulator-min-microvolt = <1200000>;
 506                                         regulator-max-microvolt = <1200000>;
 507                                 };
 508
 509                                 /* +V1.2_VDD_RTC */
 510                                 ldo4_reg: ldo4 {
 511                                         regulator-name = "vdd_rtc";
 512                                         regulator-min-microvolt = <1200000>;
 513                                         regulator-max-microvolt = <1200000>;
 514                                         regulator-always-on;
 515                                 };
 516
 517                                 /*
 518                                  * +V2.8_AVDD_VDAC:
 519                                  * only required for analog RGB
 520                                  */
 521                                 ldo5_reg: ldo5 {
 522                                         regulator-name = "avdd_vdac";
 523                                         regulator-min-microvolt = <2800000>;
 524                                         regulator-max-microvolt = <2800000>;
 525                                         regulator-always-on;
 526                                 };
 527
 528                                 /*
 529                                  * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
 530                                  * but LDO6 can't set voltage in 50mV
 531                                  * granularity
 532                                  */
 533                                 ldo6_reg: ldo6 {
 534                                         regulator-name = "avdd_plle";
 535                                         regulator-min-microvolt = <1100000>;
 536                                         regulator-max-microvolt = <1100000>;
 537                                 };
 538
 539                                 /* +V1.2_AVDD_PLL */
 540                                 ldo7_reg: ldo7 {
 541                                         regulator-name = "avdd_pll";
 542                                         regulator-min-microvolt = <1200000>;
 543                                         regulator-max-microvolt = <1200000>;
 544                                         regulator-always-on;
 545                                 };
 546
 547                                 /* +V1.0_VDD_DDR_HS */
 548                                 ldo8_reg: ldo8 {
 549                                         regulator-name = "vdd_ddr_hs";
 550                                         regulator-min-microvolt = <1000000>;
 551                                         regulator-max-microvolt = <1000000>;
 552                                         regulator-always-on;
 553                                 };
 554                         };
 555                 };
 556
 557                 /* STMPE811 touch screen controller */
 558                 stmpe811@41 {
 559                         compatible = "st,stmpe811";
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                         reg = <0x41>;
 563                         interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
 564                         interrupt-parent = <&gpio>;
 565                         interrupt-controller;
 566                         id = <0>;
 567                         blocks = <0x5>;
 568                         irq-trigger = <0x1>;
 569
 570                         stmpe_touchscreen {
 571                                 compatible = "st,stmpe-ts";
 572                                 reg = <0>;
 573                                 /* 3.25 MHz ADC clock speed */
 574                                 st,adc-freq = <1>;
 575                                 /* 8 sample average control */
 576                                 st,ave-ctrl = <3>;
 577                                 /* 7 length fractional part in z */
 578                                 st,fraction-z = <7>;
 579                                 /*
 580                                  * 50 mA typical 80 mA max touchscreen drivers
 581                                  * current limit value
 582                                  */
 583                                 st,i-drive = <1>;
 584                                 /* 12-bit ADC */
 585                                 st,mod-12b = <1>;
 586                                 /* internal ADC reference */
 587                                 st,ref-sel = <0>;
 588                                 /* ADC converstion time: 80 clocks */
 589                                 st,sample-time = <4>;
 590                                 /* 1 ms panel driver settling time */
 591                                 st,settling = <3>;
 592                                 /* 5 ms touch detect interrupt delay */
 593                                 st,touch-det-delay = <5>;
 594                         };
 595                 };
 596
 597                 /*
 598                  * LM95245 temperature sensor
 599                  * Note: OVERT_N directly connected to PMIC PWRDN
 600                  */
 601                 temp-sensor@4c {
 602                         compatible = "national,lm95245";
 603                         reg = <0x4c>;
 604                 };
 605
 606                 /* SW: +V1.2_VDD_CORE */
 607                 tps62362@60 {
 608                         compatible = "ti,tps62362";
 609                         reg = <0x60>;
 610
 611                         regulator-name = "tps62362-vout";
 612                         regulator-min-microvolt = <900000>;
 613                         regulator-max-microvolt = <1400000>;
 614                         regulator-boot-on;
 615                         regulator-always-on;
 616                         ti,vsel0-state-low;
 617                         /* VSEL1: EN_CORE_DVFS_N low for DVFS */
 618                         ti,vsel1-state-low;
 619                 };
 620         };
 621
 622         /* SPI4: CAN2 */
 623         spi@7000da00 {
 624                 status = "okay";
 625                 spi-max-frequency = <10000000>;
 626
 627                 can@1 {
 628                         compatible = "microchip,mcp2515";
 629                         reg = <1>;
 630                         clocks = <&clk16m>;
 631                         interrupt-parent = <&gpio>;
 632                         interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
 633                         spi-max-frequency = <10000000>;
 634                 };
 635         };
 636
 637         /* SPI6: CAN1 */
 638         spi@7000de00 {
 639                 status = "okay";
 640                 spi-max-frequency = <10000000>;
 641
 642                 can@0 {
 643                         compatible = "microchip,mcp2515";
 644                         reg = <0>;
 645                         clocks = <&clk16m>;
 646                         interrupt-parent = <&gpio>;
 647                         interrupts = <TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
 648                         spi-max-frequency = <10000000>;
 649                 };
 650         };
 651
 652         pmc@7000e400 {
 653                 nvidia,invert-interrupt;
 654                 nvidia,suspend-mode = <1>;
 655                 nvidia,cpu-pwr-good-time = <5000>;
 656                 nvidia,cpu-pwr-off-time = <5000>;
 657                 nvidia,core-pwr-good-time = <3845 3845>;
 658                 nvidia,core-pwr-off-time = <0>;
 659                 nvidia,core-power-req-active-high;
 660                 nvidia,sys-clock-req-active-high;
 661         };
 662
 663         /* eMMC */
 664         sdhci@78000600 {
 665                 status = "okay";
 666                 bus-width = <8>;
 667                 non-removable;
 668         };
 669
 670         clocks {
 671                 compatible = "simple-bus";
 672                 #address-cells = <1>;
 673                 #size-cells = <0>;
 674
 675                 clk32k_in: clk@0 {
 676                         compatible = "fixed-clock";
 677                         reg=<0>;
 678                         #clock-cells = <0>;
 679                         clock-frequency = <32768>;
 680                 };
 681                 clk16m: clk@1 {
 682                         compatible = "fixed-clock";
 683                         reg=<1>;
 684                         #clock-cells = <0>;
 685                         clock-frequency = <16000000>;
 686                         clock-output-names = "clk16m";
 687                 };
 688         };
 689
 690         regulators {
 691                 compatible = "simple-bus";
 692                 #address-cells = <1>;
 693                 #size-cells = <0>;
 694
 695                 avdd_hdmi_pll_1v8_reg: regulator@100 {
 696                         compatible = "regulator-fixed";
 697                         reg = <100>;
 698                         regulator-name = "+V1.8_AVDD_HDMI_PLL";
 699                         regulator-min-microvolt = <1800000>;
 700                         regulator-max-microvolt = <1800000>;
 701                         enable-active-high;
 702                         gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 703                         vin-supply = <&vio_reg>;
 704                 };
 705
 706                 sys_3v3_reg: regulator@101 {
 707                         compatible = "regulator-fixed";
 708                         reg = <101>;
 709                         regulator-name = "3v3";
 710                         regulator-min-microvolt = <3300000>;
 711                         regulator-max-microvolt = <3300000>;
 712                         regulator-always-on;
 713                 };
 714
 715                 avdd_hdmi_3v3_reg: regulator@102 {
 716                         compatible = "regulator-fixed";
 717                         reg = <102>;
 718                         regulator-name = "+V3.3_AVDD_HDMI";
 719                         regulator-min-microvolt = <3300000>;
 720                         regulator-max-microvolt = <3300000>;
 721                         enable-active-high;
 722                         gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
 723                         vin-supply = <&sys_3v3_reg>;
 724                 };
 725
 726                 charge_pump_5v0_reg: regulator@103 {
 727                         compatible = "regulator-fixed";
 728                         reg = <103>;
 729                         regulator-name = "5v0";
 730                         regulator-min-microvolt = <5000000>;
 731                         regulator-max-microvolt = <5000000>;
 732                         regulator-always-on;
 733                 };
 734         };
 735 };