arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #define pr_fmt(fmt)     "AT91: " fmt
   9
  10 #include <linux/module.h>
  11 #include <linux/io.h>
  12 #include <linux/mm.h>
  13 #include <linux/pm.h>
  14 #include <linux/of_address.h>
  15 #include <linux/pinctrl/machine.h>
  16 #include <linux/clk/at91_pmc.h>
  17
  18 #include <asm/system_misc.h>
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/cpu.h>
  23 #include <mach/at91_dbgu.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "pm.h"
  28
  29 struct at91_init_soc __initdata at91_boot_soc;
  30
  31 struct at91_socinfo at91_soc_initdata;
  32 EXPORT_SYMBOL(at91_soc_initdata);
  33
  34 void __init at91rm9200_set_type(int type)
  35 {
  36         if (type == ARCH_REVISON_9200_PQFP)
  37                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  38         else
  39                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  40
  41         pr_info("filled in soc subtype: %s\n",
  42                 at91_get_soc_subtype(&at91_soc_initdata));
  43 }
  44
  45 void __init at91_init_irq_default(void)
  46 {
  47         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  48 }
  49
  50 void __init at91_init_interrupts(unsigned int *priority)
  51 {
  52         /* Enable GPIO interrupts */
  53         at91_gpio_irq_setup();
  54 }
  55
  56 void __iomem *at91_ramc_base[2];
  57 EXPORT_SYMBOL_GPL(at91_ramc_base);
  58
  59 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  60 {
  61         if (id < 0 || id > 1) {
  62                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  63                 BUG();
  64         }
  65         at91_ramc_base[id] = ioremap(addr, size);
  66         if (!at91_ramc_base[id])
  67                 panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
  68 }
  69
  70 static struct map_desc sram_desc[2] __initdata;
  71
  72 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  73 {
  74         struct map_desc *desc = &sram_desc[bank];
  75
  76         desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
  77         if (bank > 0)
  78                 desc->virtual -= sram_desc[bank - 1].length;
  79
  80         desc->pfn = __phys_to_pfn(base);
  81         desc->length = length;
  82         desc->type = MT_MEMORY_RWX_NONCACHED;
  83
  84         pr_info("sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  85                 base, length, desc->virtual);
  86
  87         iotable_init(desc, 1);
  88 }
  89
  90 static struct map_desc at91_io_desc __initdata __maybe_unused = {
  91         .virtual        = (unsigned long)AT91_VA_BASE_SYS,
  92         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  93         .length         = SZ_16K,
  94         .type           = MT_DEVICE,
  95 };
  96
  97 static struct map_desc at91_alt_io_desc __initdata __maybe_unused = {
  98         .virtual        = (unsigned long)AT91_ALT_VA_BASE_SYS,
  99         .pfn            = __phys_to_pfn(AT91_ALT_BASE_SYS),
 100         .length         = 24 * SZ_1K,
 101         .type           = MT_DEVICE,
 102 };
 103
 104 static void __init soc_detect(u32 dbgu_base)
 105 {
 106         u32 cidr, socid;
 107
 108         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 109         socid = cidr & ~AT91_CIDR_VERSION;
 110
 111         switch (socid) {
 112         case ARCH_ID_AT91RM9200:
 113                 at91_soc_initdata.type = AT91_SOC_RM9200;
 114                 if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN)
 115                         at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
 116                 at91_boot_soc = at91rm9200_soc;
 117                 break;
 118
 119         case ARCH_ID_AT91SAM9260:
 120                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 121                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 122                 at91_boot_soc = at91sam9260_soc;
 123                 break;
 124
 125         case ARCH_ID_AT91SAM9261:
 126                 at91_soc_initdata.type = AT91_SOC_SAM9261;
 127                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 128                 at91_boot_soc = at91sam9261_soc;
 129                 break;
 130
 131         case ARCH_ID_AT91SAM9263:
 132                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 133                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 134                 at91_boot_soc = at91sam9263_soc;
 135                 break;
 136
 137         case ARCH_ID_AT91SAM9G20:
 138                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 139                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 140                 at91_boot_soc = at91sam9260_soc;
 141                 break;
 142
 143         case ARCH_ID_AT91SAM9G45:
 144                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 145                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 146                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 147                 at91_boot_soc = at91sam9g45_soc;
 148                 break;
 149
 150         case ARCH_ID_AT91SAM9RL64:
 151                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 152                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 153                 at91_boot_soc = at91sam9rl_soc;
 154                 break;
 155
 156         case ARCH_ID_AT91SAM9X5:
 157                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 158                 at91_boot_soc = at91sam9x5_soc;
 159                 break;
 160
 161         case ARCH_ID_AT91SAM9N12:
 162                 at91_soc_initdata.type = AT91_SOC_SAM9N12;
 163                 at91_boot_soc = at91sam9n12_soc;
 164                 break;
 165
 166         case ARCH_ID_SAMA5:
 167                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 168                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 169                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 170                         at91_boot_soc = sama5d3_soc;
 171                 }
 172                 break;
 173         }
 174
 175         /* at91sam9g10 */
 176         if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 177                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 178                 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 179                 at91_boot_soc = at91sam9261_soc;
 180         }
 181         /* at91sam9xe */
 182         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 183                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 184                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 185                 at91_boot_soc = at91sam9260_soc;
 186         }
 187
 188         if (!at91_soc_is_detected())
 189                 return;
 190
 191         at91_soc_initdata.cidr = cidr;
 192
 193         /* sub version of soc */
 194         if (!at91_soc_initdata.exid)
 195                 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 196
 197         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 198                 switch (at91_soc_initdata.exid) {
 199                 case ARCH_EXID_AT91SAM9M10:
 200                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 201                         break;
 202                 case ARCH_EXID_AT91SAM9G46:
 203                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 204                         break;
 205                 case ARCH_EXID_AT91SAM9M11:
 206                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 207                         break;
 208                 }
 209         }
 210
 211         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 212                 switch (at91_soc_initdata.exid) {
 213                 case ARCH_EXID_AT91SAM9G15:
 214                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 215                         break;
 216                 case ARCH_EXID_AT91SAM9G35:
 217                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 218                         break;
 219                 case ARCH_EXID_AT91SAM9X35:
 220                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 221                         break;
 222                 case ARCH_EXID_AT91SAM9G25:
 223                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 224                         break;
 225                 case ARCH_EXID_AT91SAM9X25:
 226                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 227                         break;
 228                 }
 229         }
 230
 231         if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) {
 232                 switch (at91_soc_initdata.exid) {
 233                 case ARCH_EXID_SAMA5D31:
 234                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D31;
 235                         break;
 236                 case ARCH_EXID_SAMA5D33:
 237                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D33;
 238                         break;
 239                 case ARCH_EXID_SAMA5D34:
 240                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D34;
 241                         break;
 242                 case ARCH_EXID_SAMA5D35:
 243                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D35;
 244                         break;
 245                 case ARCH_EXID_SAMA5D36:
 246                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D36;
 247                         break;
 248                 }
 249         }
 250 }
 251
 252 static void __init alt_soc_detect(u32 dbgu_base)
 253 {
 254         u32 cidr, socid;
 255
 256         /* SoC ID */
 257         cidr = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 258         socid = cidr & ~AT91_CIDR_VERSION;
 259
 260         switch (socid) {
 261         case ARCH_ID_SAMA5:
 262                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 263                 if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D3) {
 264                         at91_soc_initdata.type = AT91_SOC_SAMA5D3;
 265                         at91_boot_soc = sama5d3_soc;
 266                 } else if (at91_soc_initdata.exid & ARCH_EXID_SAMA5D4) {
 267                         at91_soc_initdata.type = AT91_SOC_SAMA5D4;
 268                         at91_boot_soc = sama5d4_soc;
 269                 }
 270                 break;
 271         }
 272
 273         if (!at91_soc_is_detected())
 274                 return;
 275
 276         at91_soc_initdata.cidr = cidr;
 277
 278         /* sub version of soc */
 279         if (!at91_soc_initdata.exid)
 280                 at91_soc_initdata.exid = __raw_readl(AT91_ALT_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 281
 282         if (at91_soc_initdata.type == AT91_SOC_SAMA5D4) {
 283                 switch (at91_soc_initdata.exid) {
 284                 case ARCH_EXID_SAMA5D41:
 285                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D41;
 286                         break;
 287                 case ARCH_EXID_SAMA5D42:
 288                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D42;
 289                         break;
 290                 case ARCH_EXID_SAMA5D43:
 291                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D43;
 292                         break;
 293                 case ARCH_EXID_SAMA5D44:
 294                         at91_soc_initdata.subtype = AT91_SOC_SAMA5D44;
 295                         break;
 296                 }
 297         }
 298 }
 299
 300 static const char *soc_name[] = {
 301         [AT91_SOC_RM9200]       = "at91rm9200",
 302         [AT91_SOC_SAM9260]      = "at91sam9260",
 303         [AT91_SOC_SAM9261]      = "at91sam9261",
 304         [AT91_SOC_SAM9263]      = "at91sam9263",
 305         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 306         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 307         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 308         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 309         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 310         [AT91_SOC_SAM9N12]      = "at91sam9n12",
 311         [AT91_SOC_SAMA5D3]      = "sama5d3",
 312         [AT91_SOC_SAMA5D4]      = "sama5d4",
 313         [AT91_SOC_UNKNOWN]      = "Unknown",
 314 };
 315
 316 const char *at91_get_soc_type(struct at91_socinfo *c)
 317 {
 318         return soc_name[c->type];
 319 }
 320 EXPORT_SYMBOL(at91_get_soc_type);
 321
 322 static const char *soc_subtype_name[] = {
 323         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 324         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 325         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 326         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 327         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 328         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 329         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 330         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 331         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 332         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 333         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 334         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 335         [AT91_SOC_SAMA5D31]     = "sama5d31",
 336         [AT91_SOC_SAMA5D33]     = "sama5d33",
 337         [AT91_SOC_SAMA5D34]     = "sama5d34",
 338         [AT91_SOC_SAMA5D35]     = "sama5d35",
 339         [AT91_SOC_SAMA5D36]     = "sama5d36",
 340         [AT91_SOC_SAMA5D41]     = "sama5d41",
 341         [AT91_SOC_SAMA5D42]     = "sama5d42",
 342         [AT91_SOC_SAMA5D43]     = "sama5d43",
 343         [AT91_SOC_SAMA5D44]     = "sama5d44",
 344         [AT91_SOC_SUBTYPE_NONE] = "None",
 345         [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown",
 346 };
 347
 348 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 349 {
 350         return soc_subtype_name[c->subtype];
 351 }
 352 EXPORT_SYMBOL(at91_get_soc_subtype);
 353
 354 void __init at91_map_io(void)
 355 {
 356         /* Map peripherals */
 357         iotable_init(&at91_io_desc, 1);
 358
 359         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 360         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 361
 362         soc_detect(AT91_BASE_DBGU0);
 363         if (!at91_soc_is_detected())
 364                 soc_detect(AT91_BASE_DBGU1);
 365
 366         if (!at91_soc_is_detected())
 367                 panic(pr_fmt("Impossible to detect the SOC type"));
 368
 369         pr_info("Detected soc type: %s\n",
 370                 at91_get_soc_type(&at91_soc_initdata));
 371         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 372                 pr_info("Detected soc subtype: %s\n",
 373                         at91_get_soc_subtype(&at91_soc_initdata));
 374
 375         if (!at91_soc_is_enabled())
 376                 panic(pr_fmt("Soc not enabled"));
 377
 378         if (at91_boot_soc.map_io)
 379                 at91_boot_soc.map_io();
 380 }
 381
 382 void __init at91_alt_map_io(void)
 383 {
 384         /* Map peripherals */
 385         iotable_init(&at91_alt_io_desc, 1);
 386
 387         at91_soc_initdata.type = AT91_SOC_UNKNOWN;
 388         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN;
 389
 390         alt_soc_detect(AT91_BASE_DBGU2);
 391         if (!at91_soc_is_detected())
 392                 panic("AT91: Impossible to detect the SOC type");
 393
 394         pr_info("AT91: Detected soc type: %s\n",
 395                 at91_get_soc_type(&at91_soc_initdata));
 396         if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE)
 397                 pr_info("AT91: Detected soc subtype: %s\n",
 398                         at91_get_soc_subtype(&at91_soc_initdata));
 399
 400         if (!at91_soc_is_enabled())
 401                 panic("AT91: Soc not enabled");
 402
 403         if (at91_boot_soc.map_io)
 404                 at91_boot_soc.map_io();
 405 }
 406
 407 void __iomem *at91_matrix_base;
 408 EXPORT_SYMBOL_GPL(at91_matrix_base);
 409
 410 void __init at91_ioremap_matrix(u32 base_addr)
 411 {
 412         at91_matrix_base = ioremap(base_addr, 512);
 413         if (!at91_matrix_base)
 414                 panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
 415 }
 416
 417 #if defined(CONFIG_OF)
 418 static struct of_device_id ramc_ids[] = {
 419         { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
 420         { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
 421         { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
 422         { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
 423         { /*sentinel*/ }
 424 };
 425
 426 static void at91_dt_ramc(void)
 427 {
 428         struct device_node *np;
 429         const struct of_device_id *of_id;
 430         int idx = 0;
 431         const void *standby = NULL;
 432
 433         for_each_matching_node_and_match(np, ramc_ids, &of_id) {
 434                 at91_ramc_base[idx] = of_iomap(np, 0);
 435                 if (!at91_ramc_base[idx])
 436                         panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
 437
 438                 if (!standby)
 439                         standby = of_id->data;
 440
 441                 idx++;
 442         }
 443
 444         if (!idx)
 445                 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
 446
 447         if (!standby) {
 448                 pr_warn("ramc no standby function available\n");
 449                 return;
 450         }
 451
 452         at91_pm_set_standby(standby);
 453 }
 454
 455 void __init at91rm9200_dt_initialize(void)
 456 {
 457         at91_dt_ramc();
 458
 459         /* Register the processor-specific clocks */
 460         if (at91_boot_soc.register_clocks)
 461                 at91_boot_soc.register_clocks();
 462
 463         at91_boot_soc.init();
 464 }
 465
 466 void __init at91_dt_initialize(void)
 467 {
 468         at91_dt_ramc();
 469
 470         /* Register the processor-specific clocks */
 471         if (at91_boot_soc.register_clocks)
 472                 at91_boot_soc.register_clocks();
 473
 474         if (at91_boot_soc.init)
 475                 at91_boot_soc.init();
 476 }
 477 #endif
 478
 479 void __init at91_initialize(unsigned long main_clock)
 480 {
 481         at91_boot_soc.ioremap_registers();
 482
 483         /* Register the processor-specific clocks */
 484         at91_boot_soc.register_clocks();
 485
 486         at91_boot_soc.init();
 487
 488         pinctrl_provide_dummies();
 489 }
 490
 491 void __init at91_register_devices(void)
 492 {
 493         at91_boot_soc.register_devices();
 494 }
 495
 496 void __init at91_init_time(void)
 497 {
 498         at91_boot_soc.init_time();
 499 }