Merge remote-tracking branch 'samsung/for-next'
[karo-tx-linux.git] / arch / arm / mach-exynos / suspend.c
1 /*
2  * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3  *              http://www.samsung.com
4  *
5  * EXYNOS - Suspend support
6  *
7  * Based on arch/arm/mach-s3c2410/pm.c
8  * Copyright (c) 2006 Simtec Electronics
9  *      Ben Dooks <ben@simtec.co.uk>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15
16 #include <linux/init.h>
17 #include <linux/suspend.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/io.h>
21 #include <linux/irq.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqdomain.h>
24 #include <linux/of_address.h>
25 #include <linux/err.h>
26 #include <linux/regulator/machine.h>
27
28 #include <asm/cacheflush.h>
29 #include <asm/hardware/cache-l2x0.h>
30 #include <asm/firmware.h>
31 #include <asm/mcpm.h>
32 #include <asm/smp_scu.h>
33 #include <asm/suspend.h>
34
35 #include <mach/map.h>
36
37 #include <plat/pm-common.h>
38
39 #include "common.h"
40 #include "exynos-pmu.h"
41 #include "regs-pmu.h"
42
43 #define REG_TABLE_END (-1U)
44
45 #define EXYNOS5420_CPU_STATE    0x28
46
47 /**
48  * struct exynos_wkup_irq - PMU IRQ to mask mapping
49  * @hwirq: Hardware IRQ signal of the PMU
50  * @mask: Mask in PMU wake-up mask register
51  */
52 struct exynos_wkup_irq {
53         unsigned int hwirq;
54         u32 mask;
55 };
56
57 struct exynos_pm_data {
58         const struct exynos_wkup_irq *wkup_irq;
59         unsigned int wake_disable_mask;
60         unsigned int *release_ret_regs;
61
62         void (*pm_prepare)(void);
63         void (*pm_resume_prepare)(void);
64         void (*pm_resume)(void);
65         int (*pm_suspend)(void);
66         int (*cpu_suspend)(unsigned long);
67 };
68
69 static const struct exynos_pm_data *pm_data;
70
71 static int exynos5420_cpu_state;
72 static unsigned int exynos_pmu_spare3;
73
74 /*
75  * GIC wake-up support
76  */
77
78 static u32 exynos_irqwake_intmask = 0xffffffff;
79
80 static const struct exynos_wkup_irq exynos3250_wkup_irq[] = {
81         { 73, BIT(1) }, /* RTC alarm */
82         { 74, BIT(2) }, /* RTC tick */
83         { /* sentinel */ },
84 };
85
86 static const struct exynos_wkup_irq exynos4_wkup_irq[] = {
87         { 44, BIT(1) }, /* RTC alarm */
88         { 45, BIT(2) }, /* RTC tick */
89         { /* sentinel */ },
90 };
91
92 static const struct exynos_wkup_irq exynos5250_wkup_irq[] = {
93         { 43, BIT(1) }, /* RTC alarm */
94         { 44, BIT(2) }, /* RTC tick */
95         { /* sentinel */ },
96 };
97
98 static unsigned int exynos_release_ret_regs[] = {
99         S5P_PAD_RET_MAUDIO_OPTION,
100         S5P_PAD_RET_GPIO_OPTION,
101         S5P_PAD_RET_UART_OPTION,
102         S5P_PAD_RET_MMCA_OPTION,
103         S5P_PAD_RET_MMCB_OPTION,
104         S5P_PAD_RET_EBIA_OPTION,
105         S5P_PAD_RET_EBIB_OPTION,
106         REG_TABLE_END,
107 };
108
109 static unsigned int exynos3250_release_ret_regs[] = {
110         S5P_PAD_RET_MAUDIO_OPTION,
111         S5P_PAD_RET_GPIO_OPTION,
112         S5P_PAD_RET_UART_OPTION,
113         S5P_PAD_RET_MMCA_OPTION,
114         S5P_PAD_RET_MMCB_OPTION,
115         S5P_PAD_RET_EBIA_OPTION,
116         S5P_PAD_RET_EBIB_OPTION,
117         S5P_PAD_RET_MMC2_OPTION,
118         S5P_PAD_RET_SPI_OPTION,
119         REG_TABLE_END,
120 };
121
122 static unsigned int exynos5420_release_ret_regs[] = {
123         EXYNOS_PAD_RET_DRAM_OPTION,
124         EXYNOS_PAD_RET_MAUDIO_OPTION,
125         EXYNOS_PAD_RET_JTAG_OPTION,
126         EXYNOS5420_PAD_RET_GPIO_OPTION,
127         EXYNOS5420_PAD_RET_UART_OPTION,
128         EXYNOS5420_PAD_RET_MMCA_OPTION,
129         EXYNOS5420_PAD_RET_MMCB_OPTION,
130         EXYNOS5420_PAD_RET_MMCC_OPTION,
131         EXYNOS5420_PAD_RET_HSI_OPTION,
132         EXYNOS_PAD_RET_EBIA_OPTION,
133         EXYNOS_PAD_RET_EBIB_OPTION,
134         EXYNOS5420_PAD_RET_SPI_OPTION,
135         EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
136         REG_TABLE_END,
137 };
138
139 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
140 {
141         const struct exynos_wkup_irq *wkup_irq;
142
143         if (!pm_data->wkup_irq)
144                 return -ENOENT;
145         wkup_irq = pm_data->wkup_irq;
146
147         while (wkup_irq->mask) {
148                 if (wkup_irq->hwirq == data->hwirq) {
149                         if (!state)
150                                 exynos_irqwake_intmask |= wkup_irq->mask;
151                         else
152                                 exynos_irqwake_intmask &= ~wkup_irq->mask;
153                         return 0;
154                 }
155                 ++wkup_irq;
156         }
157
158         return -ENOENT;
159 }
160
161 static struct irq_chip exynos_pmu_chip = {
162         .name                   = "PMU",
163         .irq_eoi                = irq_chip_eoi_parent,
164         .irq_mask               = irq_chip_mask_parent,
165         .irq_unmask             = irq_chip_unmask_parent,
166         .irq_retrigger          = irq_chip_retrigger_hierarchy,
167         .irq_set_wake           = exynos_irq_set_wake,
168 #ifdef CONFIG_SMP
169         .irq_set_affinity       = irq_chip_set_affinity_parent,
170 #endif
171 };
172
173 static int exynos_pmu_domain_translate(struct irq_domain *d,
174                                        struct irq_fwspec *fwspec,
175                                        unsigned long *hwirq,
176                                        unsigned int *type)
177 {
178         if (is_of_node(fwspec->fwnode)) {
179                 if (fwspec->param_count != 3)
180                         return -EINVAL;
181
182                 /* No PPI should point to this domain */
183                 if (fwspec->param[0] != 0)
184                         return -EINVAL;
185
186                 *hwirq = fwspec->param[1];
187                 *type = fwspec->param[2];
188                 return 0;
189         }
190
191         return -EINVAL;
192 }
193
194 static int exynos_pmu_domain_alloc(struct irq_domain *domain,
195                                    unsigned int virq,
196                                    unsigned int nr_irqs, void *data)
197 {
198         struct irq_fwspec *fwspec = data;
199         struct irq_fwspec parent_fwspec;
200         irq_hw_number_t hwirq;
201         int i;
202
203         if (fwspec->param_count != 3)
204                 return -EINVAL; /* Not GIC compliant */
205         if (fwspec->param[0] != 0)
206                 return -EINVAL; /* No PPI should point to this domain */
207
208         hwirq = fwspec->param[1];
209
210         for (i = 0; i < nr_irqs; i++)
211                 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
212                                               &exynos_pmu_chip, NULL);
213
214         parent_fwspec = *fwspec;
215         parent_fwspec.fwnode = domain->parent->fwnode;
216         return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
217                                             &parent_fwspec);
218 }
219
220 static const struct irq_domain_ops exynos_pmu_domain_ops = {
221         .translate      = exynos_pmu_domain_translate,
222         .alloc          = exynos_pmu_domain_alloc,
223         .free           = irq_domain_free_irqs_common,
224 };
225
226 static int __init exynos_pmu_irq_init(struct device_node *node,
227                                       struct device_node *parent)
228 {
229         struct irq_domain *parent_domain, *domain;
230
231         if (!parent) {
232                 pr_err("%s: no parent, giving up\n", node->full_name);
233                 return -ENODEV;
234         }
235
236         parent_domain = irq_find_host(parent);
237         if (!parent_domain) {
238                 pr_err("%s: unable to obtain parent domain\n", node->full_name);
239                 return -ENXIO;
240         }
241
242         pmu_base_addr = of_iomap(node, 0);
243
244         if (!pmu_base_addr) {
245                 pr_err("%s: failed to find exynos pmu register\n",
246                        node->full_name);
247                 return -ENOMEM;
248         }
249
250         domain = irq_domain_add_hierarchy(parent_domain, 0, 0,
251                                           node, &exynos_pmu_domain_ops,
252                                           NULL);
253         if (!domain) {
254                 iounmap(pmu_base_addr);
255                 return -ENOMEM;
256         }
257
258         return 0;
259 }
260
261 #define EXYNOS_PMU_IRQ(symbol, name)    IRQCHIP_DECLARE(symbol, name, exynos_pmu_irq_init)
262
263 EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu");
264 EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
265 EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
266 EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
267 EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu");
268 EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
269 EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
270
271 static int exynos_cpu_do_idle(void)
272 {
273         /* issue the standby signal into the pm unit. */
274         cpu_do_idle();
275
276         pr_info("Failed to suspend the system\n");
277         return 1; /* Aborting suspend */
278 }
279 static void exynos_flush_cache_all(void)
280 {
281         flush_cache_all();
282         outer_flush_all();
283 }
284
285 static int exynos_cpu_suspend(unsigned long arg)
286 {
287         exynos_flush_cache_all();
288         return exynos_cpu_do_idle();
289 }
290
291 static int exynos3250_cpu_suspend(unsigned long arg)
292 {
293         flush_cache_all();
294         return exynos_cpu_do_idle();
295 }
296
297 static int exynos5420_cpu_suspend(unsigned long arg)
298 {
299         /* MCPM works with HW CPU identifiers */
300         unsigned int mpidr = read_cpuid_mpidr();
301         unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
302         unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
303
304         __raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
305
306         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM)) {
307                 mcpm_set_entry_vector(cpu, cluster, exynos_cpu_resume);
308                 mcpm_cpu_suspend();
309         }
310
311         pr_info("Failed to suspend the system\n");
312
313         /* return value != 0 means failure */
314         return 1;
315 }
316
317 static void exynos_pm_set_wakeup_mask(void)
318 {
319         /* Set wake-up mask registers */
320         pmu_raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
321         pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
322 }
323
324 static void exynos_pm_enter_sleep_mode(void)
325 {
326         /* Set value of power down register for sleep mode */
327         exynos_sys_powerdown_conf(SYS_SLEEP);
328         pmu_raw_writel(EXYNOS_SLEEP_MAGIC, S5P_INFORM1);
329 }
330
331 static void exynos_pm_prepare(void)
332 {
333         exynos_set_delayed_reset_assertion(false);
334
335         /* Set wake-up mask registers */
336         exynos_pm_set_wakeup_mask();
337
338         exynos_pm_enter_sleep_mode();
339
340         /* ensure at least INFORM0 has the resume address */
341         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
342 }
343
344 static void exynos3250_pm_prepare(void)
345 {
346         unsigned int tmp;
347
348         /* Set wake-up mask registers */
349         exynos_pm_set_wakeup_mask();
350
351         tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
352         tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
353         pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
354
355         exynos_pm_enter_sleep_mode();
356
357         /* ensure at least INFORM0 has the resume address */
358         pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
359 }
360
361 static void exynos5420_pm_prepare(void)
362 {
363         unsigned int tmp;
364
365         /* Set wake-up mask registers */
366         exynos_pm_set_wakeup_mask();
367
368         exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
369         /*
370          * The cpu state needs to be saved and restored so that the
371          * secondary CPUs will enter low power start. Though the U-Boot
372          * is setting the cpu state with low power flag, the kernel
373          * needs to restore it back in case, the primary cpu fails to
374          * suspend for any reason.
375          */
376         exynos5420_cpu_state = __raw_readl(sysram_base_addr +
377                                                 EXYNOS5420_CPU_STATE);
378
379         exynos_pm_enter_sleep_mode();
380
381         /* ensure at least INFORM0 has the resume address */
382         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
383                 pmu_raw_writel(virt_to_phys(mcpm_entry_point), S5P_INFORM0);
384
385         tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
386         tmp &= ~EXYNOS5_USE_RETENTION;
387         pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
388
389         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
390         tmp |= EXYNOS5420_UFS;
391         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
392
393         tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
394         tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
395         pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
396
397         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
398         tmp |= EXYNOS5420_EMULATION;
399         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
400
401         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
402         tmp |= EXYNOS5420_EMULATION;
403         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
404 }
405
406
407 static int exynos_pm_suspend(void)
408 {
409         exynos_pm_central_suspend();
410
411         /* Setting SEQ_OPTION register */
412         pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
413                        S5P_CENTRAL_SEQ_OPTION);
414
415         if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
416                 exynos_cpu_save_register();
417
418         return 0;
419 }
420
421 static int exynos5420_pm_suspend(void)
422 {
423         u32 this_cluster;
424
425         exynos_pm_central_suspend();
426
427         /* Setting SEQ_OPTION register */
428
429         this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
430         if (!this_cluster)
431                 pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
432                                 S5P_CENTRAL_SEQ_OPTION);
433         else
434                 pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
435                                 S5P_CENTRAL_SEQ_OPTION);
436         return 0;
437 }
438
439 static void exynos_pm_release_retention(void)
440 {
441         unsigned int i;
442
443         for (i = 0; (pm_data->release_ret_regs[i] != REG_TABLE_END); i++)
444                 pmu_raw_writel(EXYNOS_WAKEUP_FROM_LOWPWR,
445                                 pm_data->release_ret_regs[i]);
446 }
447
448 static void exynos_pm_resume(void)
449 {
450         u32 cpuid = read_cpuid_part();
451
452         if (exynos_pm_central_resume())
453                 goto early_wakeup;
454
455         /* For release retention */
456         exynos_pm_release_retention();
457
458         if (cpuid == ARM_CPU_PART_CORTEX_A9)
459                 scu_enable(S5P_VA_SCU);
460
461         if (call_firmware_op(resume) == -ENOSYS
462             && cpuid == ARM_CPU_PART_CORTEX_A9)
463                 exynos_cpu_restore_register();
464
465 early_wakeup:
466
467         /* Clear SLEEP mode set in INFORM1 */
468         pmu_raw_writel(0x0, S5P_INFORM1);
469         exynos_set_delayed_reset_assertion(true);
470 }
471
472 static void exynos3250_pm_resume(void)
473 {
474         u32 cpuid = read_cpuid_part();
475
476         if (exynos_pm_central_resume())
477                 goto early_wakeup;
478
479         /* For release retention */
480         exynos_pm_release_retention();
481
482         pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
483
484         if (call_firmware_op(resume) == -ENOSYS
485             && cpuid == ARM_CPU_PART_CORTEX_A9)
486                 exynos_cpu_restore_register();
487
488 early_wakeup:
489
490         /* Clear SLEEP mode set in INFORM1 */
491         pmu_raw_writel(0x0, S5P_INFORM1);
492 }
493
494 static void exynos5420_prepare_pm_resume(void)
495 {
496         if (IS_ENABLED(CONFIG_EXYNOS5420_MCPM))
497                 WARN_ON(mcpm_cpu_powered_up());
498 }
499
500 static void exynos5420_pm_resume(void)
501 {
502         unsigned long tmp;
503
504         /* Restore the CPU0 low power state register */
505         tmp = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
506         pmu_raw_writel(tmp | S5P_CORE_LOCAL_PWR_EN,
507                 EXYNOS5_ARM_CORE0_SYS_PWR_REG);
508
509         /* Restore the sysram cpu state register */
510         __raw_writel(exynos5420_cpu_state,
511                 sysram_base_addr + EXYNOS5420_CPU_STATE);
512
513         pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
514                         S5P_CENTRAL_SEQ_OPTION);
515
516         if (exynos_pm_central_resume())
517                 goto early_wakeup;
518
519         /* For release retention */
520         exynos_pm_release_retention();
521
522         pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
523
524 early_wakeup:
525
526         tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
527         tmp &= ~EXYNOS5420_UFS;
528         pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
529
530         tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
531         tmp &= ~EXYNOS5420_EMULATION;
532         pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
533
534         tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
535         tmp &= ~EXYNOS5420_EMULATION;
536         pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
537
538         /* Clear SLEEP mode set in INFORM1 */
539         pmu_raw_writel(0x0, S5P_INFORM1);
540 }
541
542 /*
543  * Suspend Ops
544  */
545
546 static int exynos_suspend_enter(suspend_state_t state)
547 {
548         int ret;
549
550         s3c_pm_debug_init();
551
552         S3C_PMDBG("%s: suspending the system...\n", __func__);
553
554         S3C_PMDBG("%s: wakeup masks: %08x,%08x\n", __func__,
555                         exynos_irqwake_intmask, exynos_get_eint_wake_mask());
556
557         if (exynos_irqwake_intmask == -1U
558             && exynos_get_eint_wake_mask() == -1U) {
559                 pr_err("%s: No wake-up sources!\n", __func__);
560                 pr_err("%s: Aborting sleep\n", __func__);
561                 return -EINVAL;
562         }
563
564         s3c_pm_save_uarts();
565         if (pm_data->pm_prepare)
566                 pm_data->pm_prepare();
567         flush_cache_all();
568         s3c_pm_check_store();
569
570         ret = call_firmware_op(suspend);
571         if (ret == -ENOSYS)
572                 ret = cpu_suspend(0, pm_data->cpu_suspend);
573         if (ret)
574                 return ret;
575
576         if (pm_data->pm_resume_prepare)
577                 pm_data->pm_resume_prepare();
578         s3c_pm_restore_uarts();
579
580         S3C_PMDBG("%s: wakeup stat: %08x\n", __func__,
581                         pmu_raw_readl(S5P_WAKEUP_STAT));
582
583         s3c_pm_check_restore();
584
585         S3C_PMDBG("%s: resuming the system...\n", __func__);
586
587         return 0;
588 }
589
590 static int exynos_suspend_prepare(void)
591 {
592         int ret;
593
594         /*
595          * REVISIT: It would be better if struct platform_suspend_ops
596          * .prepare handler get the suspend_state_t as a parameter to
597          * avoid hard-coding the suspend to mem state. It's safe to do
598          * it now only because the suspend_valid_only_mem function is
599          * used as the .valid callback used to check if a given state
600          * is supported by the platform anyways.
601          */
602         ret = regulator_suspend_prepare(PM_SUSPEND_MEM);
603         if (ret) {
604                 pr_err("Failed to prepare regulators for suspend (%d)\n", ret);
605                 return ret;
606         }
607
608         s3c_pm_check_prepare();
609
610         return 0;
611 }
612
613 static void exynos_suspend_finish(void)
614 {
615         int ret;
616
617         s3c_pm_check_cleanup();
618
619         ret = regulator_suspend_finish();
620         if (ret)
621                 pr_warn("Failed to resume regulators from suspend (%d)\n", ret);
622 }
623
624 static const struct platform_suspend_ops exynos_suspend_ops = {
625         .enter          = exynos_suspend_enter,
626         .prepare        = exynos_suspend_prepare,
627         .finish         = exynos_suspend_finish,
628         .valid          = suspend_valid_only_mem,
629 };
630
631 static const struct exynos_pm_data exynos3250_pm_data = {
632         .wkup_irq       = exynos3250_wkup_irq,
633         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
634         .release_ret_regs = exynos3250_release_ret_regs,
635         .pm_suspend     = exynos_pm_suspend,
636         .pm_resume      = exynos3250_pm_resume,
637         .pm_prepare     = exynos3250_pm_prepare,
638         .cpu_suspend    = exynos3250_cpu_suspend,
639 };
640
641 static const struct exynos_pm_data exynos4_pm_data = {
642         .wkup_irq       = exynos4_wkup_irq,
643         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
644         .release_ret_regs = exynos_release_ret_regs,
645         .pm_suspend     = exynos_pm_suspend,
646         .pm_resume      = exynos_pm_resume,
647         .pm_prepare     = exynos_pm_prepare,
648         .cpu_suspend    = exynos_cpu_suspend,
649 };
650
651 static const struct exynos_pm_data exynos5250_pm_data = {
652         .wkup_irq       = exynos5250_wkup_irq,
653         .wake_disable_mask = ((0xFF << 8) | (0x1F << 1)),
654         .release_ret_regs = exynos_release_ret_regs,
655         .pm_suspend     = exynos_pm_suspend,
656         .pm_resume      = exynos_pm_resume,
657         .pm_prepare     = exynos_pm_prepare,
658         .cpu_suspend    = exynos_cpu_suspend,
659 };
660
661 static const struct exynos_pm_data exynos5420_pm_data = {
662         .wkup_irq       = exynos5250_wkup_irq,
663         .wake_disable_mask = (0x7F << 7) | (0x1F << 1),
664         .release_ret_regs = exynos5420_release_ret_regs,
665         .pm_resume_prepare = exynos5420_prepare_pm_resume,
666         .pm_resume      = exynos5420_pm_resume,
667         .pm_suspend     = exynos5420_pm_suspend,
668         .pm_prepare     = exynos5420_pm_prepare,
669         .cpu_suspend    = exynos5420_cpu_suspend,
670 };
671
672 static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = {
673         {
674                 .compatible = "samsung,exynos3250-pmu",
675                 .data = &exynos3250_pm_data,
676         }, {
677                 .compatible = "samsung,exynos4210-pmu",
678                 .data = &exynos4_pm_data,
679         }, {
680                 .compatible = "samsung,exynos4212-pmu",
681                 .data = &exynos4_pm_data,
682         }, {
683                 .compatible = "samsung,exynos4412-pmu",
684                 .data = &exynos4_pm_data,
685         }, {
686                 .compatible = "samsung,exynos5250-pmu",
687                 .data = &exynos5250_pm_data,
688         }, {
689                 .compatible = "samsung,exynos5420-pmu",
690                 .data = &exynos5420_pm_data,
691         },
692         { /*sentinel*/ },
693 };
694
695 static struct syscore_ops exynos_pm_syscore_ops;
696
697 void __init exynos_pm_init(void)
698 {
699         const struct of_device_id *match;
700         struct device_node *np;
701         u32 tmp;
702
703         np = of_find_matching_node_and_match(NULL, exynos_pmu_of_device_ids, &match);
704         if (!np) {
705                 pr_err("Failed to find PMU node\n");
706                 return;
707         }
708
709         if (WARN_ON(!of_find_property(np, "interrupt-controller", NULL))) {
710                 pr_warn("Outdated DT detected, suspend/resume will NOT work\n");
711                 return;
712         }
713
714         pm_data = (const struct exynos_pm_data *) match->data;
715
716         /* All wakeup disable */
717         tmp = pmu_raw_readl(S5P_WAKEUP_MASK);
718         tmp |= pm_data->wake_disable_mask;
719         pmu_raw_writel(tmp, S5P_WAKEUP_MASK);
720
721         exynos_pm_syscore_ops.suspend   = pm_data->pm_suspend;
722         exynos_pm_syscore_ops.resume    = pm_data->pm_resume;
723
724         register_syscore_ops(&exynos_pm_syscore_ops);
725         suspend_set_ops(&exynos_suspend_ops);
726 }