arch/arm/mach-omap2/omap_hwmod_33xx_43xx_interconnect_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Interconnects common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/sizes.h>
  18 #include "omap_hwmod.h"
  19 #include "omap_hwmod_33xx_43xx_common_data.h"
  20
  21 /* mpu -> l3 main */
  22 struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
  23         .master         = &am33xx_mpu_hwmod,
  24         .slave          = &am33xx_l3_main_hwmod,
  25         .clk            = "dpll_mpu_m2_ck",
  26         .user           = OCP_USER_MPU,
  27 };
  28
  29 /* l3 main -> l3 s */
  30 struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
  31         .master         = &am33xx_l3_main_hwmod,
  32         .slave          = &am33xx_l3_s_hwmod,
  33         .clk            = "l3s_gclk",
  34         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  35 };
  36
  37 /* l3 s -> l4 per/ls */
  38 struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
  39         .master         = &am33xx_l3_s_hwmod,
  40         .slave          = &am33xx_l4_ls_hwmod,
  41         .clk            = "l3s_gclk",
  42         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  43 };
  44
  45 /* l3 s -> l4 wkup */
  46 struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
  47         .master         = &am33xx_l3_s_hwmod,
  48         .slave          = &am33xx_l4_wkup_hwmod,
  49         .clk            = "l3s_gclk",
  50         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  51 };
  52
  53 /* l3 main -> l3 instr */
  54 struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
  55         .master         = &am33xx_l3_main_hwmod,
  56         .slave          = &am33xx_l3_instr_hwmod,
  57         .clk            = "l3s_gclk",
  58         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  59 };
  60
  61 /* mpu -> prcm */
  62 struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
  63         .master         = &am33xx_mpu_hwmod,
  64         .slave          = &am33xx_prcm_hwmod,
  65         .clk            = "dpll_mpu_m2_ck",
  66         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  67 };
  68
  69 /* l3 s -> l3 main*/
  70 struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
  71         .master         = &am33xx_l3_s_hwmod,
  72         .slave          = &am33xx_l3_main_hwmod,
  73         .clk            = "l3s_gclk",
  74         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  75 };
  76
  77 /* pru-icss -> l3 main */
  78 struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
  79         .master         = &am33xx_pruss_hwmod,
  80         .slave          = &am33xx_l3_main_hwmod,
  81         .clk            = "l3_gclk",
  82         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  83 };
  84
  85 /* gfx -> l3 main */
  86 struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
  87         .master         = &am33xx_gfx_hwmod,
  88         .slave          = &am33xx_l3_main_hwmod,
  89         .clk            = "dpll_core_m4_ck",
  90         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  91 };
  92
  93 /* l3 main -> gfx */
  94 struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
  95         .master         = &am33xx_l3_main_hwmod,
  96         .slave          = &am33xx_gfx_hwmod,
  97         .clk            = "dpll_core_m4_ck",
  98         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  99 };
 100
 101 /* l4 wkup -> rtc */
 102 struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
 103         .master         = &am33xx_l4_wkup_hwmod,
 104         .slave          = &am33xx_rtc_hwmod,
 105         .clk            = "clkdiv32k_ick",
 106         .user           = OCP_USER_MPU,
 107 };
 108
 109 /* l4 per/ls -> DCAN0 */
 110 struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
 111         .master         = &am33xx_l4_ls_hwmod,
 112         .slave          = &am33xx_dcan0_hwmod,
 113         .clk            = "l4ls_gclk",
 114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 115 };
 116
 117 /* l4 per/ls -> DCAN1 */
 118 struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
 119         .master         = &am33xx_l4_ls_hwmod,
 120         .slave          = &am33xx_dcan1_hwmod,
 121         .clk            = "l4ls_gclk",
 122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 123 };
 124
 125 /* l4 per/ls -> GPIO2 */
 126 struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
 127         .master         = &am33xx_l4_ls_hwmod,
 128         .slave          = &am33xx_gpio1_hwmod,
 129         .clk            = "l4ls_gclk",
 130         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 131 };
 132
 133 /* l4 per/ls -> gpio3 */
 134 struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
 135         .master         = &am33xx_l4_ls_hwmod,
 136         .slave          = &am33xx_gpio2_hwmod,
 137         .clk            = "l4ls_gclk",
 138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 139 };
 140
 141 /* l4 per/ls -> gpio4 */
 142 struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
 143         .master         = &am33xx_l4_ls_hwmod,
 144         .slave          = &am33xx_gpio3_hwmod,
 145         .clk            = "l4ls_gclk",
 146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 147 };
 148
 149 struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
 150         .master         = &am33xx_cpgmac0_hwmod,
 151         .slave          = &am33xx_mdio_hwmod,
 152         .user           = OCP_USER_MPU,
 153 };
 154
 155 struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
 156         .master         = &am33xx_l4_ls_hwmod,
 157         .slave          = &am33xx_elm_hwmod,
 158         .clk            = "l4ls_gclk",
 159         .user           = OCP_USER_MPU,
 160 };
 161
 162 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
 163         {
 164                 .pa_start       = 0x48300000,
 165                 .pa_end         = 0x48300000 + SZ_16 - 1,
 166                 .flags          = ADDR_TYPE_RT
 167         },
 168         { }
 169 };
 170
 171 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
 172         .master         = &am33xx_l4_ls_hwmod,
 173         .slave          = &am33xx_epwmss0_hwmod,
 174         .clk            = "l4ls_gclk",
 175         .addr           = am33xx_epwmss0_addr_space,
 176         .user           = OCP_USER_MPU,
 177 };
 178
 179 struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
 180         .master         = &am33xx_epwmss0_hwmod,
 181         .slave          = &am33xx_ecap0_hwmod,
 182         .clk            = "l4ls_gclk",
 183         .user           = OCP_USER_MPU,
 184 };
 185
 186 struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
 187         .master         = &am33xx_epwmss0_hwmod,
 188         .slave          = &am33xx_eqep0_hwmod,
 189         .clk            = "l4ls_gclk",
 190         .user           = OCP_USER_MPU,
 191 };
 192
 193 struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
 194         .master         = &am33xx_epwmss0_hwmod,
 195         .slave          = &am33xx_ehrpwm0_hwmod,
 196         .clk            = "l4ls_gclk",
 197         .user           = OCP_USER_MPU,
 198 };
 199
 200
 201 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
 202         {
 203                 .pa_start       = 0x48302000,
 204                 .pa_end         = 0x48302000 + SZ_16 - 1,
 205                 .flags          = ADDR_TYPE_RT
 206         },
 207         { }
 208 };
 209
 210 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
 211         .master         = &am33xx_l4_ls_hwmod,
 212         .slave          = &am33xx_epwmss1_hwmod,
 213         .clk            = "l4ls_gclk",
 214         .addr           = am33xx_epwmss1_addr_space,
 215         .user           = OCP_USER_MPU,
 216 };
 217
 218 struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
 219         .master         = &am33xx_epwmss1_hwmod,
 220         .slave          = &am33xx_ecap1_hwmod,
 221         .clk            = "l4ls_gclk",
 222         .user           = OCP_USER_MPU,
 223 };
 224
 225 struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
 226         .master         = &am33xx_epwmss1_hwmod,
 227         .slave          = &am33xx_eqep1_hwmod,
 228         .clk            = "l4ls_gclk",
 229         .user           = OCP_USER_MPU,
 230 };
 231
 232 struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
 233         .master         = &am33xx_epwmss1_hwmod,
 234         .slave          = &am33xx_ehrpwm1_hwmod,
 235         .clk            = "l4ls_gclk",
 236         .user           = OCP_USER_MPU,
 237 };
 238
 239 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
 240         {
 241                 .pa_start       = 0x48304000,
 242                 .pa_end         = 0x48304000 + SZ_16 - 1,
 243                 .flags          = ADDR_TYPE_RT
 244         },
 245         { }
 246 };
 247
 248 struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
 249         .master         = &am33xx_l4_ls_hwmod,
 250         .slave          = &am33xx_epwmss2_hwmod,
 251         .clk            = "l4ls_gclk",
 252         .addr           = am33xx_epwmss2_addr_space,
 253         .user           = OCP_USER_MPU,
 254 };
 255
 256 struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
 257         .master         = &am33xx_epwmss2_hwmod,
 258         .slave          = &am33xx_ecap2_hwmod,
 259         .clk            = "l4ls_gclk",
 260         .user           = OCP_USER_MPU,
 261 };
 262
 263 struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
 264         .master         = &am33xx_epwmss2_hwmod,
 265         .slave          = &am33xx_eqep2_hwmod,
 266         .clk            = "l4ls_gclk",
 267         .user           = OCP_USER_MPU,
 268 };
 269
 270 struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
 271         .master         = &am33xx_epwmss2_hwmod,
 272         .slave          = &am33xx_ehrpwm2_hwmod,
 273         .clk            = "l4ls_gclk",
 274         .user           = OCP_USER_MPU,
 275 };
 276
 277 /* l3s cfg -> gpmc */
 278 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
 279         {
 280                 .pa_start       = 0x50000000,
 281                 .pa_end         = 0x50000000 + SZ_8K - 1,
 282                 .flags          = ADDR_TYPE_RT,
 283         },
 284         { }
 285 };
 286
 287 struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
 288         .master         = &am33xx_l3_s_hwmod,
 289         .slave          = &am33xx_gpmc_hwmod,
 290         .clk            = "l3s_gclk",
 291         .addr           = am33xx_gpmc_addr_space,
 292         .user           = OCP_USER_MPU,
 293 };
 294
 295 /* i2c2 */
 296 struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
 297         .master         = &am33xx_l4_ls_hwmod,
 298         .slave          = &am33xx_i2c2_hwmod,
 299         .clk            = "l4ls_gclk",
 300         .user           = OCP_USER_MPU,
 301 };
 302
 303 struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
 304         .master         = &am33xx_l4_ls_hwmod,
 305         .slave          = &am33xx_i2c3_hwmod,
 306         .clk            = "l4ls_gclk",
 307         .user           = OCP_USER_MPU,
 308 };
 309
 310 /* l4 ls -> mailbox */
 311 struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
 312         .master         = &am33xx_l4_ls_hwmod,
 313         .slave          = &am33xx_mailbox_hwmod,
 314         .clk            = "l4ls_gclk",
 315         .user           = OCP_USER_MPU,
 316 };
 317
 318 /* l4 ls -> spinlock */
 319 struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
 320         .master         = &am33xx_l4_ls_hwmod,
 321         .slave          = &am33xx_spinlock_hwmod,
 322         .clk            = "l4ls_gclk",
 323         .user           = OCP_USER_MPU,
 324 };
 325
 326 /* l4 ls -> mcasp0 */
 327 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
 328         {
 329                 .pa_start       = 0x48038000,
 330                 .pa_end         = 0x48038000 + SZ_8K - 1,
 331                 .flags          = ADDR_TYPE_RT
 332         },
 333         { }
 334 };
 335
 336 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
 337         .master         = &am33xx_l4_ls_hwmod,
 338         .slave          = &am33xx_mcasp0_hwmod,
 339         .clk            = "l4ls_gclk",
 340         .addr           = am33xx_mcasp0_addr_space,
 341         .user           = OCP_USER_MPU,
 342 };
 343
 344 /* l4 ls -> mcasp1 */
 345 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
 346         {
 347                 .pa_start       = 0x4803C000,
 348                 .pa_end         = 0x4803C000 + SZ_8K - 1,
 349                 .flags          = ADDR_TYPE_RT
 350         },
 351         { }
 352 };
 353
 354 struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
 355         .master         = &am33xx_l4_ls_hwmod,
 356         .slave          = &am33xx_mcasp1_hwmod,
 357         .clk            = "l4ls_gclk",
 358         .addr           = am33xx_mcasp1_addr_space,
 359         .user           = OCP_USER_MPU,
 360 };
 361
 362 /* l4 ls -> mmc0 */
 363 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
 364         {
 365                 .pa_start       = 0x48060100,
 366                 .pa_end         = 0x48060100 + SZ_4K - 1,
 367                 .flags          = ADDR_TYPE_RT,
 368         },
 369         { }
 370 };
 371
 372 struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
 373         .master         = &am33xx_l4_ls_hwmod,
 374         .slave          = &am33xx_mmc0_hwmod,
 375         .clk            = "l4ls_gclk",
 376         .addr           = am33xx_mmc0_addr_space,
 377         .user           = OCP_USER_MPU,
 378 };
 379
 380 /* l4 ls -> mmc1 */
 381 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
 382         {
 383                 .pa_start       = 0x481d8100,
 384                 .pa_end         = 0x481d8100 + SZ_4K - 1,
 385                 .flags          = ADDR_TYPE_RT,
 386         },
 387         { }
 388 };
 389
 390 struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
 391         .master         = &am33xx_l4_ls_hwmod,
 392         .slave          = &am33xx_mmc1_hwmod,
 393         .clk            = "l4ls_gclk",
 394         .addr           = am33xx_mmc1_addr_space,
 395         .user           = OCP_USER_MPU,
 396 };
 397
 398 /* l3 s -> mmc2 */
 399 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
 400         {
 401                 .pa_start       = 0x47810100,
 402                 .pa_end         = 0x47810100 + SZ_64K - 1,
 403                 .flags          = ADDR_TYPE_RT,
 404         },
 405         { }
 406 };
 407
 408 struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
 409         .master         = &am33xx_l3_s_hwmod,
 410         .slave          = &am33xx_mmc2_hwmod,
 411         .clk            = "l3s_gclk",
 412         .addr           = am33xx_mmc2_addr_space,
 413         .user           = OCP_USER_MPU,
 414 };
 415
 416 /* l4 ls -> mcspi0 */
 417 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
 418         .master         = &am33xx_l4_ls_hwmod,
 419         .slave          = &am33xx_spi0_hwmod,
 420         .clk            = "l4ls_gclk",
 421         .user           = OCP_USER_MPU,
 422 };
 423
 424 /* l4 ls -> mcspi1 */
 425 struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
 426         .master         = &am33xx_l4_ls_hwmod,
 427         .slave          = &am33xx_spi1_hwmod,
 428         .clk            = "l4ls_gclk",
 429         .user           = OCP_USER_MPU,
 430 };
 431
 432 /* l4 per -> timer2 */
 433 struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
 434         .master         = &am33xx_l4_ls_hwmod,
 435         .slave          = &am33xx_timer2_hwmod,
 436         .clk            = "l4ls_gclk",
 437         .user           = OCP_USER_MPU,
 438 };
 439
 440 /* l4 per -> timer3 */
 441 struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
 442         .master         = &am33xx_l4_ls_hwmod,
 443         .slave          = &am33xx_timer3_hwmod,
 444         .clk            = "l4ls_gclk",
 445         .user           = OCP_USER_MPU,
 446 };
 447
 448 /* l4 per -> timer4 */
 449 struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
 450         .master         = &am33xx_l4_ls_hwmod,
 451         .slave          = &am33xx_timer4_hwmod,
 452         .clk            = "l4ls_gclk",
 453         .user           = OCP_USER_MPU,
 454 };
 455
 456 /* l4 per -> timer5 */
 457 struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
 458         .master         = &am33xx_l4_ls_hwmod,
 459         .slave          = &am33xx_timer5_hwmod,
 460         .clk            = "l4ls_gclk",
 461         .user           = OCP_USER_MPU,
 462 };
 463
 464 /* l4 per -> timer6 */
 465 struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
 466         .master         = &am33xx_l4_ls_hwmod,
 467         .slave          = &am33xx_timer6_hwmod,
 468         .clk            = "l4ls_gclk",
 469         .user           = OCP_USER_MPU,
 470 };
 471
 472 /* l4 per -> timer7 */
 473 struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
 474         .master         = &am33xx_l4_ls_hwmod,
 475         .slave          = &am33xx_timer7_hwmod,
 476         .clk            = "l4ls_gclk",
 477         .user           = OCP_USER_MPU,
 478 };
 479
 480 /* l3 main -> tpcc */
 481 struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
 482         .master         = &am33xx_l3_main_hwmod,
 483         .slave          = &am33xx_tpcc_hwmod,
 484         .clk            = "l3_gclk",
 485         .user           = OCP_USER_MPU,
 486 };
 487
 488 /* l3 main -> tpcc0 */
 489 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
 490         {
 491                 .pa_start       = 0x49800000,
 492                 .pa_end         = 0x49800000 + SZ_8K - 1,
 493                 .flags          = ADDR_TYPE_RT,
 494         },
 495         { }
 496 };
 497
 498 struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
 499         .master         = &am33xx_l3_main_hwmod,
 500         .slave          = &am33xx_tptc0_hwmod,
 501         .clk            = "l3_gclk",
 502         .addr           = am33xx_tptc0_addr_space,
 503         .user           = OCP_USER_MPU,
 504 };
 505
 506 /* l3 main -> tpcc1 */
 507 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
 508         {
 509                 .pa_start       = 0x49900000,
 510                 .pa_end         = 0x49900000 + SZ_8K - 1,
 511                 .flags          = ADDR_TYPE_RT,
 512         },
 513         { }
 514 };
 515
 516 struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
 517         .master         = &am33xx_l3_main_hwmod,
 518         .slave          = &am33xx_tptc1_hwmod,
 519         .clk            = "l3_gclk",
 520         .addr           = am33xx_tptc1_addr_space,
 521         .user           = OCP_USER_MPU,
 522 };
 523
 524 /* l3 main -> tpcc2 */
 525 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
 526         {
 527                 .pa_start       = 0x49a00000,
 528                 .pa_end         = 0x49a00000 + SZ_8K - 1,
 529                 .flags          = ADDR_TYPE_RT,
 530         },
 531         { }
 532 };
 533
 534 struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
 535         .master         = &am33xx_l3_main_hwmod,
 536         .slave          = &am33xx_tptc2_hwmod,
 537         .clk            = "l3_gclk",
 538         .addr           = am33xx_tptc2_addr_space,
 539         .user           = OCP_USER_MPU,
 540 };
 541
 542 /* l4 ls -> uart2 */
 543 struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
 544         .master         = &am33xx_l4_ls_hwmod,
 545         .slave          = &am33xx_uart2_hwmod,
 546         .clk            = "l4ls_gclk",
 547         .user           = OCP_USER_MPU,
 548 };
 549
 550 /* l4 ls -> uart3 */
 551 struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
 552         .master         = &am33xx_l4_ls_hwmod,
 553         .slave          = &am33xx_uart3_hwmod,
 554         .clk            = "l4ls_gclk",
 555         .user           = OCP_USER_MPU,
 556 };
 557
 558 /* l4 ls -> uart4 */
 559 struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
 560         .master         = &am33xx_l4_ls_hwmod,
 561         .slave          = &am33xx_uart4_hwmod,
 562         .clk            = "l4ls_gclk",
 563         .user           = OCP_USER_MPU,
 564 };
 565
 566 /* l4 ls -> uart5 */
 567 struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
 568         .master         = &am33xx_l4_ls_hwmod,
 569         .slave          = &am33xx_uart5_hwmod,
 570         .clk            = "l4ls_gclk",
 571         .user           = OCP_USER_MPU,
 572 };
 573
 574 /* l4 ls -> uart6 */
 575 struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
 576         .master         = &am33xx_l4_ls_hwmod,
 577         .slave          = &am33xx_uart6_hwmod,
 578         .clk            = "l4ls_gclk",
 579         .user           = OCP_USER_MPU,
 580 };
 581
 582 /* l3 main -> ocmc */
 583 struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
 584         .master         = &am33xx_l3_main_hwmod,
 585         .slave          = &am33xx_ocmcram_hwmod,
 586         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 587 };
 588
 589 /* l3 main -> sha0 HIB2 */
 590 static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
 591         {
 592                 .pa_start       = 0x53100000,
 593                 .pa_end         = 0x53100000 + SZ_512 - 1,
 594                 .flags          = ADDR_TYPE_RT
 595         },
 596         { }
 597 };
 598
 599 struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
 600         .master         = &am33xx_l3_main_hwmod,
 601         .slave          = &am33xx_sha0_hwmod,
 602         .clk            = "sha0_fck",
 603         .addr           = am33xx_sha0_addrs,
 604         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 605 };
 606
 607 /* l3 main -> AES0 HIB2 */
 608 static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
 609         {
 610                 .pa_start       = 0x53500000,
 611                 .pa_end         = 0x53500000 + SZ_1M - 1,
 612                 .flags          = ADDR_TYPE_RT
 613         },
 614         { }
 615 };
 616
 617 struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
 618         .master         = &am33xx_l3_main_hwmod,
 619         .slave          = &am33xx_aes0_hwmod,
 620         .clk            = "aes0_fck",
 621         .addr           = am33xx_aes0_addrs,
 622         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 623 };