arch/arm/mach-rockchip/pm.c

   1 /*
   2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   3  * Author: Tony Xie <tony.xie@rock-chips.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21 #include <linux/regmap.h>
  22 #include <linux/suspend.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regulator/machine.h>
  25
  26 #include <asm/cacheflush.h>
  27 #include <asm/tlbflush.h>
  28 #include <asm/suspend.h>
  29
  30 #include "pm.h"
  31
  32 /* These enum are option of low power mode */
  33 enum {
  34         ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0,
  35         ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,
  36 };
  37
  38 struct rockchip_pm_data {
  39         const struct platform_suspend_ops *ops;
  40         int (*init)(struct device_node *np);
  41 };
  42
  43 static void __iomem *rk3288_bootram_base;
  44 static phys_addr_t rk3288_bootram_phy;
  45
  46 static struct regmap *pmu_regmap;
  47 static struct regmap *sgrf_regmap;
  48
  49 static u32 rk3288_pmu_pwr_mode_con;
  50 static u32 rk3288_sgrf_soc_con0;
  51 static u32 rk3288_sgrf_cpu_con0;
  52
  53 static inline u32 rk3288_l2_config(void)
  54 {
  55         u32 l2ctlr;
  56
  57         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
  58         return l2ctlr;
  59 }
  60
  61 static void rk3288_config_bootdata(void)
  62 {
  63         rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
  64         rkpm_bootdata_cpu_code = virt_to_phys(cpu_resume);
  65
  66         rkpm_bootdata_l2ctlr_f  = 1;
  67         rkpm_bootdata_l2ctlr = rk3288_l2_config();
  68 }
  69
  70 static void rk3288_slp_mode_set(int level)
  71 {
  72         u32 mode_set, mode_set1;
  73
  74         regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);
  75         regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
  76
  77         regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
  78                     &rk3288_pmu_pwr_mode_con);
  79
  80         /*
  81          * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
  82          * PCLK_WDT_GATE - disable WDT during suspend.
  83          */
  84         regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
  85                      SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
  86                      | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
  87
  88         /*
  89          * The dapswjdp can not auto reset before resume, that cause it may
  90          * access some illegal address during resume. Let's disable it before
  91          * suspend, and the MASKROM will enable it back.
  92          */
  93         regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
  94
  95         /* booting address of resuming system is from this register value */
  96         regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
  97                      rk3288_bootram_phy);
  98
  99         regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
 100                      PMU_ARMINT_WAKEUP_EN);
 101
 102         mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
 103                    BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
 104                    BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
 105                    BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
 106                    BIT(PMU_SCU_EN);
 107
 108         mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
 109
 110         if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
 111                 /* arm off, logic deep sleep */
 112                 mode_set |= BIT(PMU_BUS_PD_EN) |
 113                             BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
 114                             BIT(PMU_OSC_24M_DIS) | BIT(PMU_PMU_USE_LF) |
 115                             BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
 116
 117                 mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
 118                              BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
 119         } else {
 120                 /*
 121                  * arm off, logic normal
 122                  * if pmu_clk_core_src_gate_en is not set,
 123                  * wakeup will be error
 124                  */
 125                 mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
 126         }
 127
 128         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
 129         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
 130 }
 131
 132 static void rk3288_slp_mode_set_resume(void)
 133 {
 134         regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0,
 135                      rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE);
 136
 137         regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
 138                      rk3288_pmu_pwr_mode_con);
 139
 140         regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
 141                      rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
 142                      | SGRF_FAST_BOOT_EN_WRITE);
 143 }
 144
 145 static int rockchip_lpmode_enter(unsigned long arg)
 146 {
 147         flush_cache_all();
 148
 149         cpu_do_idle();
 150
 151         pr_err("%s: Failed to suspend\n", __func__);
 152
 153         return 1;
 154 }
 155
 156 static int rk3288_suspend_enter(suspend_state_t state)
 157 {
 158         local_fiq_disable();
 159
 160         rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
 161
 162         cpu_suspend(0, rockchip_lpmode_enter);
 163
 164         rk3288_slp_mode_set_resume();
 165
 166         local_fiq_enable();
 167
 168         return 0;
 169 }
 170
 171 static int rk3288_suspend_prepare(void)
 172 {
 173         return regulator_suspend_prepare(PM_SUSPEND_MEM);
 174 }
 175
 176 static void rk3288_suspend_finish(void)
 177 {
 178         if (regulator_suspend_finish())
 179                 pr_err("%s: Suspend finish failed\n", __func__);
 180 }
 181
 182 static int rk3288_suspend_init(struct device_node *np)
 183 {
 184         struct device_node *sram_np;
 185         struct resource res;
 186         int ret;
 187
 188         pmu_regmap = syscon_node_to_regmap(np);
 189         if (IS_ERR(pmu_regmap)) {
 190                 pr_err("%s: could not find pmu regmap\n", __func__);
 191                 return PTR_ERR(pmu_regmap);
 192         }
 193
 194         sgrf_regmap = syscon_regmap_lookup_by_compatible(
 195                                 "rockchip,rk3288-sgrf");
 196         if (IS_ERR(sgrf_regmap)) {
 197                 pr_err("%s: could not find sgrf regmap\n", __func__);
 198                 return PTR_ERR(pmu_regmap);
 199         }
 200
 201         sram_np = of_find_compatible_node(NULL, NULL,
 202                                           "rockchip,rk3288-pmu-sram");
 203         if (!sram_np) {
 204                 pr_err("%s: could not find bootram dt node\n", __func__);
 205                 return -ENODEV;
 206         }
 207
 208         rk3288_bootram_base = of_iomap(sram_np, 0);
 209         if (!rk3288_bootram_base) {
 210                 pr_err("%s: could not map bootram base\n", __func__);
 211                 return -ENOMEM;
 212         }
 213
 214         ret = of_address_to_resource(sram_np, 0, &res);
 215         if (ret) {
 216                 pr_err("%s: could not get bootram phy addr\n", __func__);
 217                 return ret;
 218         }
 219         rk3288_bootram_phy = res.start;
 220
 221         of_node_put(sram_np);
 222
 223         rk3288_config_bootdata();
 224
 225         /* copy resume code and data to bootsram */
 226         memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
 227                rk3288_bootram_sz);
 228
 229         regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, OSC_STABL_CNT_THRESH);
 230         regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, PMU_STABL_CNT_THRESH);
 231
 232         return 0;
 233 }
 234
 235 static const struct platform_suspend_ops rk3288_suspend_ops = {
 236         .enter   = rk3288_suspend_enter,
 237         .valid   = suspend_valid_only_mem,
 238         .prepare = rk3288_suspend_prepare,
 239         .finish  = rk3288_suspend_finish,
 240 };
 241
 242 static const struct rockchip_pm_data rk3288_pm_data __initconst = {
 243         .ops = &rk3288_suspend_ops,
 244         .init = rk3288_suspend_init,
 245 };
 246
 247 static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = {
 248         {
 249                 .compatible = "rockchip,rk3288-pmu",
 250                 .data = &rk3288_pm_data,
 251         },
 252         { /* sentinel */ },
 253 };
 254
 255 void __init rockchip_suspend_init(void)
 256 {
 257         const struct rockchip_pm_data *pm_data;
 258         const struct of_device_id *match;
 259         struct device_node *np;
 260         int ret;
 261
 262         np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids,
 263                                              &match);
 264         if (!match) {
 265                 pr_err("Failed to find PMU node\n");
 266                 return;
 267         }
 268         pm_data = (struct rockchip_pm_data *) match->data;
 269
 270         if (pm_data->init) {
 271                 ret = pm_data->init(np);
 272
 273                 if (ret) {
 274                         pr_err("%s: matches init error %d\n", __func__, ret);
 275                         return;
 276                 }
 277         }
 278
 279         suspend_set_ops(pm_data->ops);
 280 }