arch/arm64/boot/dts/apm/apm-storm.dtsi

   1 /*
   2  * dts file for AppliedMicro (APM) X-Gene Storm SOC
   3  *
   4  * Copyright (C) 2013, Applied Micro Circuits Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  */
  11
  12 / {
  13         compatible = "apm,xgene-storm";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <2>;
  20                 #size-cells = <0>;
  21
  22                 cpu@000 {
  23                         device_type = "cpu";
  24                         compatible = "apm,potenza", "arm,armv8";
  25                         reg = <0x0 0x000>;
  26                         enable-method = "spin-table";
  27                         cpu-release-addr = <0x1 0x0000fff8>;
  28                 };
  29                 cpu@001 {
  30                         device_type = "cpu";
  31                         compatible = "apm,potenza", "arm,armv8";
  32                         reg = <0x0 0x001>;
  33                         enable-method = "spin-table";
  34                         cpu-release-addr = <0x1 0x0000fff8>;
  35                 };
  36                 cpu@100 {
  37                         device_type = "cpu";
  38                         compatible = "apm,potenza", "arm,armv8";
  39                         reg = <0x0 0x100>;
  40                         enable-method = "spin-table";
  41                         cpu-release-addr = <0x1 0x0000fff8>;
  42                 };
  43                 cpu@101 {
  44                         device_type = "cpu";
  45                         compatible = "apm,potenza", "arm,armv8";
  46                         reg = <0x0 0x101>;
  47                         enable-method = "spin-table";
  48                         cpu-release-addr = <0x1 0x0000fff8>;
  49                 };
  50                 cpu@200 {
  51                         device_type = "cpu";
  52                         compatible = "apm,potenza", "arm,armv8";
  53                         reg = <0x0 0x200>;
  54                         enable-method = "spin-table";
  55                         cpu-release-addr = <0x1 0x0000fff8>;
  56                 };
  57                 cpu@201 {
  58                         device_type = "cpu";
  59                         compatible = "apm,potenza", "arm,armv8";
  60                         reg = <0x0 0x201>;
  61                         enable-method = "spin-table";
  62                         cpu-release-addr = <0x1 0x0000fff8>;
  63                 };
  64                 cpu@300 {
  65                         device_type = "cpu";
  66                         compatible = "apm,potenza", "arm,armv8";
  67                         reg = <0x0 0x300>;
  68                         enable-method = "spin-table";
  69                         cpu-release-addr = <0x1 0x0000fff8>;
  70                 };
  71                 cpu@301 {
  72                         device_type = "cpu";
  73                         compatible = "apm,potenza", "arm,armv8";
  74                         reg = <0x0 0x301>;
  75                         enable-method = "spin-table";
  76                         cpu-release-addr = <0x1 0x0000fff8>;
  77                 };
  78         };
  79
  80         gic: interrupt-controller@78010000 {
  81                 compatible = "arm,cortex-a15-gic";
  82                 #interrupt-cells = <3>;
  83                 interrupt-controller;
  84                 reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
  85                       <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
  86                       <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
  87                       <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
  88                 interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
  89         };
  90
  91         timer {
  92                 compatible = "arm,armv8-timer";
  93                 interrupts = <1 0 0xff01>,      /* Secure Phys IRQ */
  94                              <1 13 0xff01>,     /* Non-secure Phys IRQ */
  95                              <1 14 0xff01>,     /* Virt IRQ */
  96                              <1 15 0xff01>;     /* Hyp IRQ */
  97                 clock-frequency = <50000000>;
  98         };
  99
 100         soc {
 101                 compatible = "simple-bus";
 102                 #address-cells = <2>;
 103                 #size-cells = <2>;
 104                 ranges;
 105                 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
 106
 107                 clocks {
 108                         #address-cells = <2>;
 109                         #size-cells = <2>;
 110                         ranges;
 111                         refclk: refclk {
 112                                 compatible = "fixed-clock";
 113                                 #clock-cells = <1>;
 114                                 clock-frequency = <100000000>;
 115                                 clock-output-names = "refclk";
 116                         };
 117
 118                         pcppll: pcppll@17000100 {
 119                                 compatible = "apm,xgene-pcppll-clock";
 120                                 #clock-cells = <1>;
 121                                 clocks = <&refclk 0>;
 122                                 clock-names = "pcppll";
 123                                 reg = <0x0 0x17000100 0x0 0x1000>;
 124                                 clock-output-names = "pcppll";
 125                                 type = <0>;
 126                         };
 127
 128                         socpll: socpll@17000120 {
 129                                 compatible = "apm,xgene-socpll-clock";
 130                                 #clock-cells = <1>;
 131                                 clocks = <&refclk 0>;
 132                                 clock-names = "socpll";
 133                                 reg = <0x0 0x17000120 0x0 0x1000>;
 134                                 clock-output-names = "socpll";
 135                                 type = <1>;
 136                         };
 137
 138                         socplldiv2: socplldiv2  {
 139                                 compatible = "fixed-factor-clock";
 140                                 #clock-cells = <1>;
 141                                 clocks = <&socpll 0>;
 142                                 clock-names = "socplldiv2";
 143                                 clock-mult = <1>;
 144                                 clock-div = <2>;
 145                                 clock-output-names = "socplldiv2";
 146                         };
 147
 148                         qmlclk: qmlclk {
 149                                 compatible = "apm,xgene-device-clock";
 150                                 #clock-cells = <1>;
 151                                 clocks = <&socplldiv2 0>;
 152                                 clock-names = "qmlclk";
 153                                 reg = <0x0 0x1703C000 0x0 0x1000>;
 154                                 reg-names = "csr-reg";
 155                                 clock-output-names = "qmlclk";
 156                         };
 157
 158                         ethclk: ethclk {
 159                                 compatible = "apm,xgene-device-clock";
 160                                 #clock-cells = <1>;
 161                                 clocks = <&socplldiv2 0>;
 162                                 clock-names = "ethclk";
 163                                 reg = <0x0 0x17000000 0x0 0x1000>;
 164                                 reg-names = "div-reg";
 165                                 divider-offset = <0x238>;
 166                                 divider-width = <0x9>;
 167                                 divider-shift = <0x0>;
 168                                 clock-output-names = "ethclk";
 169                         };
 170
 171                         menetclk: menetclk {
 172                                 compatible = "apm,xgene-device-clock";
 173                                 #clock-cells = <1>;
 174                                 clocks = <&ethclk 0>;
 175                                 reg = <0x0 0x1702C000 0x0 0x1000>;
 176                                 reg-names = "csr-reg";
 177                                 clock-output-names = "menetclk";
 178                         };
 179
 180                         sge0clk: sge0clk@1f21c000 {
 181                                 compatible = "apm,xgene-device-clock";
 182                                 #clock-cells = <1>;
 183                                 clocks = <&socplldiv2 0>;
 184                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 185                                 reg-names = "csr-reg";
 186                                 csr-mask = <0x3>;
 187                                 clock-output-names = "sge0clk";
 188                         };
 189
 190                         sge1clk: sge1clk@1f21c000 {
 191                                 compatible = "apm,xgene-device-clock";
 192                                 #clock-cells = <1>;
 193                                 clocks = <&socplldiv2 0>;
 194                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 195                                 reg-names = "csr-reg";
 196                                 csr-mask = <0xc>;
 197                                 clock-output-names = "sge1clk";
 198                         };
 199
 200                         xge0clk: xge0clk@1f61c000 {
 201                                 compatible = "apm,xgene-device-clock";
 202                                 #clock-cells = <1>;
 203                                 clocks = <&socplldiv2 0>;
 204                                 reg = <0x0 0x1f61c000 0x0 0x1000>;
 205                                 reg-names = "csr-reg";
 206                                 csr-mask = <0x3>;
 207                                 clock-output-names = "xge0clk";
 208                         };
 209
 210                         xge1clk: xge1clk@1f62c000 {
 211                                 compatible = "apm,xgene-device-clock";
 212                                 status = "disabled";
 213                                 #clock-cells = <1>;
 214                                 clocks = <&socplldiv2 0>;
 215                                 reg = <0x0 0x1f62c000 0x0 0x1000>;
 216                                 reg-names = "csr-reg";
 217                                 csr-mask = <0x3>;
 218                                 clock-output-names = "xge1clk";
 219                         };
 220
 221                         sataphy1clk: sataphy1clk@1f21c000 {
 222                                 compatible = "apm,xgene-device-clock";
 223                                 #clock-cells = <1>;
 224                                 clocks = <&socplldiv2 0>;
 225                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 226                                 reg-names = "csr-reg";
 227                                 clock-output-names = "sataphy1clk";
 228                                 status = "disabled";
 229                                 csr-offset = <0x4>;
 230                                 csr-mask = <0x00>;
 231                                 enable-offset = <0x0>;
 232                                 enable-mask = <0x06>;
 233                         };
 234
 235                         sataphy2clk: sataphy1clk@1f22c000 {
 236                                 compatible = "apm,xgene-device-clock";
 237                                 #clock-cells = <1>;
 238                                 clocks = <&socplldiv2 0>;
 239                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 240                                 reg-names = "csr-reg";
 241                                 clock-output-names = "sataphy2clk";
 242                                 status = "ok";
 243                                 csr-offset = <0x4>;
 244                                 csr-mask = <0x3a>;
 245                                 enable-offset = <0x0>;
 246                                 enable-mask = <0x06>;
 247                         };
 248
 249                         sataphy3clk: sataphy1clk@1f23c000 {
 250                                 compatible = "apm,xgene-device-clock";
 251                                 #clock-cells = <1>;
 252                                 clocks = <&socplldiv2 0>;
 253                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 254                                 reg-names = "csr-reg";
 255                                 clock-output-names = "sataphy3clk";
 256                                 status = "ok";
 257                                 csr-offset = <0x4>;
 258                                 csr-mask = <0x3a>;
 259                                 enable-offset = <0x0>;
 260                                 enable-mask = <0x06>;
 261                         };
 262
 263                         sata01clk: sata01clk@1f21c000 {
 264                                 compatible = "apm,xgene-device-clock";
 265                                 #clock-cells = <1>;
 266                                 clocks = <&socplldiv2 0>;
 267                                 reg = <0x0 0x1f21c000 0x0 0x1000>;
 268                                 reg-names = "csr-reg";
 269                                 clock-output-names = "sata01clk";
 270                                 csr-offset = <0x4>;
 271                                 csr-mask = <0x05>;
 272                                 enable-offset = <0x0>;
 273                                 enable-mask = <0x39>;
 274                         };
 275
 276                         sata23clk: sata23clk@1f22c000 {
 277                                 compatible = "apm,xgene-device-clock";
 278                                 #clock-cells = <1>;
 279                                 clocks = <&socplldiv2 0>;
 280                                 reg = <0x0 0x1f22c000 0x0 0x1000>;
 281                                 reg-names = "csr-reg";
 282                                 clock-output-names = "sata23clk";
 283                                 csr-offset = <0x4>;
 284                                 csr-mask = <0x05>;
 285                                 enable-offset = <0x0>;
 286                                 enable-mask = <0x39>;
 287                         };
 288
 289                         sata45clk: sata45clk@1f23c000 {
 290                                 compatible = "apm,xgene-device-clock";
 291                                 #clock-cells = <1>;
 292                                 clocks = <&socplldiv2 0>;
 293                                 reg = <0x0 0x1f23c000 0x0 0x1000>;
 294                                 reg-names = "csr-reg";
 295                                 clock-output-names = "sata45clk";
 296                                 csr-offset = <0x4>;
 297                                 csr-mask = <0x05>;
 298                                 enable-offset = <0x0>;
 299                                 enable-mask = <0x39>;
 300                         };
 301
 302                         rtcclk: rtcclk@17000000 {
 303                                 compatible = "apm,xgene-device-clock";
 304                                 #clock-cells = <1>;
 305                                 clocks = <&socplldiv2 0>;
 306                                 reg = <0x0 0x17000000 0x0 0x2000>;
 307                                 reg-names = "csr-reg";
 308                                 csr-offset = <0xc>;
 309                                 csr-mask = <0x2>;
 310                                 enable-offset = <0x10>;
 311                                 enable-mask = <0x2>;
 312                                 clock-output-names = "rtcclk";
 313                         };
 314
 315                         rngpkaclk: rngpkaclk@17000000 {
 316                                 compatible = "apm,xgene-device-clock";
 317                                 #clock-cells = <1>;
 318                                 clocks = <&socplldiv2 0>;
 319                                 reg = <0x0 0x17000000 0x0 0x2000>;
 320                                 reg-names = "csr-reg";
 321                                 csr-offset = <0xc>;
 322                                 csr-mask = <0x10>;
 323                                 enable-offset = <0x10>;
 324                                 enable-mask = <0x10>;
 325                                 clock-output-names = "rngpkaclk";
 326                         };
 327
 328                         pcie0clk: pcie0clk@1f2bc000 {
 329                                 status = "disabled";
 330                                 compatible = "apm,xgene-device-clock";
 331                                 #clock-cells = <1>;
 332                                 clocks = <&socplldiv2 0>;
 333                                 reg = <0x0 0x1f2bc000 0x0 0x1000>;
 334                                 reg-names = "csr-reg";
 335                                 clock-output-names = "pcie0clk";
 336                         };
 337
 338                         pcie1clk: pcie1clk@1f2cc000 {
 339                                 status = "disabled";
 340                                 compatible = "apm,xgene-device-clock";
 341                                 #clock-cells = <1>;
 342                                 clocks = <&socplldiv2 0>;
 343                                 reg = <0x0 0x1f2cc000 0x0 0x1000>;
 344                                 reg-names = "csr-reg";
 345                                 clock-output-names = "pcie1clk";
 346                         };
 347
 348                         pcie2clk: pcie2clk@1f2dc000 {
 349                                 status = "disabled";
 350                                 compatible = "apm,xgene-device-clock";
 351                                 #clock-cells = <1>;
 352                                 clocks = <&socplldiv2 0>;
 353                                 reg = <0x0 0x1f2dc000 0x0 0x1000>;
 354                                 reg-names = "csr-reg";
 355                                 clock-output-names = "pcie2clk";
 356                         };
 357
 358                         pcie3clk: pcie3clk@1f50c000 {
 359                                 status = "disabled";
 360                                 compatible = "apm,xgene-device-clock";
 361                                 #clock-cells = <1>;
 362                                 clocks = <&socplldiv2 0>;
 363                                 reg = <0x0 0x1f50c000 0x0 0x1000>;
 364                                 reg-names = "csr-reg";
 365                                 clock-output-names = "pcie3clk";
 366                         };
 367
 368                         pcie4clk: pcie4clk@1f51c000 {
 369                                 status = "disabled";
 370                                 compatible = "apm,xgene-device-clock";
 371                                 #clock-cells = <1>;
 372                                 clocks = <&socplldiv2 0>;
 373                                 reg = <0x0 0x1f51c000 0x0 0x1000>;
 374                                 reg-names = "csr-reg";
 375                                 clock-output-names = "pcie4clk";
 376                         };
 377
 378                         dmaclk: dmaclk@1f27c000 {
 379                                 compatible = "apm,xgene-device-clock";
 380                                 #clock-cells = <1>;
 381                                 clocks = <&socplldiv2 0>;
 382                                 reg = <0x0 0x1f27c000 0x0 0x1000>;
 383                                 reg-names = "csr-reg";
 384                                 clock-output-names = "dmaclk";
 385                         };
 386                 };
 387
 388                 msi: msi@79000000 {
 389                         compatible = "apm,xgene1-msi";
 390                         msi-controller;
 391                         reg = <0x00 0x79000000 0x0 0x900000>;
 392                         interrupts = <  0x0 0x10 0x4
 393                                         0x0 0x11 0x4
 394                                         0x0 0x12 0x4
 395                                         0x0 0x13 0x4
 396                                         0x0 0x14 0x4
 397                                         0x0 0x15 0x4
 398                                         0x0 0x16 0x4
 399                                         0x0 0x17 0x4
 400                                         0x0 0x18 0x4
 401                                         0x0 0x19 0x4
 402                                         0x0 0x1a 0x4
 403                                         0x0 0x1b 0x4
 404                                         0x0 0x1c 0x4
 405                                         0x0 0x1d 0x4
 406                                         0x0 0x1e 0x4
 407                                         0x0 0x1f 0x4>;
 408                 };
 409
 410                 csw: csw@7e200000 {
 411                         compatible = "apm,xgene-csw", "syscon";
 412                         reg = <0x0 0x7e200000 0x0 0x1000>;
 413                 };
 414
 415                 mcba: mcba@7e700000 {
 416                         compatible = "apm,xgene-mcb", "syscon";
 417                         reg = <0x0 0x7e700000 0x0 0x1000>;
 418                 };
 419
 420                 mcbb: mcbb@7e720000 {
 421                         compatible = "apm,xgene-mcb", "syscon";
 422                         reg = <0x0 0x7e720000 0x0 0x1000>;
 423                 };
 424
 425                 efuse: efuse@1054a000 {
 426                         compatible = "apm,xgene-efuse", "syscon";
 427                         reg = <0x0 0x1054a000 0x0 0x20>;
 428                 };
 429
 430                 edac@78800000 {
 431                         compatible = "apm,xgene-edac";
 432                         #address-cells = <2>;
 433                         #size-cells = <2>;
 434                         ranges;
 435                         regmap-csw = <&csw>;
 436                         regmap-mcba = <&mcba>;
 437                         regmap-mcbb = <&mcbb>;
 438                         regmap-efuse = <&efuse>;
 439                         reg = <0x0 0x78800000 0x0 0x100>;
 440                         interrupts = <0x0 0x20 0x4>,
 441                                      <0x0 0x21 0x4>,
 442                                      <0x0 0x27 0x4>;
 443
 444                         edacmc@7e800000 {
 445                                 compatible = "apm,xgene-edac-mc";
 446                                 reg = <0x0 0x7e800000 0x0 0x1000>;
 447                                 memory-controller = <0>;
 448                         };
 449
 450                         edacmc@7e840000 {
 451                                 compatible = "apm,xgene-edac-mc";
 452                                 reg = <0x0 0x7e840000 0x0 0x1000>;
 453                                 memory-controller = <1>;
 454                         };
 455
 456                         edacmc@7e880000 {
 457                                 compatible = "apm,xgene-edac-mc";
 458                                 reg = <0x0 0x7e880000 0x0 0x1000>;
 459                                 memory-controller = <2>;
 460                         };
 461
 462                         edacmc@7e8c0000 {
 463                                 compatible = "apm,xgene-edac-mc";
 464                                 reg = <0x0 0x7e8c0000 0x0 0x1000>;
 465                                 memory-controller = <3>;
 466                         };
 467
 468                         edacpmd@7c000000 {
 469                                 compatible = "apm,xgene-edac-pmd";
 470                                 reg = <0x0 0x7c000000 0x0 0x200000>;
 471                                 pmd-controller = <0>;
 472                         };
 473
 474                         edacpmd@7c200000 {
 475                                 compatible = "apm,xgene-edac-pmd";
 476                                 reg = <0x0 0x7c200000 0x0 0x200000>;
 477                                 pmd-controller = <1>;
 478                         };
 479
 480                         edacpmd@7c400000 {
 481                                 compatible = "apm,xgene-edac-pmd";
 482                                 reg = <0x0 0x7c400000 0x0 0x200000>;
 483                                 pmd-controller = <2>;
 484                         };
 485
 486                         edacpmd@7c600000 {
 487                                 compatible = "apm,xgene-edac-pmd";
 488                                 reg = <0x0 0x7c600000 0x0 0x200000>;
 489                                 pmd-controller = <3>;
 490                         };
 491
 492                         edacl3@7e600000 {
 493                                 compatible = "apm,xgene-edac-l3";
 494                                 reg = <0x0 0x7e600000 0x0 0x1000>;
 495                         };
 496
 497                         edacsoc@7e930000 {
 498                                 compatible = "apm,xgene-edac-soc-v1";
 499                                 reg = <0x0 0x7e930000 0x0 0x1000>;
 500                         };
 501                 };
 502
 503                 pcie0: pcie@1f2b0000 {
 504                         status = "disabled";
 505                         device_type = "pci";
 506                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 507                         #interrupt-cells = <1>;
 508                         #size-cells = <2>;
 509                         #address-cells = <3>;
 510                         reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
 511                                 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 512                         reg-names = "csr", "cfg";
 513                         ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
 514                                   0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
 515                                   0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
 516                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 517                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 518                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 519                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
 520                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
 521                                          0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
 522                                          0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
 523                         dma-coherent;
 524                         clocks = <&pcie0clk 0>;
 525                         msi-parent = <&msi>;
 526                 };
 527
 528                 pcie1: pcie@1f2c0000 {
 529                         status = "disabled";
 530                         device_type = "pci";
 531                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 532                         #interrupt-cells = <1>;
 533                         #size-cells = <2>;
 534                         #address-cells = <3>;
 535                         reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
 536                                 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 537                         reg-names = "csr", "cfg";
 538                         ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
 539                                   0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
 540                                   0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
 541                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 542                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 543                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 544                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
 545                                          0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
 546                                          0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
 547                                          0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
 548                         dma-coherent;
 549                         clocks = <&pcie1clk 0>;
 550                         msi-parent = <&msi>;
 551                 };
 552
 553                 pcie2: pcie@1f2d0000 {
 554                         status = "disabled";
 555                         device_type = "pci";
 556                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 557                         #interrupt-cells = <1>;
 558                         #size-cells = <2>;
 559                         #address-cells = <3>;
 560                         reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
 561                                  0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
 562                         reg-names = "csr", "cfg";
 563                         ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
 564                                   0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
 565                                   0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
 566                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 567                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 568                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 569                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
 570                                          0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
 571                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
 572                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
 573                         dma-coherent;
 574                         clocks = <&pcie2clk 0>;
 575                         msi-parent = <&msi>;
 576                 };
 577
 578                 pcie3: pcie@1f500000 {
 579                         status = "disabled";
 580                         device_type = "pci";
 581                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 582                         #interrupt-cells = <1>;
 583                         #size-cells = <2>;
 584                         #address-cells = <3>;
 585                         reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
 586                                 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
 587                         reg-names = "csr", "cfg";
 588                         ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
 589                                   0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
 590                                   0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
 591                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 592                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 593                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 594                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
 595                                          0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
 596                                          0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
 597                                          0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
 598                         dma-coherent;
 599                         clocks = <&pcie3clk 0>;
 600                         msi-parent = <&msi>;
 601                 };
 602
 603                 pcie4: pcie@1f510000 {
 604                         status = "disabled";
 605                         device_type = "pci";
 606                         compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
 607                         #interrupt-cells = <1>;
 608                         #size-cells = <2>;
 609                         #address-cells = <3>;
 610                         reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
 611                                 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
 612                         reg-names = "csr", "cfg";
 613                         ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
 614                                   0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
 615                                   0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
 616                         dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
 617                                       0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
 618                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 619                         interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
 620                                          0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
 621                                          0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
 622                                          0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
 623                         dma-coherent;
 624                         clocks = <&pcie4clk 0>;
 625                         msi-parent = <&msi>;
 626                 };
 627
 628                 serial0: serial@1c020000 {
 629                         status = "disabled";
 630                         device_type = "serial";
 631                         compatible = "ns16550a";
 632                         reg = <0 0x1c020000 0x0 0x1000>;
 633                         reg-shift = <2>;
 634                         clock-frequency = <10000000>; /* Updated by bootloader */
 635                         interrupt-parent = <&gic>;
 636                         interrupts = <0x0 0x4c 0x4>;
 637                 };
 638
 639                 serial1: serial@1c021000 {
 640                         status = "disabled";
 641                         device_type = "serial";
 642                         compatible = "ns16550a";
 643                         reg = <0 0x1c021000 0x0 0x1000>;
 644                         reg-shift = <2>;
 645                         clock-frequency = <10000000>; /* Updated by bootloader */
 646                         interrupt-parent = <&gic>;
 647                         interrupts = <0x0 0x4d 0x4>;
 648                 };
 649
 650                 serial2: serial@1c022000 {
 651                         status = "disabled";
 652                         device_type = "serial";
 653                         compatible = "ns16550a";
 654                         reg = <0 0x1c022000 0x0 0x1000>;
 655                         reg-shift = <2>;
 656                         clock-frequency = <10000000>; /* Updated by bootloader */
 657                         interrupt-parent = <&gic>;
 658                         interrupts = <0x0 0x4e 0x4>;
 659                 };
 660
 661                 serial3: serial@1c023000 {
 662                         status = "disabled";
 663                         device_type = "serial";
 664                         compatible = "ns16550a";
 665                         reg = <0 0x1c023000 0x0 0x1000>;
 666                         reg-shift = <2>;
 667                         clock-frequency = <10000000>; /* Updated by bootloader */
 668                         interrupt-parent = <&gic>;
 669                         interrupts = <0x0 0x4f 0x4>;
 670                 };
 671
 672                 phy1: phy@1f21a000 {
 673                         compatible = "apm,xgene-phy";
 674                         reg = <0x0 0x1f21a000 0x0 0x100>;
 675                         #phy-cells = <1>;
 676                         clocks = <&sataphy1clk 0>;
 677                         status = "disabled";
 678                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 679                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 680                 };
 681
 682                 phy2: phy@1f22a000 {
 683                         compatible = "apm,xgene-phy";
 684                         reg = <0x0 0x1f22a000 0x0 0x100>;
 685                         #phy-cells = <1>;
 686                         clocks = <&sataphy2clk 0>;
 687                         status = "ok";
 688                         apm,tx-boost-gain = <30 30 30 30 30 30>;
 689                         apm,tx-eye-tuning = <1 10 10 2 10 10>;
 690                 };
 691
 692                 phy3: phy@1f23a000 {
 693                         compatible = "apm,xgene-phy";
 694                         reg = <0x0 0x1f23a000 0x0 0x100>;
 695                         #phy-cells = <1>;
 696                         clocks = <&sataphy3clk 0>;
 697                         status = "ok";
 698                         apm,tx-boost-gain = <31 31 31 31 31 31>;
 699                         apm,tx-eye-tuning = <2 10 10 2 10 10>;
 700                 };
 701
 702                 sata1: sata@1a000000 {
 703                         compatible = "apm,xgene-ahci";
 704                         reg = <0x0 0x1a000000 0x0 0x1000>,
 705                               <0x0 0x1f210000 0x0 0x1000>,
 706                               <0x0 0x1f21d000 0x0 0x1000>,
 707                               <0x0 0x1f21e000 0x0 0x1000>,
 708                               <0x0 0x1f217000 0x0 0x1000>;
 709                         interrupts = <0x0 0x86 0x4>;
 710                         dma-coherent;
 711                         status = "disabled";
 712                         clocks = <&sata01clk 0>;
 713                         phys = <&phy1 0>;
 714                         phy-names = "sata-phy";
 715                 };
 716
 717                 sata2: sata@1a400000 {
 718                         compatible = "apm,xgene-ahci";
 719                         reg = <0x0 0x1a400000 0x0 0x1000>,
 720                               <0x0 0x1f220000 0x0 0x1000>,
 721                               <0x0 0x1f22d000 0x0 0x1000>,
 722                               <0x0 0x1f22e000 0x0 0x1000>,
 723                               <0x0 0x1f227000 0x0 0x1000>;
 724                         interrupts = <0x0 0x87 0x4>;
 725                         dma-coherent;
 726                         status = "ok";
 727                         clocks = <&sata23clk 0>;
 728                         phys = <&phy2 0>;
 729                         phy-names = "sata-phy";
 730                 };
 731
 732                 sata3: sata@1a800000 {
 733                         compatible = "apm,xgene-ahci";
 734                         reg = <0x0 0x1a800000 0x0 0x1000>,
 735                               <0x0 0x1f230000 0x0 0x1000>,
 736                               <0x0 0x1f23d000 0x0 0x1000>,
 737                               <0x0 0x1f23e000 0x0 0x1000>;
 738                         interrupts = <0x0 0x88 0x4>;
 739                         dma-coherent;
 740                         status = "ok";
 741                         clocks = <&sata45clk 0>;
 742                         phys = <&phy3 0>;
 743                         phy-names = "sata-phy";
 744                 };
 745
 746                 sbgpio: sbgpio@17001000{
 747                         compatible = "apm,xgene-gpio-sb";
 748                         reg = <0x0 0x17001000 0x0 0x400>;
 749                         #gpio-cells = <2>;
 750                         gpio-controller;
 751                         interrupts =    <0x0 0x28 0x1>,
 752                                         <0x0 0x29 0x1>,
 753                                         <0x0 0x2a 0x1>,
 754                                         <0x0 0x2b 0x1>,
 755                                         <0x0 0x2c 0x1>,
 756                                         <0x0 0x2d 0x1>;
 757                 };
 758
 759                 rtc: rtc@10510000 {
 760                         compatible = "apm,xgene-rtc";
 761                         reg = <0x0 0x10510000 0x0 0x400>;
 762                         interrupts = <0x0 0x46 0x4>;
 763                         #clock-cells = <1>;
 764                         clocks = <&rtcclk 0>;
 765                 };
 766
 767                 menet: ethernet@17020000 {
 768                         compatible = "apm,xgene-enet";
 769                         status = "disabled";
 770                         reg = <0x0 0x17020000 0x0 0xd100>,
 771                               <0x0 0X17030000 0x0 0Xc300>,
 772                               <0x0 0X10000000 0x0 0X200>;
 773                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 774                         interrupts = <0x0 0x3c 0x4>;
 775                         dma-coherent;
 776                         clocks = <&menetclk 0>;
 777                         /* mac address will be overwritten by the bootloader */
 778                         local-mac-address = [00 00 00 00 00 00];
 779                         phy-connection-type = "rgmii";
 780                         phy-handle = <&menetphy>;
 781                         mdio {
 782                                 compatible = "apm,xgene-mdio";
 783                                 #address-cells = <1>;
 784                                 #size-cells = <0>;
 785                                 menetphy: menetphy@3 {
 786                                         compatible = "ethernet-phy-id001c.c915";
 787                                         reg = <0x3>;
 788                                 };
 789
 790                         };
 791                 };
 792
 793                 sgenet0: ethernet@1f210000 {
 794                         compatible = "apm,xgene1-sgenet";
 795                         status = "disabled";
 796                         reg = <0x0 0x1f210000 0x0 0xd100>,
 797                               <0x0 0x1f200000 0x0 0Xc300>,
 798                               <0x0 0x1B000000 0x0 0X200>;
 799                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 800                         interrupts = <0x0 0xA0 0x4>,
 801                                      <0x0 0xA1 0x4>;
 802                         dma-coherent;
 803                         clocks = <&sge0clk 0>;
 804                         local-mac-address = [00 00 00 00 00 00];
 805                         phy-connection-type = "sgmii";
 806                 };
 807
 808                 sgenet1: ethernet@1f210030 {
 809                         compatible = "apm,xgene1-sgenet";
 810                         status = "disabled";
 811                         reg = <0x0 0x1f210030 0x0 0xd100>,
 812                               <0x0 0x1f200000 0x0 0Xc300>,
 813                               <0x0 0x1B000000 0x0 0X8000>;
 814                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 815                         interrupts = <0x0 0xAC 0x4>,
 816                                      <0x0 0xAD 0x4>;
 817                         port-id = <1>;
 818                         dma-coherent;
 819                         clocks = <&sge1clk 0>;
 820                         local-mac-address = [00 00 00 00 00 00];
 821                         phy-connection-type = "sgmii";
 822                 };
 823
 824                 xgenet: ethernet@1f610000 {
 825                         compatible = "apm,xgene1-xgenet";
 826                         status = "disabled";
 827                         reg = <0x0 0x1f610000 0x0 0xd100>,
 828                               <0x0 0x1f600000 0x0 0Xc300>,
 829                               <0x0 0x18000000 0x0 0X200>;
 830                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 831                         interrupts = <0x0 0x60 0x4>,
 832                                      <0x0 0x61 0x4>;
 833                         dma-coherent;
 834                         clocks = <&xge0clk 0>;
 835                         /* mac address will be overwritten by the bootloader */
 836                         local-mac-address = [00 00 00 00 00 00];
 837                         phy-connection-type = "xgmii";
 838                 };
 839
 840                 xgenet1: ethernet@1f620000 {
 841                         compatible = "apm,xgene1-xgenet";
 842                         status = "disabled";
 843                         reg = <0x0 0x1f620000 0x0 0xd100>,
 844                               <0x0 0x1f600000 0x0 0Xc300>,
 845                               <0x0 0x18000000 0x0 0X8000>;
 846                         reg-names = "enet_csr", "ring_csr", "ring_cmd";
 847                         interrupts = <0x0 0x6C 0x4>,
 848                                      <0x0 0x6D 0x4>;
 849                         port-id = <1>;
 850                         dma-coherent;
 851                         clocks = <&xge1clk 0>;
 852                         /* mac address will be overwritten by the bootloader */
 853                         local-mac-address = [00 00 00 00 00 00];
 854                         phy-connection-type = "xgmii";
 855                 };
 856
 857                 rng: rng@10520000 {
 858                         compatible = "apm,xgene-rng";
 859                         reg = <0x0 0x10520000 0x0 0x100>;
 860                         interrupts = <0x0 0x41 0x4>;
 861                         clocks = <&rngpkaclk 0>;
 862                 };
 863
 864                 dma: dma@1f270000 {
 865                         compatible = "apm,xgene-storm-dma";
 866                         device_type = "dma";
 867                         reg = <0x0 0x1f270000 0x0 0x10000>,
 868                               <0x0 0x1f200000 0x0 0x10000>,
 869                               <0x0 0x1b000000 0x0 0x400000>,
 870                               <0x0 0x1054a000 0x0 0x100>;
 871                         interrupts = <0x0 0x82 0x4>,
 872                                      <0x0 0xb8 0x4>,
 873                                      <0x0 0xb9 0x4>,
 874                                      <0x0 0xba 0x4>,
 875                                      <0x0 0xbb 0x4>;
 876                         dma-coherent;
 877                         clocks = <&dmaclk 0>;
 878                 };
 879         };
 880 };