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1 /*
2  * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 #ifndef __ASM_CPUFEATURE_H
10 #define __ASM_CPUFEATURE_H
11
12 #include <asm/hwcap.h>
13 #include <asm/sysreg.h>
14
15 /*
16  * In the arm64 world (as in the ARM world), elf_hwcap is used both internally
17  * in the kernel and for user space to keep track of which optional features
18  * are supported by the current system. So let's map feature 'x' to HWCAP_x.
19  * Note that HWCAP_x constants are bit fields so we need to take the log.
20  */
21
22 #define MAX_CPU_FEATURES        (8 * sizeof(elf_hwcap))
23 #define cpu_feature(x)          ilog2(HWCAP_ ## x)
24
25 #define ARM64_WORKAROUND_CLEAN_CACHE            0
26 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE    1
27 #define ARM64_WORKAROUND_845719                 2
28 #define ARM64_HAS_SYSREG_GIC_CPUIF              3
29 #define ARM64_HAS_PAN                           4
30 #define ARM64_HAS_LSE_ATOMICS                   5
31 #define ARM64_WORKAROUND_CAVIUM_23154           6
32
33 #define ARM64_NCAPS                             7
34
35 #ifndef __ASSEMBLY__
36
37 #include <linux/kernel.h>
38
39 /* CPU feature register tracking */
40 enum ftr_type {
41         FTR_EXACT,      /* Use a predefined safe value */
42         FTR_LOWER_SAFE, /* Smaller value is safe */
43         FTR_HIGHER_SAFE,/* Bigger value is safe */
44 };
45
46 #define FTR_STRICT      true    /* SANITY check strict matching required */
47 #define FTR_NONSTRICT   false   /* SANITY check ignored */
48
49 struct arm64_ftr_bits {
50         bool            strict;   /* CPU Sanity check: strict matching required ? */
51         enum ftr_type   type;
52         u8              shift;
53         u8              width;
54         s64             safe_val; /* safe value for discrete features */
55 };
56
57 /*
58  * @arm64_ftr_reg - Feature register
59  * @strict_mask         Bits which should match across all CPUs for sanity.
60  * @sys_val             Safe value across the CPUs (system view)
61  */
62 struct arm64_ftr_reg {
63         u32                     sys_id;
64         const char              *name;
65         u64                     strict_mask;
66         u64                     sys_val;
67         struct arm64_ftr_bits   *ftr_bits;
68 };
69
70 struct arm64_cpu_capabilities {
71         const char *desc;
72         u16 capability;
73         bool (*matches)(const struct arm64_cpu_capabilities *);
74         void (*enable)(void *);         /* Called on all active CPUs */
75         union {
76                 struct {        /* To be used for erratum handling only */
77                         u32 midr_model;
78                         u32 midr_range_min, midr_range_max;
79                 };
80
81                 struct {        /* Feature register checking */
82                         u32 sys_reg;
83                         int field_pos;
84                         int min_field_value;
85                         int hwcap_type;
86                         unsigned long hwcap;
87                 };
88         };
89 };
90
91 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
92
93 static inline bool cpu_have_feature(unsigned int num)
94 {
95         return elf_hwcap & (1UL << num);
96 }
97
98 static inline bool cpus_have_cap(unsigned int num)
99 {
100         if (num >= ARM64_NCAPS)
101                 return false;
102         return test_bit(num, cpu_hwcaps);
103 }
104
105 static inline void cpus_set_cap(unsigned int num)
106 {
107         if (num >= ARM64_NCAPS)
108                 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
109                         num, ARM64_NCAPS);
110         else
111                 __set_bit(num, cpu_hwcaps);
112 }
113
114 static inline int __attribute_const__
115 cpuid_feature_extract_field_width(u64 features, int field, int width)
116 {
117         return (s64)(features << (64 - width - field)) >> (64 - width);
118 }
119
120 static inline int __attribute_const__
121 cpuid_feature_extract_field(u64 features, int field)
122 {
123         return cpuid_feature_extract_field_width(features, field, 4);
124 }
125
126 static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp)
127 {
128         return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
129 }
130
131 static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)
132 {
133         return cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width);
134 }
135
136 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
137 {
138         return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
139                 cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
140 }
141
142 void __init setup_cpu_features(void);
143
144 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
145                             const char *info);
146 void check_local_cpu_errata(void);
147
148 #ifdef CONFIG_HOTPLUG_CPU
149 void verify_local_cpu_capabilities(void);
150 #else
151 static inline void verify_local_cpu_capabilities(void)
152 {
153 }
154 #endif
155
156 u64 read_system_reg(u32 id);
157
158 static inline bool cpu_supports_mixed_endian_el0(void)
159 {
160         return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
161 }
162
163 static inline bool system_supports_mixed_endian_el0(void)
164 {
165         return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
166 }
167
168 #endif /* __ASSEMBLY__ */
169
170 #endif