2 * Blackfin architecture-dependent process handling
4 * Copyright 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later
9 #include <linux/module.h>
10 #include <linux/unistd.h>
11 #include <linux/user.h>
12 #include <linux/uaccess.h>
13 #include <linux/slab.h>
14 #include <linux/sched.h>
15 #include <linux/tick.h>
17 #include <linux/err.h>
19 #include <asm/blackfin.h>
20 #include <asm/fixed_code.h>
21 #include <asm/mem_map.h>
24 asmlinkage void ret_from_fork(void);
26 /* Points to the SDRAM backup memory for the stack that is currently in
27 * L1 scratchpad memory.
29 void *current_l1_stack_save;
31 /* The number of tasks currently using a L1 stack area. The SRAM is
32 * allocated/deallocated whenever this changes from/to zero.
36 /* Start and length of the area in L1 scratchpad memory which we've allocated
40 unsigned long l1_stack_len;
42 void (*pm_power_off)(void) = NULL;
43 EXPORT_SYMBOL(pm_power_off);
46 * The idle loop on BFIN
49 static void default_idle(void)__attribute__((l1_text));
50 void cpu_idle(void)__attribute__((l1_text));
54 * This is our default idle handler. We need to disable
55 * interrupts here to ensure we don't miss a wakeup call.
57 static void default_idle(void)
60 ipipe_suspend_domain();
62 hard_local_irq_disable();
64 idle_with_irq_disabled();
66 hard_local_irq_enable();
70 * The idle thread. We try to conserve power, while trying to keep
71 * overall latency low. The architecture specific idle is passed
72 * a value to indicate the level of "idleness" of the system.
76 /* endless idle loop with no priority at all */
79 #ifdef CONFIG_HOTPLUG_CPU
80 if (cpu_is_offline(smp_processor_id()))
85 tick_nohz_idle_enter();
87 while (!need_resched())
90 tick_nohz_idle_exit();
91 preempt_enable_no_resched();
98 * Do necessary setup to start up a newly executed thread.
100 * pass the data segment into user programs if it exists,
101 * it can't hurt anything as far as I can tell
103 void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
107 regs->p5 = current->mm->start_data;
109 task_thread_info(current)->l1_task_info.stack_start =
110 (void *)current->mm->context.stack_start;
111 task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
112 memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
113 sizeof(*L1_SCRATCH_TASK_INFO));
117 EXPORT_SYMBOL_GPL(start_thread);
119 void flush_thread(void)
123 asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
125 #ifdef __ARCH_SYNC_CORE_DCACHE
126 if (current->nr_cpus_allowed == num_possible_cpus())
127 set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
131 return do_fork(clone_flags, newsp, 0, NULL, NULL);
135 copy_thread(unsigned long clone_flags,
136 unsigned long usp, unsigned long topstk,
137 struct task_struct *p)
139 struct pt_regs *childregs;
142 childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
143 v = ((unsigned long *)childregs) - 2;
144 if (unlikely(p->flags & PF_KTHREAD)) {
145 memset(childregs, 0, sizeof(struct pt_regs));
148 childregs->orig_p0 = -1;
149 childregs->ipend = 0x8000;
150 __asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
153 *childregs = *current_pt_regs();
155 p->thread.usp = usp ? : rdusp();
159 p->thread.ksp = (unsigned long)v;
160 p->thread.pc = (unsigned long)ret_from_fork;
165 unsigned long get_wchan(struct task_struct *p)
167 unsigned long fp, pc;
168 unsigned long stack_page;
170 if (!p || p == current || p->state == TASK_RUNNING)
173 stack_page = (unsigned long)p;
176 if (fp < stack_page + sizeof(struct thread_info) ||
177 fp >= 8184 + stack_page)
179 pc = ((unsigned long *)fp)[1];
180 if (!in_sched_functions(pc))
182 fp = *(unsigned long *)fp;
184 while (count++ < 16);
188 void finish_atomic_sections (struct pt_regs *regs)
190 int __user *up0 = (int __user *)regs->p0;
194 /* not in middle of an atomic step, so resume like normal */
197 case ATOMIC_XCHG32 + 2:
198 put_user(regs->r1, up0);
201 case ATOMIC_CAS32 + 2:
202 case ATOMIC_CAS32 + 4:
203 if (regs->r0 == regs->r1)
204 case ATOMIC_CAS32 + 6:
205 put_user(regs->r2, up0);
208 case ATOMIC_ADD32 + 2:
209 regs->r0 = regs->r1 + regs->r0;
211 case ATOMIC_ADD32 + 4:
212 put_user(regs->r0, up0);
215 case ATOMIC_SUB32 + 2:
216 regs->r0 = regs->r1 - regs->r0;
218 case ATOMIC_SUB32 + 4:
219 put_user(regs->r0, up0);
222 case ATOMIC_IOR32 + 2:
223 regs->r0 = regs->r1 | regs->r0;
225 case ATOMIC_IOR32 + 4:
226 put_user(regs->r0, up0);
229 case ATOMIC_AND32 + 2:
230 regs->r0 = regs->r1 & regs->r0;
232 case ATOMIC_AND32 + 4:
233 put_user(regs->r0, up0);
236 case ATOMIC_XOR32 + 2:
237 regs->r0 = regs->r1 ^ regs->r0;
239 case ATOMIC_XOR32 + 4:
240 put_user(regs->r0, up0);
245 * We've finished the atomic section, and the only thing left for
246 * userspace is to do a RTS, so we might as well handle that too
247 * since we need to update the PC anyways.
249 regs->pc = regs->rets;
253 int in_mem(unsigned long addr, unsigned long size,
254 unsigned long start, unsigned long end)
256 return addr >= start && addr + size <= end;
259 int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
260 unsigned long const_addr, unsigned long const_size)
263 in_mem(addr, size, const_addr + off, const_addr + const_size);
266 int in_mem_const(unsigned long addr, unsigned long size,
267 unsigned long const_addr, unsigned long const_size)
269 return in_mem_const_off(addr, size, 0, const_addr, const_size);
272 #define ASYNC_ENABLED(bnum, bctlnum) 1
274 #define ASYNC_ENABLED(bnum, bctlnum) \
276 (bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
277 bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
282 * We can't read EBIU banks that aren't enabled or we end up hanging
283 * on the access to the async space. Make sure we validate accesses
284 * that cross async banks too.
285 * 0 - found, but unusable
290 int in_async(unsigned long addr, unsigned long size)
292 if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
293 if (!ASYNC_ENABLED(0, 0))
295 if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
297 size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
298 addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
300 if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
301 if (!ASYNC_ENABLED(1, 0))
303 if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
305 size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
306 addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
308 if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
309 if (!ASYNC_ENABLED(2, 1))
311 if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
313 size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
314 addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
316 if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
317 if (ASYNC_ENABLED(3, 1))
319 if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
324 /* not within async bounds */
328 int bfin_mem_access_type(unsigned long addr, unsigned long size)
330 int cpu = raw_smp_processor_id();
332 /* Check that things do not wrap around */
333 if (addr > ULONG_MAX - size)
336 if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
337 return BFIN_MEM_ACCESS_CORE;
339 if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
340 return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
341 if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
342 return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
343 if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
344 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
345 if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
346 return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
347 #ifdef COREB_L1_CODE_START
348 if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
349 return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
350 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
351 return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
352 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
353 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
354 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
355 return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
357 if (in_mem_const(addr, size, L2_START, L2_LENGTH))
358 return BFIN_MEM_ACCESS_CORE;
360 if (addr >= SYSMMR_BASE)
361 return BFIN_MEM_ACCESS_CORE_ONLY;
363 switch (in_async(addr, size)) {
364 case 0: return -EFAULT;
365 case 1: return BFIN_MEM_ACCESS_CORE;
366 case 2: /* fall through */;
369 if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
370 return BFIN_MEM_ACCESS_CORE;
371 if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
372 return BFIN_MEM_ACCESS_DMA;
377 #if defined(CONFIG_ACCESS_CHECK)
378 #ifdef CONFIG_ACCESS_OK_L1
379 __attribute__((l1_text))
381 /* Return 1 if access to memory range is OK, 0 otherwise */
382 int _access_ok(unsigned long addr, unsigned long size)
388 /* Check that things do not wrap around */
389 if (addr > ULONG_MAX - size)
391 if (segment_eq(get_fs(), KERNEL_DS))
393 #ifdef CONFIG_MTD_UCLINUX
399 if (in_mem(addr, size, memory_start, memory_end))
401 if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
403 # ifndef CONFIG_ROMFS_ON_MTD
406 /* For XIP, allow user space to use pointers within the ROMFS. */
407 if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
410 if (in_mem(addr, size, memory_start, physical_mem_end))
414 if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
417 if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
419 if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
421 if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
423 if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
425 #ifdef COREB_L1_CODE_START
426 if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
428 if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
430 if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
432 if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
436 #ifndef CONFIG_EXCEPTION_L1_SCRATCH
437 if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
441 aret = in_async(addr, size);
445 if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
448 if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
450 if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
455 EXPORT_SYMBOL(_access_ok);
456 #endif /* CONFIG_ACCESS_CHECK */