arch/mips/boot/dts/brcm/bcm7362.dtsi

   1 / {
   2         #address-cells = <1>;
   3         #size-cells = <1>;
   4         compatible = "brcm,bcm7362";
   5
   6         cpus {
   7                 #address-cells = <1>;
   8                 #size-cells = <0>;
   9
  10                 mips-hpt-frequency = <375000000>;
  11
  12                 cpu@0 {
  13                         compatible = "brcm,bmips4380";
  14                         device_type = "cpu";
  15                         reg = <0>;
  16                 };
  17
  18                 cpu@1 {
  19                         compatible = "brcm,bmips4380";
  20                         device_type = "cpu";
  21                         reg = <1>;
  22                 };
  23         };
  24
  25         aliases {
  26                 uart0 = &uart0;
  27                 uart1 = &uart1;
  28                 uart2 = &uart2;
  29         };
  30
  31         cpu_intc: cpu_intc {
  32                 #address-cells = <0>;
  33                 compatible = "mti,cpu-interrupt-controller";
  34
  35                 interrupt-controller;
  36                 #interrupt-cells = <1>;
  37         };
  38
  39         clocks {
  40                 uart_clk: uart_clk {
  41                         compatible = "fixed-clock";
  42                         #clock-cells = <0>;
  43                         clock-frequency = <81000000>;
  44                 };
  45         };
  46
  47         rdb {
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50
  51                 compatible = "simple-bus";
  52                 ranges = <0 0x10000000 0x01000000>;
  53
  54                 periph_intc: periph_intc@411400 {
  55                         compatible = "brcm,bcm7038-l1-intc";
  56                         reg = <0x411400 0x30>, <0x411600 0x30>;
  57
  58                         interrupt-controller;
  59                         #interrupt-cells = <1>;
  60
  61                         interrupt-parent = <&cpu_intc>;
  62                         interrupts = <2>, <3>;
  63                 };
  64
  65                 sun_l2_intc: sun_l2_intc@403000 {
  66                         compatible = "brcm,l2-intc";
  67                         reg = <0x403000 0x30>;
  68                         interrupt-controller;
  69                         #interrupt-cells = <1>;
  70                         interrupt-parent = <&periph_intc>;
  71                         interrupts = <48>;
  72                 };
  73
  74                 gisb-arb@400000 {
  75                         compatible = "brcm,bcm7400-gisb-arb";
  76                         reg = <0x400000 0xdc>;
  77                         native-endian;
  78                         interrupt-parent = <&sun_l2_intc>;
  79                         interrupts = <0>, <2>;
  80                         brcm,gisb-arb-master-mask = <0x2f3>;
  81                         brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
  82                                                      "rdc_0", "raaga_0",
  83                                                      "avd_0", "jtag_0";
  84                 };
  85
  86                 upg_irq0_intc: upg_irq0_intc@406600 {
  87                         compatible = "brcm,bcm7120-l2-intc";
  88                         reg = <0x406600 0x8>;
  89
  90                         brcm,int-map-mask = <0x44>;
  91                         brcm,int-fwd-mask = <0x70000>;
  92
  93                         interrupt-controller;
  94                         #interrupt-cells = <1>;
  95
  96                         interrupt-parent = <&periph_intc>;
  97                         interrupts = <56>;
  98                 };
  99
 100                 sun_top_ctrl: syscon@404000 {
 101                         compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
 102                         reg = <0x404000 0x51c>;
 103                 };
 104
 105                 reboot {
 106                         compatible = "brcm,brcmstb-reboot";
 107                         syscon = <&sun_top_ctrl 0x304 0x308>;
 108                 };
 109
 110                 uart0: serial@406800 {
 111                         compatible = "ns16550a";
 112                         reg = <0x406800 0x20>;
 113                         reg-io-width = <0x4>;
 114                         reg-shift = <0x2>;
 115                         native-endian;
 116                         interrupt-parent = <&periph_intc>;
 117                         interrupts = <61>;
 118                         clocks = <&uart_clk>;
 119                         status = "disabled";
 120                 };
 121
 122                 uart1: serial@406840 {
 123                         compatible = "ns16550a";
 124                         reg = <0x406840 0x20>;
 125                         reg-io-width = <0x4>;
 126                         reg-shift = <0x2>;
 127                         native-endian;
 128                         interrupt-parent = <&periph_intc>;
 129                         interrupts = <62>;
 130                         clocks = <&uart_clk>;
 131                         status = "disabled";
 132                 };
 133
 134                 uart2: serial@406880 {
 135                         compatible = "ns16550a";
 136                         reg = <0x406880 0x20>;
 137                         reg-io-width = <0x4>;
 138                         reg-shift = <0x2>;
 139                         native-endian;
 140                         interrupt-parent = <&periph_intc>;
 141                         interrupts = <63>;
 142                         clocks = <&uart_clk>;
 143                         status = "disabled";
 144                 };
 145
 146                 enet0: ethernet@430000 {
 147                         phy-mode = "internal";
 148                         phy-handle = <&phy1>;
 149                         mac-address = [ 00 10 18 36 23 1a ];
 150                         compatible = "brcm,genet-v2";
 151                         #address-cells = <0x1>;
 152                         #size-cells = <0x1>;
 153                         reg = <0x430000 0x4c8c>;
 154                         interrupts = <24>, <25>;
 155                         interrupt-parent = <&periph_intc>;
 156                         status = "disabled";
 157
 158                         mdio@e14 {
 159                                 compatible = "brcm,genet-mdio-v2";
 160                                 #address-cells = <0x1>;
 161                                 #size-cells = <0x0>;
 162                                 reg = <0xe14 0x8>;
 163
 164                                 phy1: ethernet-phy@1 {
 165                                         max-speed = <100>;
 166                                         reg = <0x1>;
 167                                         compatible = "brcm,40nm-ephy",
 168                                                 "ethernet-phy-ieee802.3-c22";
 169                                 };
 170                         };
 171                 };
 172
 173                 ehci0: usb@480300 {
 174                         compatible = "brcm,bcm7362-ehci", "generic-ehci";
 175                         reg = <0x480300 0x100>;
 176                         native-endian;
 177                         interrupt-parent = <&periph_intc>;
 178                         interrupts = <65>;
 179                         status = "disabled";
 180                 };
 181
 182                 ohci0: usb@480400 {
 183                         compatible = "brcm,bcm7362-ohci", "generic-ohci";
 184                         reg = <0x480400 0x100>;
 185                         native-endian;
 186                         no-big-frame-no;
 187                         interrupt-parent = <&periph_intc>;
 188                         interrupts = <66>;
 189                         status = "disabled";
 190                 };
 191         };
 192 };