arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/war.h>
  20
  21 /*
  22  * The following macros are especially useful for __asm__
  23  * inline assembler.
  24  */
  25 #ifndef __STR
  26 #define __STR(x) #x
  27 #endif
  28 #ifndef STR
  29 #define STR(x) __STR(x)
  30 #endif
  31
  32 /*
  33  *  Configure language
  34  */
  35 #ifdef __ASSEMBLY__
  36 #define _ULCAST_
  37 #else
  38 #define _ULCAST_ (unsigned long)
  39 #endif
  40
  41 /*
  42  * Coprocessor 0 register names
  43  */
  44 #define CP0_INDEX $0
  45 #define CP0_RANDOM $1
  46 #define CP0_ENTRYLO0 $2
  47 #define CP0_ENTRYLO1 $3
  48 #define CP0_CONF $3
  49 #define CP0_CONTEXT $4
  50 #define CP0_PAGEMASK $5
  51 #define CP0_WIRED $6
  52 #define CP0_INFO $7
  53 #define CP0_BADVADDR $8
  54 #define CP0_BADINSTR $8, 1
  55 #define CP0_COUNT $9
  56 #define CP0_ENTRYHI $10
  57 #define CP0_COMPARE $11
  58 #define CP0_STATUS $12
  59 #define CP0_CAUSE $13
  60 #define CP0_EPC $14
  61 #define CP0_PRID $15
  62 #define CP0_EBASE $15, 1
  63 #define CP0_CMGCRBASE $15, 3
  64 #define CP0_CONFIG $16
  65 #define CP0_LLADDR $17
  66 #define CP0_WATCHLO $18
  67 #define CP0_WATCHHI $19
  68 #define CP0_XCONTEXT $20
  69 #define CP0_FRAMEMASK $21
  70 #define CP0_DIAGNOSTIC $22
  71 #define CP0_DEBUG $23
  72 #define CP0_DEPC $24
  73 #define CP0_PERFORMANCE $25
  74 #define CP0_ECC $26
  75 #define CP0_CACHEERR $27
  76 #define CP0_TAGLO $28
  77 #define CP0_TAGHI $29
  78 #define CP0_ERROREPC $30
  79 #define CP0_DESAVE $31
  80
  81 /*
  82  * R4640/R4650 cp0 register names.  These registers are listed
  83  * here only for completeness; without MMU these CPUs are not useable
  84  * by Linux.  A future ELKS port might take make Linux run on them
  85  * though ...
  86  */
  87 #define CP0_IBASE $0
  88 #define CP0_IBOUND $1
  89 #define CP0_DBASE $2
  90 #define CP0_DBOUND $3
  91 #define CP0_CALG $17
  92 #define CP0_IWATCH $18
  93 #define CP0_DWATCH $19
  94
  95 /*
  96  * Coprocessor 0 Set 1 register names
  97  */
  98 #define CP0_S1_DERRADDR0  $26
  99 #define CP0_S1_DERRADDR1  $27
 100 #define CP0_S1_INTCONTROL $20
 101
 102 /*
 103  * Coprocessor 0 Set 2 register names
 104  */
 105 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 106
 107 /*
 108  * Coprocessor 0 Set 3 register names
 109  */
 110 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 111
 112 /*
 113  *  TX39 Series
 114  */
 115 #define CP0_TX39_CACHE  $7
 116
 117
 118 /* Generic EntryLo bit definitions */
 119 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 120 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 121 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 122 #define ENTRYLO_C_SHIFT         3
 123 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 124
 125 /* R3000 EntryLo bit definitions */
 126 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 127 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 128 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 129 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 130
 131 /* MIPS32/64 EntryLo bit definitions */
 132 #define MIPS_ENTRYLO_PFN_SHIFT  6
 133 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 134 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 135
 136 /*
 137  * Values for PageMask register
 138  */
 139 #ifdef CONFIG_CPU_VR41XX
 140
 141 /* Why doesn't stupidity hurt ... */
 142
 143 #define PM_1K           0x00000000
 144 #define PM_4K           0x00001800
 145 #define PM_16K          0x00007800
 146 #define PM_64K          0x0001f800
 147 #define PM_256K         0x0007f800
 148
 149 #else
 150
 151 #define PM_4K           0x00000000
 152 #define PM_8K           0x00002000
 153 #define PM_16K          0x00006000
 154 #define PM_32K          0x0000e000
 155 #define PM_64K          0x0001e000
 156 #define PM_128K         0x0003e000
 157 #define PM_256K         0x0007e000
 158 #define PM_512K         0x000fe000
 159 #define PM_1M           0x001fe000
 160 #define PM_2M           0x003fe000
 161 #define PM_4M           0x007fe000
 162 #define PM_8M           0x00ffe000
 163 #define PM_16M          0x01ffe000
 164 #define PM_32M          0x03ffe000
 165 #define PM_64M          0x07ffe000
 166 #define PM_256M         0x1fffe000
 167 #define PM_1G           0x7fffe000
 168
 169 #endif
 170
 171 /*
 172  * Default page size for a given kernel configuration
 173  */
 174 #ifdef CONFIG_PAGE_SIZE_4KB
 175 #define PM_DEFAULT_MASK PM_4K
 176 #elif defined(CONFIG_PAGE_SIZE_8KB)
 177 #define PM_DEFAULT_MASK PM_8K
 178 #elif defined(CONFIG_PAGE_SIZE_16KB)
 179 #define PM_DEFAULT_MASK PM_16K
 180 #elif defined(CONFIG_PAGE_SIZE_32KB)
 181 #define PM_DEFAULT_MASK PM_32K
 182 #elif defined(CONFIG_PAGE_SIZE_64KB)
 183 #define PM_DEFAULT_MASK PM_64K
 184 #else
 185 #error Bad page size configuration!
 186 #endif
 187
 188 /*
 189  * Default huge tlb size for a given kernel configuration
 190  */
 191 #ifdef CONFIG_PAGE_SIZE_4KB
 192 #define PM_HUGE_MASK    PM_1M
 193 #elif defined(CONFIG_PAGE_SIZE_8KB)
 194 #define PM_HUGE_MASK    PM_4M
 195 #elif defined(CONFIG_PAGE_SIZE_16KB)
 196 #define PM_HUGE_MASK    PM_16M
 197 #elif defined(CONFIG_PAGE_SIZE_32KB)
 198 #define PM_HUGE_MASK    PM_64M
 199 #elif defined(CONFIG_PAGE_SIZE_64KB)
 200 #define PM_HUGE_MASK    PM_256M
 201 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 202 #error Bad page size configuration for hugetlbfs!
 203 #endif
 204
 205 /*
 206  * Values used for computation of new tlb entries
 207  */
 208 #define PL_4K           12
 209 #define PL_16K          14
 210 #define PL_64K          16
 211 #define PL_256K         18
 212 #define PL_1M           20
 213 #define PL_4M           22
 214 #define PL_16M          24
 215 #define PL_64M          26
 216 #define PL_256M         28
 217
 218 /*
 219  * PageGrain bits
 220  */
 221 #define PG_RIE          (_ULCAST_(1) <<  31)
 222 #define PG_XIE          (_ULCAST_(1) <<  30)
 223 #define PG_ELPA         (_ULCAST_(1) <<  29)
 224 #define PG_ESP          (_ULCAST_(1) <<  28)
 225 #define PG_IEC          (_ULCAST_(1) <<  27)
 226
 227 /* MIPS32/64 EntryHI bit definitions */
 228 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 229
 230 /*
 231  * R4x00 interrupt enable / cause bits
 232  */
 233 #define IE_SW0          (_ULCAST_(1) <<  8)
 234 #define IE_SW1          (_ULCAST_(1) <<  9)
 235 #define IE_IRQ0         (_ULCAST_(1) << 10)
 236 #define IE_IRQ1         (_ULCAST_(1) << 11)
 237 #define IE_IRQ2         (_ULCAST_(1) << 12)
 238 #define IE_IRQ3         (_ULCAST_(1) << 13)
 239 #define IE_IRQ4         (_ULCAST_(1) << 14)
 240 #define IE_IRQ5         (_ULCAST_(1) << 15)
 241
 242 /*
 243  * R4x00 interrupt cause bits
 244  */
 245 #define C_SW0           (_ULCAST_(1) <<  8)
 246 #define C_SW1           (_ULCAST_(1) <<  9)
 247 #define C_IRQ0          (_ULCAST_(1) << 10)
 248 #define C_IRQ1          (_ULCAST_(1) << 11)
 249 #define C_IRQ2          (_ULCAST_(1) << 12)
 250 #define C_IRQ3          (_ULCAST_(1) << 13)
 251 #define C_IRQ4          (_ULCAST_(1) << 14)
 252 #define C_IRQ5          (_ULCAST_(1) << 15)
 253
 254 /*
 255  * Bitfields in the R4xx0 cp0 status register
 256  */
 257 #define ST0_IE                  0x00000001
 258 #define ST0_EXL                 0x00000002
 259 #define ST0_ERL                 0x00000004
 260 #define ST0_KSU                 0x00000018
 261 #  define KSU_USER              0x00000010
 262 #  define KSU_SUPERVISOR        0x00000008
 263 #  define KSU_KERNEL            0x00000000
 264 #define ST0_UX                  0x00000020
 265 #define ST0_SX                  0x00000040
 266 #define ST0_KX                  0x00000080
 267 #define ST0_DE                  0x00010000
 268 #define ST0_CE                  0x00020000
 269
 270 /*
 271  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 272  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 273  * processors.
 274  */
 275 #define ST0_CO                  0x08000000
 276
 277 /*
 278  * Bitfields in the R[23]000 cp0 status register.
 279  */
 280 #define ST0_IEC                 0x00000001
 281 #define ST0_KUC                 0x00000002
 282 #define ST0_IEP                 0x00000004
 283 #define ST0_KUP                 0x00000008
 284 #define ST0_IEO                 0x00000010
 285 #define ST0_KUO                 0x00000020
 286 /* bits 6 & 7 are reserved on R[23]000 */
 287 #define ST0_ISC                 0x00010000
 288 #define ST0_SWC                 0x00020000
 289 #define ST0_CM                  0x00080000
 290
 291 /*
 292  * Bits specific to the R4640/R4650
 293  */
 294 #define ST0_UM                  (_ULCAST_(1) <<  4)
 295 #define ST0_IL                  (_ULCAST_(1) << 23)
 296 #define ST0_DL                  (_ULCAST_(1) << 24)
 297
 298 /*
 299  * Enable the MIPS MDMX and DSP ASEs
 300  */
 301 #define ST0_MX                  0x01000000
 302
 303 /*
 304  * Status register bits available in all MIPS CPUs.
 305  */
 306 #define ST0_IM                  0x0000ff00
 307 #define  STATUSB_IP0            8
 308 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 309 #define  STATUSB_IP1            9
 310 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 311 #define  STATUSB_IP2            10
 312 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 313 #define  STATUSB_IP3            11
 314 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 315 #define  STATUSB_IP4            12
 316 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 317 #define  STATUSB_IP5            13
 318 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 319 #define  STATUSB_IP6            14
 320 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 321 #define  STATUSB_IP7            15
 322 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 323 #define  STATUSB_IP8            0
 324 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 325 #define  STATUSB_IP9            1
 326 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 327 #define  STATUSB_IP10           2
 328 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 329 #define  STATUSB_IP11           3
 330 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 331 #define  STATUSB_IP12           4
 332 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 333 #define  STATUSB_IP13           5
 334 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 335 #define  STATUSB_IP14           6
 336 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 337 #define  STATUSB_IP15           7
 338 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 339 #define ST0_CH                  0x00040000
 340 #define ST0_NMI                 0x00080000
 341 #define ST0_SR                  0x00100000
 342 #define ST0_TS                  0x00200000
 343 #define ST0_BEV                 0x00400000
 344 #define ST0_RE                  0x02000000
 345 #define ST0_FR                  0x04000000
 346 #define ST0_CU                  0xf0000000
 347 #define ST0_CU0                 0x10000000
 348 #define ST0_CU1                 0x20000000
 349 #define ST0_CU2                 0x40000000
 350 #define ST0_CU3                 0x80000000
 351 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 352
 353 /*
 354  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 355  */
 356 #define INTCTLB_IPFDC           23
 357 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 358 #define INTCTLB_IPPCI           26
 359 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 360 #define INTCTLB_IPTI            29
 361 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 362
 363 /*
 364  * Bitfields and bit numbers in the coprocessor 0 cause register.
 365  *
 366  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 367  */
 368 #define CAUSEB_EXCCODE          2
 369 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 370 #define CAUSEB_IP               8
 371 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 372 #define  CAUSEB_IP0             8
 373 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 374 #define  CAUSEB_IP1             9
 375 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 376 #define  CAUSEB_IP2             10
 377 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 378 #define  CAUSEB_IP3             11
 379 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 380 #define  CAUSEB_IP4             12
 381 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 382 #define  CAUSEB_IP5             13
 383 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 384 #define  CAUSEB_IP6             14
 385 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 386 #define  CAUSEB_IP7             15
 387 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 388 #define CAUSEB_FDCI             21
 389 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 390 #define CAUSEB_IV               23
 391 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 392 #define CAUSEB_PCI              26
 393 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 394 #define CAUSEB_CE               28
 395 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 396 #define CAUSEB_TI               30
 397 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 398 #define CAUSEB_BD               31
 399 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 400
 401 /*
 402  * Bits in the coprocessor 0 config register.
 403  */
 404 /* Generic bits.  */
 405 #define CONF_CM_CACHABLE_NO_WA          0
 406 #define CONF_CM_CACHABLE_WA             1
 407 #define CONF_CM_UNCACHED                2
 408 #define CONF_CM_CACHABLE_NONCOHERENT    3
 409 #define CONF_CM_CACHABLE_CE             4
 410 #define CONF_CM_CACHABLE_COW            5
 411 #define CONF_CM_CACHABLE_CUW            6
 412 #define CONF_CM_CACHABLE_ACCELERATED    7
 413 #define CONF_CM_CMASK                   7
 414 #define CONF_BE                 (_ULCAST_(1) << 15)
 415
 416 /* Bits common to various processors.  */
 417 #define CONF_CU                 (_ULCAST_(1) <<  3)
 418 #define CONF_DB                 (_ULCAST_(1) <<  4)
 419 #define CONF_IB                 (_ULCAST_(1) <<  5)
 420 #define CONF_DC                 (_ULCAST_(7) <<  6)
 421 #define CONF_IC                 (_ULCAST_(7) <<  9)
 422 #define CONF_EB                 (_ULCAST_(1) << 13)
 423 #define CONF_EM                 (_ULCAST_(1) << 14)
 424 #define CONF_SM                 (_ULCAST_(1) << 16)
 425 #define CONF_SC                 (_ULCAST_(1) << 17)
 426 #define CONF_EW                 (_ULCAST_(3) << 18)
 427 #define CONF_EP                 (_ULCAST_(15)<< 24)
 428 #define CONF_EC                 (_ULCAST_(7) << 28)
 429 #define CONF_CM                 (_ULCAST_(1) << 31)
 430
 431 /* Bits specific to the R4xx0.  */
 432 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 433 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 434 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 435
 436 /* Bits specific to the R5000.  */
 437 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 438 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 439
 440 /* Bits specific to the RM7000.  */
 441 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 442 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 443 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 444 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 445 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 446 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 447
 448 /* Bits specific to the R10000.  */
 449 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 450 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 451 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 452 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 453 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 454 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 455 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 456 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 457 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 458 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 459 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 460
 461 /* Bits specific to the VR41xx.  */
 462 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 463 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 464 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 465 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 466 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 467
 468 /* Bits specific to the R30xx.  */
 469 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 470 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 471 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 472 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 473 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 474 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 475 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 476 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 477 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 478
 479 /* Bits specific to the TX49.  */
 480 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 481 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 482 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 483 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 484
 485 /* Bits specific to the MIPS32/64 PRA.  */
 486 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 487 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 488 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 489 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 490 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 491 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 492
 493 /*
 494  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 495  */
 496 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 497 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 498 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 499 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 500 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 501 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 502 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 503 #define MIPS_CONF1_DA_SHF       7
 504 #define MIPS_CONF1_DA_SZ        3
 505 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 506 #define MIPS_CONF1_DL_SHF       10
 507 #define MIPS_CONF1_DL_SZ        3
 508 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 509 #define MIPS_CONF1_DS_SHF       13
 510 #define MIPS_CONF1_DS_SZ        3
 511 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 512 #define MIPS_CONF1_IA_SHF       16
 513 #define MIPS_CONF1_IA_SZ        3
 514 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 515 #define MIPS_CONF1_IL_SHF       19
 516 #define MIPS_CONF1_IL_SZ        3
 517 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 518 #define MIPS_CONF1_IS_SHF       22
 519 #define MIPS_CONF1_IS_SZ        3
 520 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 521 #define MIPS_CONF1_TLBS_SHIFT   (25)
 522 #define MIPS_CONF1_TLBS_SIZE    (6)
 523 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 524
 525 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 526 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 527 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 528 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 529 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 530 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 531 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 532 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 533
 534 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 535 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 536 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 537 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 538 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 539 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 540 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 541 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 542 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 543 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 544 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 545 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 546 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 547 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 548 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 549 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 550 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 551 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 552 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 553 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 554 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 555 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 556 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 557 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 558 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 559 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 560 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 561
 562 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 563 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 564 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 565 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 566 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 567 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 568 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 569 /* bits 10:8 in FTLB-only configurations */
 570 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 571 /* bits 12:8 in VTLB-FTLB only configurations */
 572 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 573 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 574 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 575 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 576 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 577 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << 16)
 578 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 579 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 580 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 581 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 582 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 583
 584 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 585 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 586 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 587 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 588 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 589 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 590 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 591 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 592 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 593 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 594 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 595
 596 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 597 /* proAptiv FTLB on/off bit */
 598 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 599 /* FTLB probability bits */
 600 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 601
 602 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 603
 604 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 605
 606 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 607 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 608 /* FTLB probability bits for R6 */
 609 #define MIPS_CONF7_FTLBP_SHIFT  (18)
 610
 611 /* MAAR bit definitions */
 612 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 613 #define MIPS_MAAR_ADDR_SHIFT    12
 614 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 615 #define MIPS_MAAR_V             (_ULCAST_(1) << 0)
 616
 617 /* CMGCRBase bit definitions */
 618 #define MIPS_CMGCRB_BASE        11
 619 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 620
 621 /*
 622  * Bits in the MIPS32 Memory Segmentation registers.
 623  */
 624 #define MIPS_SEGCFG_PA_SHIFT    9
 625 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 626 #define MIPS_SEGCFG_AM_SHIFT    4
 627 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 628 #define MIPS_SEGCFG_EU_SHIFT    3
 629 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 630 #define MIPS_SEGCFG_C_SHIFT     0
 631 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 632
 633 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 634 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 635 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 636 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 637 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 638 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 639 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 640
 641 #define MIPS_PWFIELD_GDI_SHIFT  24
 642 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 643 #define MIPS_PWFIELD_UDI_SHIFT  18
 644 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 645 #define MIPS_PWFIELD_MDI_SHIFT  12
 646 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 647 #define MIPS_PWFIELD_PTI_SHIFT  6
 648 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 649 #define MIPS_PWFIELD_PTEI_SHIFT 0
 650 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 651
 652 #define MIPS_PWSIZE_GDW_SHIFT   24
 653 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 654 #define MIPS_PWSIZE_UDW_SHIFT   18
 655 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 656 #define MIPS_PWSIZE_MDW_SHIFT   12
 657 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 658 #define MIPS_PWSIZE_PTW_SHIFT   6
 659 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 660 #define MIPS_PWSIZE_PTEW_SHIFT  0
 661 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 662
 663 #define MIPS_PWCTL_PWEN_SHIFT   31
 664 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 665 #define MIPS_PWCTL_DPH_SHIFT    7
 666 #define MIPS_PWCTL_DPH_MASK     0x00000080
 667 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 668 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 669 #define MIPS_PWCTL_PSN_SHIFT    0
 670 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 671
 672 /* CDMMBase register bit definitions */
 673 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 674 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 675 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 676 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 677 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 678 #define MIPS_CDMMBASE_ADDR_START 15
 679
 680 /*
 681  * Bitfields in the TX39 family CP0 Configuration Register 3
 682  */
 683 #define TX39_CONF_ICS_SHIFT     19
 684 #define TX39_CONF_ICS_MASK      0x00380000
 685 #define TX39_CONF_ICS_1KB       0x00000000
 686 #define TX39_CONF_ICS_2KB       0x00080000
 687 #define TX39_CONF_ICS_4KB       0x00100000
 688 #define TX39_CONF_ICS_8KB       0x00180000
 689 #define TX39_CONF_ICS_16KB      0x00200000
 690
 691 #define TX39_CONF_DCS_SHIFT     16
 692 #define TX39_CONF_DCS_MASK      0x00070000
 693 #define TX39_CONF_DCS_1KB       0x00000000
 694 #define TX39_CONF_DCS_2KB       0x00010000
 695 #define TX39_CONF_DCS_4KB       0x00020000
 696 #define TX39_CONF_DCS_8KB       0x00030000
 697 #define TX39_CONF_DCS_16KB      0x00040000
 698
 699 #define TX39_CONF_CWFON         0x00004000
 700 #define TX39_CONF_WBON          0x00002000
 701 #define TX39_CONF_RF_SHIFT      10
 702 #define TX39_CONF_RF_MASK       0x00000c00
 703 #define TX39_CONF_DOZE          0x00000200
 704 #define TX39_CONF_HALT          0x00000100
 705 #define TX39_CONF_LOCK          0x00000080
 706 #define TX39_CONF_ICE           0x00000020
 707 #define TX39_CONF_DCE           0x00000010
 708 #define TX39_CONF_IRSIZE_SHIFT  2
 709 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 710 #define TX39_CONF_DRSIZE_SHIFT  0
 711 #define TX39_CONF_DRSIZE_MASK   0x00000003
 712
 713 /*
 714  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 715  */
 716 /* Disable Branch Target Address Cache */
 717 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 718 /* Enable Branch Prediction Global History */
 719 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 720 /* Disable Branch Return Cache */
 721 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 722
 723 /*
 724  * Coprocessor 1 (FPU) register names
 725  */
 726 #define CP1_REVISION    $0
 727 #define CP1_UFR         $1
 728 #define CP1_UNFR        $4
 729 #define CP1_FCCR        $25
 730 #define CP1_FEXR        $26
 731 #define CP1_FENR        $28
 732 #define CP1_STATUS      $31
 733
 734
 735 /*
 736  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
 737  */
 738 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
 739 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
 740 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
 741 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
 742 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
 743 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
 744 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
 745 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
 746 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
 747 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
 748
 749 /*
 750  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
 751  */
 752 #define MIPS_FCCR_CONDX_S       0
 753 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
 754 #define MIPS_FCCR_COND0_S       0
 755 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
 756 #define MIPS_FCCR_COND1_S       1
 757 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
 758 #define MIPS_FCCR_COND2_S       2
 759 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
 760 #define MIPS_FCCR_COND3_S       3
 761 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
 762 #define MIPS_FCCR_COND4_S       4
 763 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
 764 #define MIPS_FCCR_COND5_S       5
 765 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
 766 #define MIPS_FCCR_COND6_S       6
 767 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
 768 #define MIPS_FCCR_COND7_S       7
 769 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
 770
 771 /*
 772  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
 773  */
 774 #define MIPS_FENR_FS_S          2
 775 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
 776
 777 /*
 778  * FPU Status Register Values
 779  */
 780 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
 781 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
 782
 783 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
 784 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
 785
 786 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
 787 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
 788 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
 789 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
 790 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
 791 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
 792 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
 793 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
 794 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
 795 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
 796 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
 797 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
 798 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
 799 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
 800 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
 801 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
 802
 803 /*
 804  * Bits 22:20 of the FPU Status Register will be read as 0,
 805  * and should be written as zero.
 806  */
 807 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
 808
 809 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
 810 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
 811
 812 /*
 813  * X the exception cause indicator
 814  * E the exception enable
 815  * S the sticky/flag bit
 816 */
 817 #define FPU_CSR_ALL_X   0x0003f000
 818 #define FPU_CSR_UNI_X   0x00020000
 819 #define FPU_CSR_INV_X   0x00010000
 820 #define FPU_CSR_DIV_X   0x00008000
 821 #define FPU_CSR_OVF_X   0x00004000
 822 #define FPU_CSR_UDF_X   0x00002000
 823 #define FPU_CSR_INE_X   0x00001000
 824
 825 #define FPU_CSR_ALL_E   0x00000f80
 826 #define FPU_CSR_INV_E   0x00000800
 827 #define FPU_CSR_DIV_E   0x00000400
 828 #define FPU_CSR_OVF_E   0x00000200
 829 #define FPU_CSR_UDF_E   0x00000100
 830 #define FPU_CSR_INE_E   0x00000080
 831
 832 #define FPU_CSR_ALL_S   0x0000007c
 833 #define FPU_CSR_INV_S   0x00000040
 834 #define FPU_CSR_DIV_S   0x00000020
 835 #define FPU_CSR_OVF_S   0x00000010
 836 #define FPU_CSR_UDF_S   0x00000008
 837 #define FPU_CSR_INE_S   0x00000004
 838
 839 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 840 #define FPU_CSR_RM      0x00000003
 841 #define FPU_CSR_RN      0x0     /* nearest */
 842 #define FPU_CSR_RZ      0x1     /* towards zero */
 843 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 844 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 845
 846
 847 #ifndef __ASSEMBLY__
 848
 849 /*
 850  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
 851  */
 852 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
 853     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
 854 #define get_isa16_mode(x)               ((x) & 0x1)
 855 #define msk_isa16_mode(x)               ((x) & ~0x1)
 856 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
 857 #else
 858 #define get_isa16_mode(x)               0
 859 #define msk_isa16_mode(x)               (x)
 860 #define set_isa16_mode(x)               do { } while(0)
 861 #endif
 862
 863 /*
 864  * microMIPS instructions can be 16-bit or 32-bit in length. This
 865  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
 866  */
 867 static inline int mm_insn_16bit(u16 insn)
 868 {
 869         u16 opcode = (insn >> 10) & 0x7;
 870
 871         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
 872 }
 873
 874 /*
 875  * TLB Invalidate Flush
 876  */
 877 static inline void tlbinvf(void)
 878 {
 879         __asm__ __volatile__(
 880                 ".set push\n\t"
 881                 ".set noreorder\n\t"
 882                 ".word 0x42000004\n\t" /* tlbinvf */
 883                 ".set pop");
 884 }
 885
 886
 887 /*
 888  * Functions to access the R10000 performance counters.  These are basically
 889  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
 890  * performance counter number encoded into bits 1 ... 5 of the instruction.
 891  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
 892  * disassembler these will look like an access to sel 0 or 1.
 893  */
 894 #define read_r10k_perf_cntr(counter)                            \
 895 ({                                                              \
 896         unsigned int __res;                                     \
 897         __asm__ __volatile__(                                   \
 898         "mfpc\t%0, %1"                                          \
 899         : "=r" (__res)                                          \
 900         : "i" (counter));                                       \
 901                                                                 \
 902         __res;                                                  \
 903 })
 904
 905 #define write_r10k_perf_cntr(counter,val)                       \
 906 do {                                                            \
 907         __asm__ __volatile__(                                   \
 908         "mtpc\t%0, %1"                                          \
 909         :                                                       \
 910         : "r" (val), "i" (counter));                            \
 911 } while (0)
 912
 913 #define read_r10k_perf_event(counter)                           \
 914 ({                                                              \
 915         unsigned int __res;                                     \
 916         __asm__ __volatile__(                                   \
 917         "mfps\t%0, %1"                                          \
 918         : "=r" (__res)                                          \
 919         : "i" (counter));                                       \
 920                                                                 \
 921         __res;                                                  \
 922 })
 923
 924 #define write_r10k_perf_cntl(counter,val)                       \
 925 do {                                                            \
 926         __asm__ __volatile__(                                   \
 927         "mtps\t%0, %1"                                          \
 928         :                                                       \
 929         : "r" (val), "i" (counter));                            \
 930 } while (0)
 931
 932
 933 /*
 934  * Macros to access the system control coprocessor
 935  */
 936
 937 #define __read_32bit_c0_register(source, sel)                           \
 938 ({ unsigned int __res;                                                  \
 939         if (sel == 0)                                                   \
 940                 __asm__ __volatile__(                                   \
 941                         "mfc0\t%0, " #source "\n\t"                     \
 942                         : "=r" (__res));                                \
 943         else                                                            \
 944                 __asm__ __volatile__(                                   \
 945                         ".set\tmips32\n\t"                              \
 946                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
 947                         ".set\tmips0\n\t"                               \
 948                         : "=r" (__res));                                \
 949         __res;                                                          \
 950 })
 951
 952 #define __read_64bit_c0_register(source, sel)                           \
 953 ({ unsigned long long __res;                                            \
 954         if (sizeof(unsigned long) == 4)                                 \
 955                 __res = __read_64bit_c0_split(source, sel);             \
 956         else if (sel == 0)                                              \
 957                 __asm__ __volatile__(                                   \
 958                         ".set\tmips3\n\t"                               \
 959                         "dmfc0\t%0, " #source "\n\t"                    \
 960                         ".set\tmips0"                                   \
 961                         : "=r" (__res));                                \
 962         else                                                            \
 963                 __asm__ __volatile__(                                   \
 964                         ".set\tmips64\n\t"                              \
 965                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
 966                         ".set\tmips0"                                   \
 967                         : "=r" (__res));                                \
 968         __res;                                                          \
 969 })
 970
 971 #define __write_32bit_c0_register(register, sel, value)                 \
 972 do {                                                                    \
 973         if (sel == 0)                                                   \
 974                 __asm__ __volatile__(                                   \
 975                         "mtc0\t%z0, " #register "\n\t"                  \
 976                         : : "Jr" ((unsigned int)(value)));              \
 977         else                                                            \
 978                 __asm__ __volatile__(                                   \
 979                         ".set\tmips32\n\t"                              \
 980                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
 981                         ".set\tmips0"                                   \
 982                         : : "Jr" ((unsigned int)(value)));              \
 983 } while (0)
 984
 985 #define __write_64bit_c0_register(register, sel, value)                 \
 986 do {                                                                    \
 987         if (sizeof(unsigned long) == 4)                                 \
 988                 __write_64bit_c0_split(register, sel, value);           \
 989         else if (sel == 0)                                              \
 990                 __asm__ __volatile__(                                   \
 991                         ".set\tmips3\n\t"                               \
 992                         "dmtc0\t%z0, " #register "\n\t"                 \
 993                         ".set\tmips0"                                   \
 994                         : : "Jr" (value));                              \
 995         else                                                            \
 996                 __asm__ __volatile__(                                   \
 997                         ".set\tmips64\n\t"                              \
 998                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
 999                         ".set\tmips0"                                   \
1000                         : : "Jr" (value));                              \
1001 } while (0)
1002
1003 #define __read_ulong_c0_register(reg, sel)                              \
1004         ((sizeof(unsigned long) == 4) ?                                 \
1005         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1006         (unsigned long) __read_64bit_c0_register(reg, sel))
1007
1008 #define __write_ulong_c0_register(reg, sel, val)                        \
1009 do {                                                                    \
1010         if (sizeof(unsigned long) == 4)                                 \
1011                 __write_32bit_c0_register(reg, sel, val);               \
1012         else                                                            \
1013                 __write_64bit_c0_register(reg, sel, val);               \
1014 } while (0)
1015
1016 /*
1017  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1018  */
1019 #define __read_32bit_c0_ctrl_register(source)                           \
1020 ({ unsigned int __res;                                                  \
1021         __asm__ __volatile__(                                           \
1022                 "cfc0\t%0, " #source "\n\t"                             \
1023                 : "=r" (__res));                                        \
1024         __res;                                                          \
1025 })
1026
1027 #define __write_32bit_c0_ctrl_register(register, value)                 \
1028 do {                                                                    \
1029         __asm__ __volatile__(                                           \
1030                 "ctc0\t%z0, " #register "\n\t"                          \
1031                 : : "Jr" ((unsigned int)(value)));                      \
1032 } while (0)
1033
1034 /*
1035  * These versions are only needed for systems with more than 38 bits of
1036  * physical address space running the 32-bit kernel.  That's none atm :-)
1037  */
1038 #define __read_64bit_c0_split(source, sel)                              \
1039 ({                                                                      \
1040         unsigned long long __val;                                       \
1041         unsigned long __flags;                                          \
1042                                                                         \
1043         local_irq_save(__flags);                                        \
1044         if (sel == 0)                                                   \
1045                 __asm__ __volatile__(                                   \
1046                         ".set\tmips64\n\t"                              \
1047                         "dmfc0\t%M0, " #source "\n\t"                   \
1048                         "dsll\t%L0, %M0, 32\n\t"                        \
1049                         "dsra\t%M0, %M0, 32\n\t"                        \
1050                         "dsra\t%L0, %L0, 32\n\t"                        \
1051                         ".set\tmips0"                                   \
1052                         : "=r" (__val));                                \
1053         else                                                            \
1054                 __asm__ __volatile__(                                   \
1055                         ".set\tmips64\n\t"                              \
1056                         "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
1057                         "dsll\t%L0, %M0, 32\n\t"                        \
1058                         "dsra\t%M0, %M0, 32\n\t"                        \
1059                         "dsra\t%L0, %L0, 32\n\t"                        \
1060                         ".set\tmips0"                                   \
1061                         : "=r" (__val));                                \
1062         local_irq_restore(__flags);                                     \
1063                                                                         \
1064         __val;                                                          \
1065 })
1066
1067 #define __write_64bit_c0_split(source, sel, val)                        \
1068 do {                                                                    \
1069         unsigned long __flags;                                          \
1070                                                                         \
1071         local_irq_save(__flags);                                        \
1072         if (sel == 0)                                                   \
1073                 __asm__ __volatile__(                                   \
1074                         ".set\tmips64\n\t"                              \
1075                         "dsll\t%L0, %L0, 32\n\t"                        \
1076                         "dsrl\t%L0, %L0, 32\n\t"                        \
1077                         "dsll\t%M0, %M0, 32\n\t"                        \
1078                         "or\t%L0, %L0, %M0\n\t"                         \
1079                         "dmtc0\t%L0, " #source "\n\t"                   \
1080                         ".set\tmips0"                                   \
1081                         : : "r" (val));                                 \
1082         else                                                            \
1083                 __asm__ __volatile__(                                   \
1084                         ".set\tmips64\n\t"                              \
1085                         "dsll\t%L0, %L0, 32\n\t"                        \
1086                         "dsrl\t%L0, %L0, 32\n\t"                        \
1087                         "dsll\t%M0, %M0, 32\n\t"                        \
1088                         "or\t%L0, %L0, %M0\n\t"                         \
1089                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1090                         ".set\tmips0"                                   \
1091                         : : "r" (val));                                 \
1092         local_irq_restore(__flags);                                     \
1093 } while (0)
1094
1095 #define __readx_32bit_c0_register(source)                               \
1096 ({                                                                      \
1097         unsigned int __res;                                             \
1098                                                                         \
1099         __asm__ __volatile__(                                           \
1100         "       .set    push                                    \n"     \
1101         "       .set    noat                                    \n"     \
1102         "       .set    mips32r2                                \n"     \
1103         "       .insn                                           \n"     \
1104         "       # mfhc0 $1, %1                                  \n"     \
1105         "       .word   (0x40410000 | ((%1 & 0x1f) << 11))      \n"     \
1106         "       move    %0, $1                                  \n"     \
1107         "       .set    pop                                     \n"     \
1108         : "=r" (__res)                                                  \
1109         : "i" (source));                                                \
1110         __res;                                                          \
1111 })
1112
1113 #define __writex_32bit_c0_register(register, value)                     \
1114 do {                                                                    \
1115         __asm__ __volatile__(                                           \
1116         "       .set    push                                    \n"     \
1117         "       .set    noat                                    \n"     \
1118         "       .set    mips32r2                                \n"     \
1119         "       move    $1, %0                                  \n"     \
1120         "       # mthc0 $1, %1                                  \n"     \
1121         "       .insn                                           \n"     \
1122         "       .word   (0x40c10000 | ((%1 & 0x1f) << 11))      \n"     \
1123         "       .set    pop                                     \n"     \
1124         :                                                               \
1125         : "r" (value), "i" (register));                                 \
1126 } while (0)
1127
1128 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1129 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1130
1131 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1132 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1133
1134 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1135 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1136
1137 #define readx_c0_entrylo0()     __readx_32bit_c0_register(2)
1138 #define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1139
1140 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1141 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1142
1143 #define readx_c0_entrylo1()     __readx_32bit_c0_register(3)
1144 #define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1145
1146 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1147 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1148
1149 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1150 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1151
1152 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1153 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1154
1155 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1156 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1157
1158 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1159 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1160
1161 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1162 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1163
1164 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1165
1166 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1167 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1168
1169 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1170 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1171
1172 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1173 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1174
1175 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1176 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1177
1178 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1179 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1180
1181 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1182 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1183
1184 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1185 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1186
1187 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1188 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1189
1190 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1191 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1192
1193 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1194
1195 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1196
1197 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1198 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1199
1200 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1201 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1202
1203 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1204
1205 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1206
1207 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1208 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1209 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1210 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1211 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1212 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1213 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1214 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1215 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1216 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1217 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1218 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1219 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1220 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1221 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1222 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1223
1224 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1225 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1226 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1227 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1228 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1229 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1230
1231 /*
1232  * The WatchLo register.  There may be up to 8 of them.
1233  */
1234 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1235 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1236 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1237 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1238 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1239 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1240 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1241 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1242 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1243 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1244 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1245 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1246 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1247 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1248 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1249 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1250
1251 /*
1252  * The WatchHi register.  There may be up to 8 of them.
1253  */
1254 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1255 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1256 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1257 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1258 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1259 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1260 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1261 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1262
1263 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1264 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1265 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1266 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1267 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1268 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1269 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1270 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1271
1272 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1273 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1274
1275 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1276 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1277
1278 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1279 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1280
1281 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1282 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1283
1284 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1285 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1286 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1287
1288 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1289 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1290
1291 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1292 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1293
1294 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1295 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1296
1297 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1298 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1299
1300 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1301 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1302
1303 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1304 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1305
1306 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1307 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1308
1309 /*
1310  * MIPS32 / MIPS64 performance counters
1311  */
1312 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1313 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1314 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1315 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1316 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1317 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1318 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1319 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1320 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1321 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1322 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1323 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1324 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1325 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1326 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1327 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1328 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1329 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1330 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1331 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1332 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1333 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1334 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1335 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1336
1337 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1338 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1339
1340 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1341 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1342
1343 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1344
1345 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1346 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1347
1348 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1349 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1350
1351 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1352 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1353
1354 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1355 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1356
1357 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1358 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1359
1360 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1361 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1362
1363 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1364 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1365
1366 /* MIPSR2 */
1367 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1368 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1369
1370 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1371 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1372
1373 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1374 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1375
1376 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1377 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1378
1379 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1380 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1381
1382 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1383 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1384
1385 /* MIPSR3 */
1386 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1387 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1388
1389 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1390 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1391
1392 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1393 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1394
1395 /* Hardware Page Table Walker */
1396 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1397 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1398
1399 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1400 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1401
1402 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1403 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1404
1405 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1406 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1407
1408 /* Cavium OCTEON (cnMIPS) */
1409 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1410 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1411
1412 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1413 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1414
1415 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1416 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1417 /*
1418  * The cacheerr registers are not standardized.  On OCTEON, they are
1419  * 64 bits wide.
1420  */
1421 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1422 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1423
1424 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1425 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1426
1427 /* BMIPS3300 */
1428 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1429 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1430
1431 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1432 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1433
1434 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1435 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1436
1437 /* BMIPS43xx */
1438 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1439 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1440
1441 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1442 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1443
1444 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1445 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1446
1447 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1448 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1449
1450 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1451 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1452
1453 /* BMIPS5000 */
1454 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1455 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1456
1457 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1458 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1459
1460 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1461 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1462
1463 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1464 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1465
1466 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1467 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1468
1469 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1470 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1471
1472 /*
1473  * Macros to access the floating point coprocessor control registers
1474  */
1475 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
1476 ({                                                                      \
1477         unsigned int __res;                                             \
1478                                                                         \
1479         __asm__ __volatile__(                                           \
1480         "       .set    push                                    \n"     \
1481         "       .set    reorder                                 \n"     \
1482         "       # gas fails to assemble cfc1 for some archs,    \n"     \
1483         "       # like Octeon.                                  \n"     \
1484         "       .set    mips1                                   \n"     \
1485         "       "STR(gas_hardfloat)"                            \n"     \
1486         "       cfc1    %0,"STR(source)"                        \n"     \
1487         "       .set    pop                                     \n"     \
1488         : "=r" (__res));                                                \
1489         __res;                                                          \
1490 })
1491
1492 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
1493 do {                                                                    \
1494         __asm__ __volatile__(                                           \
1495         "       .set    push                                    \n"     \
1496         "       .set    reorder                                 \n"     \
1497         "       "STR(gas_hardfloat)"                            \n"     \
1498         "       ctc1    %0,"STR(dest)"                          \n"     \
1499         "       .set    pop                                     \n"     \
1500         : : "r" (val));                                                 \
1501 } while (0)
1502
1503 #ifdef GAS_HAS_SET_HARDFLOAT
1504 #define read_32bit_cp1_register(source)                                 \
1505         _read_32bit_cp1_register(source, .set hardfloat)
1506 #define write_32bit_cp1_register(dest, val)                             \
1507         _write_32bit_cp1_register(dest, val, .set hardfloat)
1508 #else
1509 #define read_32bit_cp1_register(source)                                 \
1510         _read_32bit_cp1_register(source, )
1511 #define write_32bit_cp1_register(dest, val)                             \
1512         _write_32bit_cp1_register(dest, val, )
1513 #endif
1514
1515 #ifdef HAVE_AS_DSP
1516 #define rddsp(mask)                                                     \
1517 ({                                                                      \
1518         unsigned int __dspctl;                                          \
1519                                                                         \
1520         __asm__ __volatile__(                                           \
1521         "       .set push                                       \n"     \
1522         "       .set dsp                                        \n"     \
1523         "       rddsp   %0, %x1                                 \n"     \
1524         "       .set pop                                        \n"     \
1525         : "=r" (__dspctl)                                               \
1526         : "i" (mask));                                                  \
1527         __dspctl;                                                       \
1528 })
1529
1530 #define wrdsp(val, mask)                                                \
1531 do {                                                                    \
1532         __asm__ __volatile__(                                           \
1533         "       .set push                                       \n"     \
1534         "       .set dsp                                        \n"     \
1535         "       wrdsp   %0, %x1                                 \n"     \
1536         "       .set pop                                        \n"     \
1537         :                                                               \
1538         : "r" (val), "i" (mask));                                       \
1539 } while (0)
1540
1541 #define mflo0()                                                         \
1542 ({                                                                      \
1543         long mflo0;                                                     \
1544         __asm__(                                                        \
1545         "       .set push                                       \n"     \
1546         "       .set dsp                                        \n"     \
1547         "       mflo %0, $ac0                                   \n"     \
1548         "       .set pop                                        \n"     \
1549         : "=r" (mflo0));                                                \
1550         mflo0;                                                          \
1551 })
1552
1553 #define mflo1()                                                         \
1554 ({                                                                      \
1555         long mflo1;                                                     \
1556         __asm__(                                                        \
1557         "       .set push                                       \n"     \
1558         "       .set dsp                                        \n"     \
1559         "       mflo %0, $ac1                                   \n"     \
1560         "       .set pop                                        \n"     \
1561         : "=r" (mflo1));                                                \
1562         mflo1;                                                          \
1563 })
1564
1565 #define mflo2()                                                         \
1566 ({                                                                      \
1567         long mflo2;                                                     \
1568         __asm__(                                                        \
1569         "       .set push                                       \n"     \
1570         "       .set dsp                                        \n"     \
1571         "       mflo %0, $ac2                                   \n"     \
1572         "       .set pop                                        \n"     \
1573         : "=r" (mflo2));                                                \
1574         mflo2;                                                          \
1575 })
1576
1577 #define mflo3()                                                         \
1578 ({                                                                      \
1579         long mflo3;                                                     \
1580         __asm__(                                                        \
1581         "       .set push                                       \n"     \
1582         "       .set dsp                                        \n"     \
1583         "       mflo %0, $ac3                                   \n"     \
1584         "       .set pop                                        \n"     \
1585         : "=r" (mflo3));                                                \
1586         mflo3;                                                          \
1587 })
1588
1589 #define mfhi0()                                                         \
1590 ({                                                                      \
1591         long mfhi0;                                                     \
1592         __asm__(                                                        \
1593         "       .set push                                       \n"     \
1594         "       .set dsp                                        \n"     \
1595         "       mfhi %0, $ac0                                   \n"     \
1596         "       .set pop                                        \n"     \
1597         : "=r" (mfhi0));                                                \
1598         mfhi0;                                                          \
1599 })
1600
1601 #define mfhi1()                                                         \
1602 ({                                                                      \
1603         long mfhi1;                                                     \
1604         __asm__(                                                        \
1605         "       .set push                                       \n"     \
1606         "       .set dsp                                        \n"     \
1607         "       mfhi %0, $ac1                                   \n"     \
1608         "       .set pop                                        \n"     \
1609         : "=r" (mfhi1));                                                \
1610         mfhi1;                                                          \
1611 })
1612
1613 #define mfhi2()                                                         \
1614 ({                                                                      \
1615         long mfhi2;                                                     \
1616         __asm__(                                                        \
1617         "       .set push                                       \n"     \
1618         "       .set dsp                                        \n"     \
1619         "       mfhi %0, $ac2                                   \n"     \
1620         "       .set pop                                        \n"     \
1621         : "=r" (mfhi2));                                                \
1622         mfhi2;                                                          \
1623 })
1624
1625 #define mfhi3()                                                         \
1626 ({                                                                      \
1627         long mfhi3;                                                     \
1628         __asm__(                                                        \
1629         "       .set push                                       \n"     \
1630         "       .set dsp                                        \n"     \
1631         "       mfhi %0, $ac3                                   \n"     \
1632         "       .set pop                                        \n"     \
1633         : "=r" (mfhi3));                                                \
1634         mfhi3;                                                          \
1635 })
1636
1637
1638 #define mtlo0(x)                                                        \
1639 ({                                                                      \
1640         __asm__(                                                        \
1641         "       .set push                                       \n"     \
1642         "       .set dsp                                        \n"     \
1643         "       mtlo %0, $ac0                                   \n"     \
1644         "       .set pop                                        \n"     \
1645         :                                                               \
1646         : "r" (x));                                                     \
1647 })
1648
1649 #define mtlo1(x)                                                        \
1650 ({                                                                      \
1651         __asm__(                                                        \
1652         "       .set push                                       \n"     \
1653         "       .set dsp                                        \n"     \
1654         "       mtlo %0, $ac1                                   \n"     \
1655         "       .set pop                                        \n"     \
1656         :                                                               \
1657         : "r" (x));                                                     \
1658 })
1659
1660 #define mtlo2(x)                                                        \
1661 ({                                                                      \
1662         __asm__(                                                        \
1663         "       .set push                                       \n"     \
1664         "       .set dsp                                        \n"     \
1665         "       mtlo %0, $ac2                                   \n"     \
1666         "       .set pop                                        \n"     \
1667         :                                                               \
1668         : "r" (x));                                                     \
1669 })
1670
1671 #define mtlo3(x)                                                        \
1672 ({                                                                      \
1673         __asm__(                                                        \
1674         "       .set push                                       \n"     \
1675         "       .set dsp                                        \n"     \
1676         "       mtlo %0, $ac3                                   \n"     \
1677         "       .set pop                                        \n"     \
1678         :                                                               \
1679         : "r" (x));                                                     \
1680 })
1681
1682 #define mthi0(x)                                                        \
1683 ({                                                                      \
1684         __asm__(                                                        \
1685         "       .set push                                       \n"     \
1686         "       .set dsp                                        \n"     \
1687         "       mthi %0, $ac0                                   \n"     \
1688         "       .set pop                                        \n"     \
1689         :                                                               \
1690         : "r" (x));                                                     \
1691 })
1692
1693 #define mthi1(x)                                                        \
1694 ({                                                                      \
1695         __asm__(                                                        \
1696         "       .set push                                       \n"     \
1697         "       .set dsp                                        \n"     \
1698         "       mthi %0, $ac1                                   \n"     \
1699         "       .set pop                                        \n"     \
1700         :                                                               \
1701         : "r" (x));                                                     \
1702 })
1703
1704 #define mthi2(x)                                                        \
1705 ({                                                                      \
1706         __asm__(                                                        \
1707         "       .set push                                       \n"     \
1708         "       .set dsp                                        \n"     \
1709         "       mthi %0, $ac2                                   \n"     \
1710         "       .set pop                                        \n"     \
1711         :                                                               \
1712         : "r" (x));                                                     \
1713 })
1714
1715 #define mthi3(x)                                                        \
1716 ({                                                                      \
1717         __asm__(                                                        \
1718         "       .set push                                       \n"     \
1719         "       .set dsp                                        \n"     \
1720         "       mthi %0, $ac3                                   \n"     \
1721         "       .set pop                                        \n"     \
1722         :                                                               \
1723         : "r" (x));                                                     \
1724 })
1725
1726 #else
1727
1728 #ifdef CONFIG_CPU_MICROMIPS
1729 #define rddsp(mask)                                                     \
1730 ({                                                                      \
1731         unsigned int __res;                                             \
1732                                                                         \
1733         __asm__ __volatile__(                                           \
1734         "       .set    push                                    \n"     \
1735         "       .set    noat                                    \n"     \
1736         "       # rddsp $1, %x1                                 \n"     \
1737         "       .hword  ((0x0020067c | (%x1 << 14)) >> 16)      \n"     \
1738         "       .hword  ((0x0020067c | (%x1 << 14)) & 0xffff)   \n"     \
1739         "       move    %0, $1                                  \n"     \
1740         "       .set    pop                                     \n"     \
1741         : "=r" (__res)                                                  \
1742         : "i" (mask));                                                  \
1743         __res;                                                          \
1744 })
1745
1746 #define wrdsp(val, mask)                                                \
1747 do {                                                                    \
1748         __asm__ __volatile__(                                           \
1749         "       .set    push                                    \n"     \
1750         "       .set    noat                                    \n"     \
1751         "       move    $1, %0                                  \n"     \
1752         "       # wrdsp $1, %x1                                 \n"     \
1753         "       .hword  ((0x0020167c | (%x1 << 14)) >> 16)      \n"     \
1754         "       .hword  ((0x0020167c | (%x1 << 14)) & 0xffff)   \n"     \
1755         "       .set    pop                                     \n"     \
1756         :                                                               \
1757         : "r" (val), "i" (mask));                                       \
1758 } while (0)
1759
1760 #define _umips_dsp_mfxxx(ins)                                           \
1761 ({                                                                      \
1762         unsigned long __treg;                                           \
1763                                                                         \
1764         __asm__ __volatile__(                                           \
1765         "       .set    push                                    \n"     \
1766         "       .set    noat                                    \n"     \
1767         "       .hword  0x0001                                  \n"     \
1768         "       .hword  %x1                                     \n"     \
1769         "       move    %0, $1                                  \n"     \
1770         "       .set    pop                                     \n"     \
1771         : "=r" (__treg)                                                 \
1772         : "i" (ins));                                                   \
1773         __treg;                                                         \
1774 })
1775
1776 #define _umips_dsp_mtxxx(val, ins)                                      \
1777 do {                                                                    \
1778         __asm__ __volatile__(                                           \
1779         "       .set    push                                    \n"     \
1780         "       .set    noat                                    \n"     \
1781         "       move    $1, %0                                  \n"     \
1782         "       .hword  0x0001                                  \n"     \
1783         "       .hword  %x1                                     \n"     \
1784         "       .set    pop                                     \n"     \
1785         :                                                               \
1786         : "r" (val), "i" (ins));                                        \
1787 } while (0)
1788
1789 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1790 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1791
1792 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1793 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1794
1795 #define mflo0() _umips_dsp_mflo(0)
1796 #define mflo1() _umips_dsp_mflo(1)
1797 #define mflo2() _umips_dsp_mflo(2)
1798 #define mflo3() _umips_dsp_mflo(3)
1799
1800 #define mfhi0() _umips_dsp_mfhi(0)
1801 #define mfhi1() _umips_dsp_mfhi(1)
1802 #define mfhi2() _umips_dsp_mfhi(2)
1803 #define mfhi3() _umips_dsp_mfhi(3)
1804
1805 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1806 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1807 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1808 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1809
1810 #define mthi0(x) _umips_dsp_mthi(x, 0)
1811 #define mthi1(x) _umips_dsp_mthi(x, 1)
1812 #define mthi2(x) _umips_dsp_mthi(x, 2)
1813 #define mthi3(x) _umips_dsp_mthi(x, 3)
1814
1815 #else  /* !CONFIG_CPU_MICROMIPS */
1816 #define rddsp(mask)                                                     \
1817 ({                                                                      \
1818         unsigned int __res;                                             \
1819                                                                         \
1820         __asm__ __volatile__(                                           \
1821         "       .set    push                            \n"             \
1822         "       .set    noat                            \n"             \
1823         "       # rddsp $1, %x1                         \n"             \
1824         "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
1825         "       move    %0, $1                          \n"             \
1826         "       .set    pop                             \n"             \
1827         : "=r" (__res)                                                  \
1828         : "i" (mask));                                                  \
1829         __res;                                                          \
1830 })
1831
1832 #define wrdsp(val, mask)                                                \
1833 do {                                                                    \
1834         __asm__ __volatile__(                                           \
1835         "       .set    push                                    \n"     \
1836         "       .set    noat                                    \n"     \
1837         "       move    $1, %0                                  \n"     \
1838         "       # wrdsp $1, %x1                                 \n"     \
1839         "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
1840         "       .set    pop                                     \n"     \
1841         :                                                               \
1842         : "r" (val), "i" (mask));                                       \
1843 } while (0)
1844
1845 #define _dsp_mfxxx(ins)                                                 \
1846 ({                                                                      \
1847         unsigned long __treg;                                           \
1848                                                                         \
1849         __asm__ __volatile__(                                           \
1850         "       .set    push                                    \n"     \
1851         "       .set    noat                                    \n"     \
1852         "       .word   (0x00000810 | %1)                       \n"     \
1853         "       move    %0, $1                                  \n"     \
1854         "       .set    pop                                     \n"     \
1855         : "=r" (__treg)                                                 \
1856         : "i" (ins));                                                   \
1857         __treg;                                                         \
1858 })
1859
1860 #define _dsp_mtxxx(val, ins)                                            \
1861 do {                                                                    \
1862         __asm__ __volatile__(                                           \
1863         "       .set    push                                    \n"     \
1864         "       .set    noat                                    \n"     \
1865         "       move    $1, %0                                  \n"     \
1866         "       .word   (0x00200011 | %1)                       \n"     \
1867         "       .set    pop                                     \n"     \
1868         :                                                               \
1869         : "r" (val), "i" (ins));                                        \
1870 } while (0)
1871
1872 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1873 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1874
1875 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1876 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1877
1878 #define mflo0() _dsp_mflo(0)
1879 #define mflo1() _dsp_mflo(1)
1880 #define mflo2() _dsp_mflo(2)
1881 #define mflo3() _dsp_mflo(3)
1882
1883 #define mfhi0() _dsp_mfhi(0)
1884 #define mfhi1() _dsp_mfhi(1)
1885 #define mfhi2() _dsp_mfhi(2)
1886 #define mfhi3() _dsp_mfhi(3)
1887
1888 #define mtlo0(x) _dsp_mtlo(x, 0)
1889 #define mtlo1(x) _dsp_mtlo(x, 1)
1890 #define mtlo2(x) _dsp_mtlo(x, 2)
1891 #define mtlo3(x) _dsp_mtlo(x, 3)
1892
1893 #define mthi0(x) _dsp_mthi(x, 0)
1894 #define mthi1(x) _dsp_mthi(x, 1)
1895 #define mthi2(x) _dsp_mthi(x, 2)
1896 #define mthi3(x) _dsp_mthi(x, 3)
1897
1898 #endif /* CONFIG_CPU_MICROMIPS */
1899 #endif
1900
1901 /*
1902  * TLB operations.
1903  *
1904  * It is responsibility of the caller to take care of any TLB hazards.
1905  */
1906 static inline void tlb_probe(void)
1907 {
1908         __asm__ __volatile__(
1909                 ".set noreorder\n\t"
1910                 "tlbp\n\t"
1911                 ".set reorder");
1912 }
1913
1914 static inline void tlb_read(void)
1915 {
1916 #if MIPS34K_MISSED_ITLB_WAR
1917         int res = 0;
1918
1919         __asm__ __volatile__(
1920         "       .set    push                                    \n"
1921         "       .set    noreorder                               \n"
1922         "       .set    noat                                    \n"
1923         "       .set    mips32r2                                \n"
1924         "       .word   0x41610001              # dvpe $1       \n"
1925         "       move    %0, $1                                  \n"
1926         "       ehb                                             \n"
1927         "       .set    pop                                     \n"
1928         : "=r" (res));
1929
1930         instruction_hazard();
1931 #endif
1932
1933         __asm__ __volatile__(
1934                 ".set noreorder\n\t"
1935                 "tlbr\n\t"
1936                 ".set reorder");
1937
1938 #if MIPS34K_MISSED_ITLB_WAR
1939         if ((res & _ULCAST_(1)))
1940                 __asm__ __volatile__(
1941                 "       .set    push                            \n"
1942                 "       .set    noreorder                       \n"
1943                 "       .set    noat                            \n"
1944                 "       .set    mips32r2                        \n"
1945                 "       .word   0x41600021      # evpe          \n"
1946                 "       ehb                                     \n"
1947                 "       .set    pop                             \n");
1948 #endif
1949 }
1950
1951 static inline void tlb_write_indexed(void)
1952 {
1953         __asm__ __volatile__(
1954                 ".set noreorder\n\t"
1955                 "tlbwi\n\t"
1956                 ".set reorder");
1957 }
1958
1959 static inline void tlb_write_random(void)
1960 {
1961         __asm__ __volatile__(
1962                 ".set noreorder\n\t"
1963                 "tlbwr\n\t"
1964                 ".set reorder");
1965 }
1966
1967 /*
1968  * Manipulate bits in a c0 register.
1969  */
1970 #define __BUILD_SET_C0(name)                                    \
1971 static inline unsigned int                                      \
1972 set_c0_##name(unsigned int set)                                 \
1973 {                                                               \
1974         unsigned int res, new;                                  \
1975                                                                 \
1976         res = read_c0_##name();                                 \
1977         new = res | set;                                        \
1978         write_c0_##name(new);                                   \
1979                                                                 \
1980         return res;                                             \
1981 }                                                               \
1982                                                                 \
1983 static inline unsigned int                                      \
1984 clear_c0_##name(unsigned int clear)                             \
1985 {                                                               \
1986         unsigned int res, new;                                  \
1987                                                                 \
1988         res = read_c0_##name();                                 \
1989         new = res & ~clear;                                     \
1990         write_c0_##name(new);                                   \
1991                                                                 \
1992         return res;                                             \
1993 }                                                               \
1994                                                                 \
1995 static inline unsigned int                                      \
1996 change_c0_##name(unsigned int change, unsigned int val)         \
1997 {                                                               \
1998         unsigned int res, new;                                  \
1999                                                                 \
2000         res = read_c0_##name();                                 \
2001         new = res & ~change;                                    \
2002         new |= (val & change);                                  \
2003         write_c0_##name(new);                                   \
2004                                                                 \
2005         return res;                                             \
2006 }
2007
2008 __BUILD_SET_C0(status)
2009 __BUILD_SET_C0(cause)
2010 __BUILD_SET_C0(config)
2011 __BUILD_SET_C0(config5)
2012 __BUILD_SET_C0(intcontrol)
2013 __BUILD_SET_C0(intctl)
2014 __BUILD_SET_C0(srsmap)
2015 __BUILD_SET_C0(pagegrain)
2016 __BUILD_SET_C0(brcm_config_0)
2017 __BUILD_SET_C0(brcm_bus_pll)
2018 __BUILD_SET_C0(brcm_reset)
2019 __BUILD_SET_C0(brcm_cmt_intr)
2020 __BUILD_SET_C0(brcm_cmt_ctrl)
2021 __BUILD_SET_C0(brcm_config)
2022 __BUILD_SET_C0(brcm_mode)
2023
2024 /*
2025  * Return low 10 bits of ebase.
2026  * Note that under KVM (MIPSVZ) this returns vcpu id.
2027  */
2028 static inline unsigned int get_ebase_cpunum(void)
2029 {
2030         return read_c0_ebase() & 0x3ff;
2031 }
2032
2033 #endif /* !__ASSEMBLY__ */
2034
2035 #endif /* _ASM_MIPSREGS_H */